1 /* $OpenBSD: cia.c,v 1.27 2022/03/13 08:04:13 mpi Exp $ */
2 /* $NetBSD: cia.c,v 1.56 2000/06/29 08:58:45 mrg Exp $ */
3
4 /*-
5 * Copyright (c) 1998, 2000 The NetBSD Foundation, Inc.
6 * All rights reserved.
7 *
8 * This code is derived from software contributed to The NetBSD Foundation
9 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
10 * NASA Ames Research Center.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 /*
35 * Copyright (c) 1995, 1996 Carnegie-Mellon University.
36 * All rights reserved.
37 *
38 * Author: Chris G. Demetriou
39 *
40 * Permission to use, copy, modify and distribute this software and
41 * its documentation is hereby granted, provided that both the copyright
42 * notice and this permission notice appear in all copies of the
43 * software, derivative works or modified versions, and any portions
44 * thereof, and that both notices appear in supporting documentation.
45 *
46 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
47 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
48 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
49 *
50 * Carnegie Mellon requests users of this software to return to
51 *
52 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
53 * School of Computer Science
54 * Carnegie Mellon University
55 * Pittsburgh PA 15213-3890
56 *
57 * any improvements or extensions that they make and grant Carnegie the
58 * rights to redistribute these changes.
59 */
60
61 #include <sys/param.h>
62 #include <sys/systm.h>
63 #include <sys/kernel.h>
64 #include <sys/malloc.h>
65 #include <sys/device.h>
66 #include <uvm/uvm_extern.h>
67
68 #include <machine/autoconf.h>
69 #include <machine/rpb.h>
70
71 #include <dev/isa/isareg.h>
72 #include <dev/isa/isavar.h>
73
74 #include <dev/pci/pcireg.h>
75 #include <dev/pci/pcivar.h>
76 #include <alpha/pci/ciareg.h>
77 #include <alpha/pci/ciavar.h>
78
79 #ifdef DEC_KN20AA
80 #include <alpha/pci/pci_kn20aa.h>
81 #endif
82 #ifdef DEC_EB164
83 #include <alpha/pci/pci_eb164.h>
84 #endif
85 #ifdef DEC_550
86 #include <alpha/pci/pci_550.h>
87 #endif
88 #ifdef DEC_1000A
89 #include <alpha/pci/pci_1000a.h>
90 #endif
91 #ifdef DEC_1000
92 #include <alpha/pci/pci_1000.h>
93 #endif
94
95 int ciamatch(struct device *, void *, void *);
96 void ciaattach(struct device *, struct device *, void *);
97
98 const struct cfattach cia_ca = {
99 sizeof(struct device), ciamatch, ciaattach,
100 };
101
102 struct cfdriver cia_cd = {
103 NULL, "cia", DV_DULL,
104 };
105
106 static int ciaprint(void *, const char *pnp);
107
108 /* There can be only one. */
109 int ciafound;
110 struct cia_config cia_configuration;
111
112 /*
113 * This determines if we attempt to use BWX for PCI bus and config space
114 * access. Some systems, notably with Pyxis, don't fare so well unless
115 * BWX is used.
116 *
117 * EXCEPT! Some devices have a really hard time if BWX is used (WHY?!).
118 * So, we decouple the uses for PCI config space and PCI bus space.
119 *
120 * FURTHERMORE! The Pyxis, most notably earlier revs, really don't
121 * do so well if you don't use BWX for bus access. So we default to
122 * forcing BWX on those chips.
123 *
124 * Geez.
125 */
126
127 #ifndef CIA_PCI_USE_BWX
128 #define CIA_PCI_USE_BWX 1
129 #endif
130
131 #ifndef CIA_BUS_USE_BWX
132 #define CIA_BUS_USE_BWX 1
133 #endif
134
135 #ifndef CIA_PYXIS_FORCE_BWX
136 #define CIA_PYXIS_FORCE_BWX 1
137 #endif
138
139 int cia_pci_use_bwx = CIA_PCI_USE_BWX;
140 int cia_bus_use_bwx = CIA_BUS_USE_BWX;
141 int cia_pyxis_force_bwx = CIA_PYXIS_FORCE_BWX;
142
143 int
ciamatch(parent,match,aux)144 ciamatch(parent, match, aux)
145 struct device *parent;
146 void *match;
147 void *aux;
148 {
149 struct mainbus_attach_args *ma = aux;
150
151 /* Make sure that we're looking for a CIA. */
152 if (strcmp(ma->ma_name, cia_cd.cd_name) != 0)
153 return (0);
154
155 if (ciafound)
156 return (0);
157
158 return (1);
159 }
160
161 /*
162 * Set up the chipset's function pointers.
163 */
164 void
cia_init(ccp,mallocsafe)165 cia_init(ccp, mallocsafe)
166 struct cia_config *ccp;
167 int mallocsafe;
168 {
169 int pci_use_bwx = cia_pci_use_bwx;
170 int bus_use_bwx = cia_bus_use_bwx;
171
172 ccp->cc_hae_mem = REGVAL(CIA_CSR_HAE_MEM);
173 ccp->cc_hae_io = REGVAL(CIA_CSR_HAE_IO);
174 ccp->cc_rev = REGVAL(CIA_CSR_REV) & REV_MASK;
175
176 /*
177 * Determine if we have a Pyxis. Only two systypes can
178 * have this: the EB164 systype (AlphaPC164LX and AlphaPC164SX)
179 * and the DEC_550 systype (Miata).
180 */
181 if ((cputype == ST_EB164 &&
182 (hwrpb->rpb_variation & SV_ST_MASK) >= SV_ST_ALPHAPC164LX_400) ||
183 cputype == ST_DEC_550) {
184 ccp->cc_flags |= CCF_ISPYXIS;
185 if (cia_pyxis_force_bwx)
186 pci_use_bwx = bus_use_bwx = 1;
187 }
188
189 /*
190 * ALCOR/ALCOR2 Revisions >= 2 and Pyxis have the CNFG register.
191 */
192 if (ccp->cc_rev >= 2 || (ccp->cc_flags & CCF_ISPYXIS) != 0)
193 ccp->cc_cnfg = REGVAL(CIA_CSR_CNFG);
194 else
195 ccp->cc_cnfg = 0;
196
197 if (!ccp->cc_initted) {
198 /*
199 * cpu_amask is not initialized if we are invoked during
200 * console initialization.
201 */
202 u_long amask = 0;
203 if (alpha_implver() >= ALPHA_IMPLVER_EV5)
204 amask =
205 (~alpha_amask(ALPHA_AMASK_ALL)) & ALPHA_AMASK_ALL;
206
207 /*
208 * Use BWX iff:
209 *
210 * - It hasn't been disabled by the user,
211 * - it's enabled in CNFG,
212 * - we're implementation version ev5,
213 * - BWX is enabled in the CPU's capabilities mask (yes,
214 * the bit is really cleared if the capability exists...)
215 */
216 if ((pci_use_bwx || bus_use_bwx) &&
217 (ccp->cc_cnfg & CNFG_BWEN) != 0 &&
218 (amask & ALPHA_AMASK_BWX) != 0) {
219 u_int32_t ctrl;
220
221 if (pci_use_bwx)
222 ccp->cc_flags |= CCF_PCI_USE_BWX;
223 if (bus_use_bwx)
224 ccp->cc_flags |= CCF_BUS_USE_BWX;
225
226 /*
227 * For whatever reason, the firmware seems to enable PCI
228 * loopback mode if it also enables BWX. Make sure it's
229 * enabled if we have an old, buggy firmware rev.
230 */
231 alpha_mb();
232 ctrl = REGVAL(CIA_CSR_CTRL);
233 if ((ctrl & CTRL_PCI_LOOP_EN) == 0) {
234 REGVAL(CIA_CSR_CTRL) = ctrl | CTRL_PCI_LOOP_EN;
235 alpha_mb();
236 }
237 }
238
239 /* don't do these twice since they set up extents */
240 if (ccp->cc_flags & CCF_BUS_USE_BWX) {
241 cia_bwx_bus_io_init(&ccp->cc_iot, ccp);
242 cia_bwx_bus_mem_init(&ccp->cc_memt, ccp);
243 } else {
244 cia_bus_io_init(&ccp->cc_iot, ccp);
245 cia_bus_mem_init(&ccp->cc_memt, ccp);
246 }
247 }
248 ccp->cc_mallocsafe = mallocsafe;
249
250 cia_pci_init(&ccp->cc_pc, ccp);
251 alpha_pci_chipset = &ccp->cc_pc;
252 alpha_pci_chipset->pc_name = "cia";
253 alpha_pci_chipset->pc_dense = CIA_PCI_DENSE;
254 alpha_pci_chipset->pc_hae_mask = 7L << 29;
255 if (ccp->cc_flags & CCF_BUS_USE_BWX) {
256 alpha_pci_chipset->pc_mem = CIA_EV56_BWMEM;
257 alpha_pci_chipset->pc_ports = CIA_EV56_BWIO;
258 alpha_pci_chipset->pc_bwx = 1;
259 } else {
260 alpha_pci_chipset->pc_mem = CIA_PCI_SMEM1;
261 alpha_pci_chipset->pc_ports = CIA_PCI_SIO1;
262 alpha_pci_chipset->pc_bwx = 0;
263 }
264
265 ccp->cc_initted = 1;
266 }
267
268 void
ciaattach(parent,self,aux)269 ciaattach(parent, self, aux)
270 struct device *parent, *self;
271 void *aux;
272 {
273 struct cia_config *ccp;
274 struct pcibus_attach_args pba;
275 const char *name;
276 int pass;
277
278 /* note that we've attached the chipset; can't have 2 CIAs. */
279 ciafound = 1;
280
281 /*
282 * set up the chipset's info; done once at console init time
283 * (maybe), but we must do it here as well to take care of things
284 * that need to use memory allocation.
285 */
286 ccp = &cia_configuration;
287 cia_init(ccp, 1);
288
289 if (ccp->cc_flags & CCF_ISPYXIS) {
290 name = "Pyxis";
291 pass = ccp->cc_rev;
292 } else {
293 name = "ALCOR/ALCOR2";
294 pass = ccp->cc_rev + 1;
295 }
296
297 printf(": DECchip 2117x Core Logic Chipset (%s), pass %d\n",
298 name, pass);
299
300 if (ccp->cc_cnfg)
301 printf("%s: extended capabilities: %b\n", self->dv_xname,
302 ccp->cc_cnfg, CIA_CSR_CNFG_BITS);
303
304 switch (ccp->cc_flags & (CCF_PCI_USE_BWX|CCF_BUS_USE_BWX)) {
305 case CCF_PCI_USE_BWX|CCF_BUS_USE_BWX:
306 name = "PCI config and bus";
307 break;
308 case CCF_PCI_USE_BWX:
309 name = "PCI config";
310 break;
311 case CCF_BUS_USE_BWX:
312 name = "bus";
313 break;
314 default:
315 name = NULL;
316 break;
317 }
318 if (name != NULL)
319 printf("%s: using BWX for %s access\n", self->dv_xname, name);
320
321 #ifdef DEC_550
322 if (cputype == ST_DEC_550 &&
323 (hwrpb->rpb_variation & SV_ST_MASK) < SV_ST_MIATA_1_5) {
324 /*
325 * Miata 1 systems have a bug: DMA cannot cross
326 * an 8k boundary! Make sure PCI read prefetching
327 * is disabled on these chips. Note that secondary
328 * PCI busses don't have this problem, because of
329 * the way PPBs handle PCI read requests.
330 *
331 * In the 21174 Technical Reference Manual, this is
332 * actually documented as "Pyxis Pass 1", but apparently
333 * there are chips that report themselves as "Pass 1"
334 * which do not have the bug! Miatas with the Cypress
335 * PCI-ISA bridge (i.e. Miata 1.5 and Miata 2) do not
336 * have the bug, so we use this check.
337 *
338 * NOTE: This bug is actually worked around in cia_dma.c,
339 * when direct-mapped DMA maps are created.
340 *
341 * XXX WE NEED TO THINK ABOUT HOW TO HANDLE THIS FOR
342 * XXX SGMAP DMA MAPPINGS!
343 */
344 u_int32_t ctrl;
345
346 /* XXX no bets... */
347 printf("%s: WARNING: Pyxis pass 1 DMA bug; no bets...\n",
348 self->dv_xname);
349
350 ccp->cc_flags |= CCF_PYXISBUG;
351
352 alpha_mb();
353 ctrl = REGVAL(CIA_CSR_CTRL);
354 ctrl &= ~(CTRL_RD_TYPE|CTRL_RL_TYPE|CTRL_RM_TYPE);
355 REGVAL(CIA_CSR_CTRL) = ctrl;
356 alpha_mb();
357 }
358 #endif /* DEC_550 */
359
360 cia_dma_init(ccp);
361
362 switch (cputype) {
363 #ifdef DEC_KN20AA
364 case ST_DEC_KN20AA:
365 pci_kn20aa_pickintr(ccp);
366 break;
367 #endif
368
369 #ifdef DEC_EB164
370 case ST_EB164:
371 pci_eb164_pickintr(ccp);
372 break;
373 #endif
374
375 #ifdef DEC_550
376 case ST_DEC_550:
377 pci_550_pickintr(ccp);
378 break;
379 #endif
380
381 #ifdef DEC_1000A
382 case ST_DEC_1000A:
383 pci_1000a_pickintr(ccp, &ccp->cc_iot, &ccp->cc_memt,
384 &ccp->cc_pc);
385 break;
386 #endif
387
388 #ifdef DEC_1000
389 case ST_DEC_1000:
390 pci_1000_pickintr(ccp, &ccp->cc_iot, &ccp->cc_memt,
391 &ccp->cc_pc);
392 break;
393 #endif
394
395 default:
396 panic("ciaattach: shouldn't be here, really...");
397 }
398
399 bzero(&pba, sizeof(pba));
400 pba.pba_busname = "pci";
401 pba.pba_iot = &ccp->cc_iot;
402 pba.pba_memt = &ccp->cc_memt;
403 pba.pba_dmat =
404 alphabus_dma_get_tag(&ccp->cc_dmat_direct, ALPHA_BUS_PCI);
405 pba.pba_pc = &ccp->cc_pc;
406 pba.pba_domain = pci_ndomains++;
407 pba.pba_bus = 0;
408 #ifdef notyet
409 pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED;
410 if ((ccp->cc_flags & CCF_PYXISBUG) == 0)
411 pba.pba_flags |= PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY |
412 PCI_FLAGS_MWI_OKAY;
413 #endif
414 config_found(self, &pba, ciaprint);
415 }
416
417 static int
ciaprint(aux,pnp)418 ciaprint(aux, pnp)
419 void *aux;
420 const char *pnp;
421 {
422 register struct pcibus_attach_args *pba = aux;
423
424 /* only PCIs can attach to CIAs; easy. */
425 if (pnp)
426 printf("%s at %s", pba->pba_busname, pnp);
427 printf(" bus %d", pba->pba_bus);
428 return (UNCONF);
429 }
430
431 void
cia_pyxis_intr_enable(irq,onoff)432 cia_pyxis_intr_enable(irq, onoff)
433 int irq, onoff;
434 {
435 u_int64_t imask;
436 int s;
437
438 #if 0
439 printf("cia_pyxis_intr_enable: %s %d\n",
440 onoff ? "enabling" : "disabling", irq);
441 #endif
442
443 s = splhigh();
444 alpha_mb();
445 imask = REGVAL64(PYXIS_INT_MASK);
446 if (onoff)
447 imask |= (1UL << irq);
448 else
449 imask &= ~(1UL << irq);
450 REGVAL64(PYXIS_INT_MASK) = imask;
451 alpha_mb();
452 splx(s);
453 }
454