| /dports/cad/verilator/verilator-4.216/test_regress/t/ |
| H A D | t_clk_concat.v | 75 input clk1 /*verilator clocker*/, port
79 input clk1, port
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| H A D | t_clk_2in.v | 72 wire clk1 = clks[1]; net
75 wire clk1 = c1; net
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| H A D | t_flag_csplit_eval.v | 14 input clk1; port
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| H A D | t_clk_2in.cpp | 18 void clockit(int clk1, int clk0) { in clockit()
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| H A D | t_clk_concat3.v | 78 input clk1 /*verilator clocker*/, port
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| /dports/cad/ghdl/ghdl-1.0.0/testsuite/gna/issue1588/ |
| H A D | tent.vhdl | 41 signal clk1 : std_logic := '1'; signal
90 signal clk1 : std_logic := '1'; signal
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| /dports/science/openmx/openmx3.8/source/liberi-091216/test/selfcheck/ |
| H A D | demo_test4.c | 24 clock_t clk0, clk1; in demo() local
48 clock_t clk0, clk1; in demo_test4() local
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| H A D | demo_test2.c | 22 clock_t clk0, clk1; in demo() local
44 clock_t clk0, clk1; in demo_test2() local
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| /dports/cad/openroad/OpenROAD-2.0/src/dbSta/test/ |
| H A D | constant1.v | 2 input in1, clk1; port
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| H A D | power1.v | 9 input clk1; port
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| H A D | hier1.v | 2 input in, clk1, clk2; port
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| H A D | reg1.v | 2 input in1, in2, clk1, clk2, clk3; port
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| H A D | example1.v | 2 input in1, in2, clk1, clk2, clk3; port
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| H A D | read_verilog6.v | 2 input in1, in2, clk1, clk2, clk3; port
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| H A D | read_verilog4.v | 2 input in1, in2, clk1, clk2, clk3; port
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| /dports/cad/openroad/OpenROAD-2.0/src/rsz/test/ |
| H A D | report_floating_nets1.v | 2 input in1, clk1, clk2, clk3; port
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| /dports/cad/ghdl/ghdl-1.0.0/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/ |
| H A D | tb_tri_state_reg.vhd | 29 signal clk1, clk2, oe1, oe2 : bit := '0'; signal
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| /dports/cad/openroad/OpenROAD-2.0/src/ifp/test/ |
| H A D | reg1.v | 2 input in1, in2, clk1, clk2, clk3; port
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| H A D | reg2.v | 2 input in1, in2, clk1, clk2, clk3, reset; port
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| /dports/cad/openroad/OpenROAD-2.0/src/sta/examples/ |
| H A D | example1.v | 2 input in1, in2, clk1, clk2, clk3; port
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| /dports/cad/ghdl/ghdl-1.0.0/testsuite/vests/vhdl-93/ashenden/compliant/ |
| H A D | ch_16_fg_16_05.vhd | 74 signal clk1, clk2, oe1, oe2 : bit := '0'; signal
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| /dports/cad/gplcver/gplcver-2.12a.src/tests_and_examples/examples.acc/ |
| H A D | accxldrvtst.v | 20 input clk, clk1, d, clr, set; port
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| /dports/emulators/mess/mame-mame0226/src/devices/machine/ |
| H A D | hd63450.h | 29 …void set_clocks(const attotime &clk1, const attotime &clk2, const attotime &clk3, const attotime &… in set_clocks()
36 …void set_burst_clocks(const attotime &clk1, const attotime &clk2, const attotime &clk3, const atto… in set_burst_clocks()
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| /dports/emulators/mame/mame-mame0226/src/devices/machine/ |
| H A D | hd63450.h | 29 …void set_clocks(const attotime &clk1, const attotime &clk2, const attotime &clk3, const attotime &… in set_clocks()
36 …void set_burst_clocks(const attotime &clk1, const attotime &clk2, const attotime &clk3, const atto… in set_burst_clocks()
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| /dports/devel/universal-ctags/ctags-p5.9.20211128.0/Units/parser-verilog.r/systemverilog-clocking.d/ |
| H A D | input.sv | 54 logic clk1, clk2; register
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