1 /* $OpenBSD: cs4280.c,v 1.63 2024/09/01 03:08:56 jsg Exp $ */
2 /* $NetBSD: cs4280.c,v 1.5 2000/06/26 04:56:23 simonb Exp $ */
3
4 /*
5 * Copyright (c) 1999, 2000 Tatoku Ogaito. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Tatoku Ogaito
18 * for the NetBSD Project.
19 * 4. The name of the author may not be used to endorse or promote products
20 * derived from this software without specific prior written permission
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 /*
35 * Cirrus Logic CS4280 (and maybe CS461x) driver.
36 * Data sheets can be found
37 * http://www.cirrus.com/ftp/pubs/4280.pdf
38 * http://www.cirrus.com/ftp/pubs/4297.pdf
39 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.pdf
40 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.doc
41 */
42
43 /*
44 * TODO
45 * Implement MIDI
46 * Joystick support
47 */
48
49 #ifdef CS4280_DEBUG
50 #ifndef MIDI_READY
51 #define MIDI_READY
52 #endif /* ! MIDI_READY */
53 #endif
54
55 #ifdef MIDI_READY
56 #include "midi.h"
57 #endif
58
59 #if defined(CS4280_DEBUG)
60 #define DPRINTF(x) if (cs4280debug) printf x
61 #define DPRINTFN(n,x) if (cs4280debug>(n)) printf x
62 int cs4280debug = 0;
63 #else
64 #define DPRINTF(x)
65 #define DPRINTFN(n,x)
66 #endif
67
68 #include <sys/param.h>
69 #include <sys/systm.h>
70 #include <sys/malloc.h>
71 #include <sys/device.h>
72
73 #include <dev/pci/pcidevs.h>
74 #include <dev/pci/pcivar.h>
75 #include <dev/pci/cs4280reg.h>
76
77 #include <sys/audioio.h>
78 #include <dev/audio_if.h>
79
80 #include <dev/ic/ac97.h>
81
82 #include <machine/bus.h>
83
84 #define CSCC_PCI_BA0 0x10
85 #define CSCC_PCI_BA1 0x14
86
87 struct cs4280_dma {
88 bus_dmamap_t map;
89 caddr_t addr; /* real dma buffer */
90 caddr_t dum; /* dummy buffer for audio driver */
91 bus_dma_segment_t segs[1];
92 int nsegs;
93 size_t size;
94 struct cs4280_dma *next;
95 };
96 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr)
97 #define BUFADDR(p) ((void *)((p)->dum))
98 #define KERNADDR(p) ((void *)((p)->addr))
99
100 /*
101 * Software state
102 */
103 struct cs4280_softc {
104 struct device sc_dev;
105
106 pci_intr_handle_t * sc_ih;
107
108 /* I/O (BA0) */
109 bus_space_tag_t ba0t;
110 bus_space_handle_t ba0h;
111
112 /* BA1 */
113 bus_space_tag_t ba1t;
114 bus_space_handle_t ba1h;
115
116 /* DMA */
117 bus_dma_tag_t sc_dmatag;
118 struct cs4280_dma *sc_dmas;
119
120 void (*sc_pintr)(void *); /* dma completion intr handler */
121 void *sc_parg; /* arg for sc_intr() */
122 char *sc_ps, *sc_pe, *sc_pn;
123 int sc_pcount;
124 int sc_pi;
125 struct cs4280_dma *sc_pdma;
126 char *sc_pbuf;
127 #ifdef DIAGNOSTIC
128 char sc_prun;
129 #endif
130
131 void (*sc_rintr)(void *); /* dma completion intr handler */
132 void *sc_rarg; /* arg for sc_intr() */
133 char *sc_rs, *sc_re, *sc_rn;
134 int sc_rcount;
135 int sc_ri;
136 struct cs4280_dma *sc_rdma;
137 char *sc_rbuf;
138 int sc_rparam; /* record format */
139 #ifdef DIAGNOSTIC
140 char sc_rrun;
141 #endif
142
143 #if NMIDI > 0
144 void (*sc_iintr)(void *, int); /* midi input ready handler */
145 void (*sc_ointr)(void *); /* midi output ready handler */
146 void *sc_arg;
147 #endif
148
149 u_int32_t pctl;
150 u_int32_t cctl;
151
152 struct ac97_codec_if *codec_if;
153 struct ac97_host_if host_if;
154
155 u_int16_t ac97_reg[CS4280_SAVE_REG_MAX + 1]; /* Save ac97 registers */
156 };
157
158 #define BA0READ4(sc, r) bus_space_read_4((sc)->ba0t, (sc)->ba0h, (r))
159 #define BA0WRITE4(sc, r, x) bus_space_write_4((sc)->ba0t, (sc)->ba0h, (r), (x))
160 #define BA1READ4(sc, r) bus_space_read_4((sc)->ba1t, (sc)->ba1h, (r))
161 #define BA1WRITE4(sc, r, x) bus_space_write_4((sc)->ba1t, (sc)->ba1h, (r), (x))
162
163 int cs4280_match(struct device *, void *, void *);
164 void cs4280_attach(struct device *, struct device *, void *);
165 int cs4280_activate(struct device *, int);
166 void cs4280_attachhook(struct device *);
167 int cs4280_intr(void *);
168 void cs4280_reset(void *);
169 int cs4280_download_image(struct cs4280_softc *);
170
171 int cs4280_download(struct cs4280_softc *, const u_int32_t *, u_int32_t, u_int32_t);
172 int cs4280_allocmem(struct cs4280_softc *, size_t, size_t,
173 struct cs4280_dma *);
174 int cs4280_freemem(struct cs4280_softc *, struct cs4280_dma *);
175
176 #ifdef CS4280_DEBUG
177 int cs4280_check_images(struct cs4280_softc *);
178 int cs4280_checkimage(struct cs4280_softc *, u_int32_t *, u_int32_t,
179 u_int32_t);
180 #endif
181
182 struct cfdriver clcs_cd = {
183 NULL, "clcs", DV_DULL
184 };
185
186 const struct cfattach clcs_ca = {
187 sizeof(struct cs4280_softc), cs4280_match, cs4280_attach, NULL,
188 cs4280_activate
189 };
190
191 int cs4280_init(struct cs4280_softc *, int);
192 int cs4280_init2(struct cs4280_softc *, int);
193 int cs4280_open(void *, int);
194 void cs4280_close(void *);
195
196 int cs4280_set_params(void *, int, int, struct audio_params *, struct audio_params *);
197 int cs4280_round_blocksize(void *, int);
198
199 int cs4280_halt_output(void *);
200 int cs4280_halt_input(void *);
201
202 int cs4280_mixer_set_port(void *, mixer_ctrl_t *);
203 int cs4280_mixer_get_port(void *, mixer_ctrl_t *);
204 int cs4280_query_devinfo(void *addr, mixer_devinfo_t *dip);
205 void *cs4280_malloc(void *, int, size_t, int, int);
206 void cs4280_free(void *, void *, int);
207 int cs4280_trigger_output(void *, void *, void *, int, void (*)(void *),
208 void *, struct audio_params *);
209 int cs4280_trigger_input(void *, void *, void *, int, void (*)(void *),
210 void *, struct audio_params *);
211
212
213 void cs4280_set_dac_rate(struct cs4280_softc *, int );
214 void cs4280_set_adc_rate(struct cs4280_softc *, int );
215 int cs4280_get_portnum_by_name(struct cs4280_softc *, char *, char *,
216 char *);
217 int cs4280_src_wait(struct cs4280_softc *);
218 int cs4280_attach_codec(void *sc, struct ac97_codec_if *);
219 int cs4280_read_codec(void *sc, u_int8_t a, u_int16_t *d);
220 int cs4280_write_codec(void *sc, u_int8_t a, u_int16_t d);
221 void cs4280_reset_codec(void *sc);
222
223 void cs4280_clear_fifos(struct cs4280_softc *);
224
225 #if NMIDI > 0
226 void cs4280_midi_close(void *);
227 void cs4280_midi_getinfo(void *, struct midi_info *);
228 int cs4280_midi_open(void *, int, void (*)(void *, int),
229 void (*)(void *), void *);
230 int cs4280_midi_output(void *, int);
231 #endif
232
233 const struct audio_hw_if cs4280_hw_if = {
234 .open = cs4280_open,
235 .close = cs4280_close,
236 .set_params = cs4280_set_params,
237 .round_blocksize = cs4280_round_blocksize,
238 .halt_output = cs4280_halt_output,
239 .halt_input = cs4280_halt_input,
240 .set_port = cs4280_mixer_set_port,
241 .get_port = cs4280_mixer_get_port,
242 .query_devinfo = cs4280_query_devinfo,
243 .allocm = cs4280_malloc,
244 .freem = cs4280_free,
245 .trigger_output = cs4280_trigger_output,
246 .trigger_input = cs4280_trigger_input,
247 };
248
249 #if NMIDI > 0
250 const struct midi_hw_if cs4280_midi_hw_if = {
251 cs4280_midi_open,
252 cs4280_midi_close,
253 cs4280_midi_output,
254 0, /* flush */
255 cs4280_midi_getinfo,
256 0, /* ioctl */
257 };
258 #endif
259
260
261 const struct pci_matchid cs4280_devices[] = {
262 { PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CS4280 },
263 { PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CS4610 },
264 { PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CS4615 },
265 };
266
267 int
cs4280_match(struct device * parent,void * ma,void * aux)268 cs4280_match(struct device *parent, void *ma, void *aux)
269 {
270 return (pci_matchbyid((struct pci_attach_args *)aux, cs4280_devices,
271 nitems(cs4280_devices)));
272 }
273
274 int
cs4280_read_codec(void * sc_,u_int8_t add,u_int16_t * data)275 cs4280_read_codec(void *sc_, u_int8_t add, u_int16_t *data)
276 {
277 struct cs4280_softc *sc = sc_;
278 int n;
279
280 DPRINTFN(5,("read_codec: add=0x%02x ", add));
281 /*
282 * Make sure that there is not data sitting around from a previous
283 * uncompleted access.
284 */
285 BA0READ4(sc, CS4280_ACSDA);
286
287 /* Set up AC97 control registers. */
288 BA0WRITE4(sc, CS4280_ACCAD, add);
289 BA0WRITE4(sc, CS4280_ACCDA, 0);
290 BA0WRITE4(sc, CS4280_ACCTL,
291 ACCTL_RSTN | ACCTL_ESYN | ACCTL_VFRM | ACCTL_CRW | ACCTL_DCV );
292
293 if (cs4280_src_wait(sc) < 0) {
294 printf("%s: AC97 read prob. (DCV!=0) for add=0x%02x\n",
295 sc->sc_dev.dv_xname, add);
296 return (1);
297 }
298
299 /* wait for valid status bit is active */
300 n = 0;
301 while (!(BA0READ4(sc, CS4280_ACSTS) & ACSTS_VSTS)) {
302 delay(1);
303 while (++n > 1000) {
304 printf("%s: AC97 read fail (VSTS==0) for add=0x%02x\n",
305 sc->sc_dev.dv_xname, add);
306 return (1);
307 }
308 }
309 *data = BA0READ4(sc, CS4280_ACSDA);
310 DPRINTFN(5,("data=0x%04x\n", *data));
311 return (0);
312 }
313
314 int
cs4280_write_codec(void * sc_,u_int8_t add,u_int16_t data)315 cs4280_write_codec(void *sc_, u_int8_t add, u_int16_t data)
316 {
317 struct cs4280_softc *sc = sc_;
318
319 DPRINTFN(5,("write_codec: add=0x%02x data=0x%04x\n", add, data));
320 BA0WRITE4(sc, CS4280_ACCAD, add);
321 BA0WRITE4(sc, CS4280_ACCDA, data);
322 BA0WRITE4(sc, CS4280_ACCTL,
323 ACCTL_RSTN | ACCTL_ESYN | ACCTL_VFRM | ACCTL_DCV );
324
325 if (cs4280_src_wait(sc) < 0) {
326 printf("%s: AC97 write fail (DCV!=0) for add=0x%02x data="
327 "0x%04x\n", sc->sc_dev.dv_xname, add, data);
328 return (1);
329 }
330 return (0);
331 }
332
333 int
cs4280_src_wait(struct cs4280_softc * sc)334 cs4280_src_wait(struct cs4280_softc *sc)
335 {
336 int n;
337
338 n = 0;
339 while ((BA0READ4(sc, CS4280_ACCTL) & ACCTL_DCV)) {
340 delay(1000);
341 if (++n > 1000)
342 return (-1);
343 }
344 return (0);
345 }
346
347
348 void
cs4280_set_adc_rate(struct cs4280_softc * sc,int rate)349 cs4280_set_adc_rate(struct cs4280_softc *sc, int rate)
350 {
351 /* calculate capture rate:
352 *
353 * capture_coefficient_increment = -round(rate*128*65536/48000;
354 * capture_phase_increment = floor(48000*65536*1024/rate);
355 * cx = round(48000*65536*1024 - capture_phase_increment*rate);
356 * cy = floor(cx/200);
357 * capture_sample_rate_correction = cx - 200*cy;
358 * capture_delay = ceil(24*48000/rate);
359 * capture_num_triplets = floor(65536*rate/24000);
360 * capture_group_length = 24000/GCD(rate, 24000);
361 * where GCD means "Greatest Common Divisor".
362 *
363 * capture_coefficient_increment, capture_phase_increment and
364 * capture_num_triplets are 32-bit signed quantities.
365 * capture_sample_rate_correction and capture_group_length are
366 * 16-bit signed quantities.
367 * capture_delay is a 14-bit unsigned quantity.
368 */
369 u_int32_t cci,cpi,cnt,cx,cy, tmp1;
370 u_int16_t csrc, cgl, cdlay;
371
372 /* XXX
373 * Even though, embedded_audio_spec says capture rate range 11025 to
374 * 48000, dhwiface.cpp says,
375 *
376 * "We can only decimate by up to a factor of 1/9th the hardware rate.
377 * Return an error if an attempt is made to stray outside that limit."
378 *
379 * so assume range as 48000/9 to 48000
380 */
381
382 if (rate < 8000)
383 rate = 8000;
384 if (rate > 48000)
385 rate = 48000;
386
387 cx = rate << 16;
388 cci = cx / 48000;
389 cx -= cci * 48000;
390 cx <<= 7;
391 cci <<= 7;
392 cci += cx / 48000;
393 cci = - cci;
394
395 cx = 48000 << 16;
396 cpi = cx / rate;
397 cx -= cpi * rate;
398 cx <<= 10;
399 cpi <<= 10;
400 cy = cx / rate;
401 cpi += cy;
402 cx -= cy * rate;
403
404 cy = cx / 200;
405 csrc = cx - 200*cy;
406
407 cdlay = ((48000 * 24) + rate - 1) / rate;
408 #if 0
409 cdlay &= 0x3fff; /* make sure cdlay is 14-bit */
410 #endif
411
412 cnt = rate << 16;
413 cnt /= 24000;
414
415 cgl = 1;
416 for (tmp1 = 2; tmp1 <= 64; tmp1 *= 2) {
417 if (((rate / tmp1) * tmp1) != rate)
418 cgl *= 2;
419 }
420 if (((rate / 3) * 3) != rate)
421 cgl *= 3;
422 for (tmp1 = 5; tmp1 <= 125; tmp1 *= 5) {
423 if (((rate / tmp1) * tmp1) != rate)
424 cgl *= 5;
425 }
426 #if 0
427 /* XXX what manual says */
428 tmp1 = BA1READ4(sc, CS4280_CSRC) & ~CSRC_MASK;
429 tmp1 |= csrc<<16;
430 BA1WRITE4(sc, CS4280_CSRC, tmp1);
431 #else
432 /* suggested by cs461x.c (ALSA driver) */
433 BA1WRITE4(sc, CS4280_CSRC, CS4280_MK_CSRC(csrc, cy));
434 #endif
435
436 #if 0
437 /* I am confused. The sample rate calculation section says
438 * cci *is* 32-bit signed quantity but in the parameter description
439 * section, CCI only assigned 16bit.
440 * I believe size of the variable.
441 */
442 tmp1 = BA1READ4(sc, CS4280_CCI) & ~CCI_MASK;
443 tmp1 |= cci<<16;
444 BA1WRITE4(sc, CS4280_CCI, tmp1);
445 #else
446 BA1WRITE4(sc, CS4280_CCI, cci);
447 #endif
448
449 tmp1 = BA1READ4(sc, CS4280_CD) & ~CD_MASK;
450 tmp1 |= cdlay <<18;
451 BA1WRITE4(sc, CS4280_CD, tmp1);
452
453 BA1WRITE4(sc, CS4280_CPI, cpi);
454
455 tmp1 = BA1READ4(sc, CS4280_CGL) & ~CGL_MASK;
456 tmp1 |= cgl;
457 BA1WRITE4(sc, CS4280_CGL, tmp1);
458
459 BA1WRITE4(sc, CS4280_CNT, cnt);
460
461 tmp1 = BA1READ4(sc, CS4280_CGC) & ~CGC_MASK;
462 tmp1 |= cgl;
463 BA1WRITE4(sc, CS4280_CGC, tmp1);
464 }
465
466 void
cs4280_set_dac_rate(struct cs4280_softc * sc,int rate)467 cs4280_set_dac_rate(struct cs4280_softc *sc, int rate)
468 {
469 /*
470 * playback rate may range from 8000Hz to 48000Hz
471 *
472 * play_phase_increment = floor(rate*65536*1024/48000)
473 * px = round(rate*65536*1024 - play_phase_increment*48000)
474 * py=floor(px/200)
475 * play_sample_rate_correction = px - 200*py
476 *
477 * play_phase_increment is a 32bit signed quantity.
478 * play_sample_rate_correction is a 16bit signed quantity.
479 */
480 int32_t ppi;
481 int16_t psrc;
482 u_int32_t px, py;
483
484 if (rate < 8000)
485 rate = 8000;
486 if (rate > 48000)
487 rate = 48000;
488 px = rate << 16;
489 ppi = px/48000;
490 px -= ppi*48000;
491 ppi <<= 10;
492 px <<= 10;
493 py = px / 48000;
494 ppi += py;
495 px -= py*48000;
496 py = px/200;
497 px -= py*200;
498 psrc = px;
499 #if 0
500 /* what manual says */
501 px = BA1READ4(sc, CS4280_PSRC) & ~PSRC_MASK;
502 BA1WRITE4(sc, CS4280_PSRC,
503 ( ((psrc<<16) & PSRC_MASK) | px ));
504 #else
505 /* suggested by cs461x.c (ALSA driver) */
506 BA1WRITE4(sc, CS4280_PSRC, CS4280_MK_PSRC(psrc,py));
507 #endif
508 BA1WRITE4(sc, CS4280_PPI, ppi);
509 }
510
511 void
cs4280_attachhook(struct device * self)512 cs4280_attachhook(struct device *self)
513 {
514 struct cs4280_softc *sc = (struct cs4280_softc *)self;
515 mixer_ctrl_t ctl;
516
517 /* Initialization */
518 if (cs4280_init2(sc, 1) != 0)
519 return;
520
521 printf("%s: firmware loaded\n", sc->sc_dev.dv_xname);
522
523 /* Turn mute off of DAC, CD and master volumes by default */
524 ctl.type = AUDIO_MIXER_ENUM;
525 ctl.un.ord = 0; /* off */
526
527 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCoutputs,
528 AudioNmaster, AudioNmute);
529 cs4280_mixer_set_port(sc, &ctl);
530
531 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCinputs,
532 AudioNdac, AudioNmute);
533 cs4280_mixer_set_port(sc, &ctl);
534
535 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCinputs,
536 AudioNcd, AudioNmute);
537 cs4280_mixer_set_port(sc, &ctl);
538
539 audio_attach_mi(&cs4280_hw_if, sc, NULL, &sc->sc_dev);
540
541 #if NMIDI > 0
542 midi_attach_mi(&cs4280_midi_hw_if, sc, &sc->sc_dev);
543 #endif
544 }
545
546 void
cs4280_attach(struct device * parent,struct device * self,void * aux)547 cs4280_attach(struct device *parent, struct device *self, void *aux)
548 {
549 struct cs4280_softc *sc = (struct cs4280_softc *) self;
550 struct pci_attach_args *pa = (struct pci_attach_args *) aux;
551 pci_chipset_tag_t pc = pa->pa_pc;
552 char const *intrstr;
553 pci_intr_handle_t ih;
554 u_int32_t mem;
555
556 /* Map I/O register */
557 if (pci_mapreg_map(pa, CSCC_PCI_BA0,
558 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0,
559 &sc->ba0t, &sc->ba0h, NULL, NULL, 0)) {
560 printf(": can't map BA0 space\n");
561 return;
562 }
563 if (pci_mapreg_map(pa, CSCC_PCI_BA1,
564 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0,
565 &sc->ba1t, &sc->ba1h, NULL, NULL, 0)) {
566 printf(": can't map BA1 space\n");
567 return;
568 }
569
570 sc->sc_dmatag = pa->pa_dmat;
571
572 /* Get out of power save mode if needed. */
573 pci_set_powerstate(pc, pa->pa_tag, PCI_PMCSR_STATE_D0);
574
575 /* LATENCY_TIMER setting */
576 mem = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG);
577 if ( PCI_LATTIMER(mem) < 32 ) {
578 mem &= 0xffff00ff;
579 mem |= 0x00002000;
580 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, mem);
581 }
582
583 /* Map and establish the interrupt. */
584 if (pci_intr_map(pa, &ih)) {
585 printf(": couldn't map interrupt\n");
586 return;
587 }
588 intrstr = pci_intr_string(pc, ih);
589
590 sc->sc_ih = pci_intr_establish(pc, ih, IPL_AUDIO | IPL_MPSAFE,
591 cs4280_intr, sc, sc->sc_dev.dv_xname);
592 if (sc->sc_ih == NULL) {
593 printf(": couldn't establish interrupt");
594 if (intrstr != NULL)
595 printf(" at %s", intrstr);
596 printf("\n");
597 return;
598 }
599 printf(": %s\n", intrstr);
600
601 /* Initialization */
602 if (cs4280_init(sc, 1) != 0)
603 return;
604
605 config_mountroot(self, cs4280_attachhook);
606
607 /* AC 97 attachment */
608 sc->host_if.arg = sc;
609 sc->host_if.attach = cs4280_attach_codec;
610 sc->host_if.read = cs4280_read_codec;
611 sc->host_if.write = cs4280_write_codec;
612 sc->host_if.reset = cs4280_reset_codec;
613
614 if (ac97_attach(&sc->host_if) != 0) {
615 printf("%s: ac97_attach failed\n", sc->sc_dev.dv_xname);
616 return;
617 }
618 }
619
620 int
cs4280_intr(void * p)621 cs4280_intr(void *p)
622 {
623 /*
624 * XXX
625 *
626 * Since CS4280 has only 4kB dma buffer and
627 * interrupt occurs every 2kB block, I create dummy buffer
628 * which returns to audio driver and actual dma buffer
629 * using in DMA transfer.
630 *
631 *
632 * ring buffer in audio.c is pointed by BUFADDR
633 * <------ ring buffer size == 64kB ------>
634 * <-----> blksize == 2048*(sc->sc_[pr]count) kB
635 * |= = = =|= = = =|= = = =|= = = =|= = = =|
636 * | | | | | | <- call audio_intp every
637 * sc->sc_[pr]_count time.
638 *
639 * actual dma buffer is pointed by KERNADDR
640 * <-> dma buffer size = 4kB
641 * |= =|
642 *
643 *
644 */
645 struct cs4280_softc *sc = p;
646 u_int32_t intr, mem;
647 char * empty_dma;
648 int handled = 0;
649
650 mtx_enter(&audio_lock);
651 /* grab interrupt register then clear it */
652 intr = BA0READ4(sc, CS4280_HISR);
653 BA0WRITE4(sc, CS4280_HICR, HICR_CHGM | HICR_IEV);
654
655 /* Playback Interrupt */
656 if (intr & HISR_PINT) {
657 handled = 1;
658 mem = BA1READ4(sc, CS4280_PFIE);
659 BA1WRITE4(sc, CS4280_PFIE, (mem & ~PFIE_PI_MASK) | PFIE_PI_DISABLE);
660 if (sc->sc_pintr) {
661 if ((sc->sc_pi%sc->sc_pcount) == 0)
662 sc->sc_pintr(sc->sc_parg);
663 } else {
664 printf("unexpected play intr\n");
665 }
666 /* copy buffer */
667 ++sc->sc_pi;
668 empty_dma = sc->sc_pdma->addr;
669 if (sc->sc_pi&1)
670 empty_dma += CS4280_ICHUNK;
671 memcpy(empty_dma, sc->sc_pn, CS4280_ICHUNK);
672 sc->sc_pn += CS4280_ICHUNK;
673 if (sc->sc_pn >= sc->sc_pe)
674 sc->sc_pn = sc->sc_ps;
675 BA1WRITE4(sc, CS4280_PFIE, mem);
676 }
677 /* Capture Interrupt */
678 if (intr & HISR_CINT) {
679 int i;
680 int16_t rdata;
681
682 handled = 1;
683 mem = BA1READ4(sc, CS4280_CIE);
684 BA1WRITE4(sc, CS4280_CIE, (mem & ~CIE_CI_MASK) | CIE_CI_DISABLE);
685 ++sc->sc_ri;
686 empty_dma = sc->sc_rdma->addr;
687 if ((sc->sc_ri&1) == 0)
688 empty_dma += CS4280_ICHUNK;
689
690 /*
691 * XXX
692 * I think this audio data conversion should be
693 * happened in upper layer, but I put this here
694 * since there is no conversion function available.
695 */
696 switch(sc->sc_rparam) {
697 case CF_16BIT_STEREO:
698 /* just copy it */
699 memcpy(sc->sc_rn, empty_dma, CS4280_ICHUNK);
700 sc->sc_rn += CS4280_ICHUNK;
701 break;
702 case CF_16BIT_MONO:
703 for (i = 0; i < 512; i++) {
704 rdata = *((int16_t *)empty_dma)>>1;
705 empty_dma += 2;
706 rdata += *((int16_t *)empty_dma)>>1;
707 empty_dma += 2;
708 *((int16_t *)sc->sc_rn) = rdata;
709 sc->sc_rn += 2;
710 }
711 break;
712 case CF_8BIT_STEREO:
713 for (i = 0; i < 512; i++) {
714 rdata = *((int16_t*)empty_dma);
715 empty_dma += 2;
716 *sc->sc_rn++ = rdata >> 8;
717 rdata = *((int16_t*)empty_dma);
718 empty_dma += 2;
719 *sc->sc_rn++ = rdata >> 8;
720 }
721 break;
722 case CF_8BIT_MONO:
723 for (i = 0; i < 512; i++) {
724 rdata = *((int16_t*)empty_dma) >>1;
725 empty_dma += 2;
726 rdata += *((int16_t*)empty_dma) >>1;
727 empty_dma += 2;
728 *sc->sc_rn++ = rdata >>8;
729 }
730 break;
731 default:
732 /* Should not reach here */
733 printf("unknown sc->sc_rparam: %d\n", sc->sc_rparam);
734 }
735 if (sc->sc_rn >= sc->sc_re)
736 sc->sc_rn = sc->sc_rs;
737 BA1WRITE4(sc, CS4280_CIE, mem);
738 if (sc->sc_rintr) {
739 if ((sc->sc_ri%(sc->sc_rcount)) == 0)
740 sc->sc_rintr(sc->sc_rarg);
741 } else {
742 printf("unexpected record intr\n");
743 }
744 }
745
746 #if NMIDI > 0
747 /* Midi port Interrupt */
748 if (intr & HISR_MIDI) {
749 int data;
750
751 handled = 1;
752 DPRINTF(("i: %d: ",
753 BA0READ4(sc, CS4280_MIDSR)));
754 /* Read the received data */
755 while ((sc->sc_iintr != NULL) &&
756 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_RBE) == 0)) {
757 data = BA0READ4(sc, CS4280_MIDRP) & MIDRP_MASK;
758 DPRINTF(("r:%x\n",data));
759 sc->sc_iintr(sc->sc_arg, data);
760 }
761
762 /* Write the data */
763 #if 1
764 /* XXX:
765 * It seems "Transmit Buffer Full" never activate until EOI
766 * is delivered. Shall I throw EOI top of this routine ?
767 */
768 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) {
769 DPRINTF(("w: "));
770 if (sc->sc_ointr != NULL)
771 sc->sc_ointr(sc->sc_arg);
772 }
773 #else
774 while ((sc->sc_ointr != NULL) &&
775 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0)) {
776 DPRINTF(("w: "));
777 sc->sc_ointr(sc->sc_arg);
778 }
779 #endif
780 DPRINTF(("\n"));
781 }
782 #endif
783 mtx_leave(&audio_lock);
784 return handled;
785 }
786
787
788 /* Download Processor Code and Data image */
789
790 int
cs4280_download(struct cs4280_softc * sc,const u_int32_t * src,u_int32_t offset,u_int32_t len)791 cs4280_download(struct cs4280_softc *sc, const u_int32_t *src, u_int32_t offset,
792 u_int32_t len)
793 {
794 u_int32_t ctr;
795
796 #ifdef CS4280_DEBUG
797 u_int32_t con, data;
798 u_int8_t c0,c1,c2,c3;
799 #endif
800 if ((offset&3) || (len&3))
801 return (-1);
802
803 len /= sizeof(u_int32_t);
804 for (ctr = 0; ctr < len; ctr++) {
805 /* XXX:
806 * I cannot confirm this is the right thing or not
807 * on BIG-ENDIAN machines.
808 */
809 BA1WRITE4(sc, offset+ctr*4, htole32(*(src+ctr)));
810 #ifdef CS4280_DEBUG
811 data = htole32(*(src+ctr));
812 c0 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+0);
813 c1 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+1);
814 c2 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+2);
815 c3 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+3);
816 con = ( (c3<<24) | (c2<<16) | (c1<<8) | c0 );
817 if (data != con ) {
818 printf("0x%06x: write=0x%08x read=0x%08x\n",
819 offset+ctr*4, data, con);
820 return (-1);
821 }
822 #endif
823 }
824 return (0);
825 }
826
827 struct BA1struct *BA1Struct;
828
829 int
cs4280_download_image(struct cs4280_softc * sc)830 cs4280_download_image(struct cs4280_softc *sc)
831 {
832 int idx, err = 0;
833 u_int32_t offset = 0;
834 static u_char *cs4280_firmware;
835 static size_t cs4280_firmwarelen;
836
837 if (cs4280_firmware == NULL) {
838 err = loadfirmware("cs4280", &cs4280_firmware,
839 &cs4280_firmwarelen);
840 if (err)
841 return (err);
842 }
843
844 BA1Struct = (struct BA1struct *)cs4280_firmware;
845
846 for (idx = 0; idx < BA1_MEMORY_COUNT; ++idx) {
847 err = cs4280_download(sc, &BA1Struct->map[offset],
848 BA1Struct->memory[idx].offset, BA1Struct->memory[idx].size);
849 if (err != 0) {
850 printf("%s: load_image failed at %d\n",
851 sc->sc_dev.dv_xname, idx);
852 return (-1);
853 }
854 offset += BA1Struct->memory[idx].size / sizeof(u_int32_t);
855 }
856 return (err);
857 }
858
859 #ifdef CS4280_DEBUG
860 int
cs4280_checkimage(struct cs4280_softc * sc,u_int32_t * src,u_int32_t offset,u_int32_t len)861 cs4280_checkimage(struct cs4280_softc *sc, u_int32_t *src, u_int32_t offset,
862 u_int32_t len)
863 {
864 u_int32_t ctr, data;
865 int err = 0;
866
867 if ((offset&3) || (len&3))
868 return -1;
869
870 len /= sizeof(u_int32_t);
871 for (ctr = 0; ctr < len; ctr++) {
872 /* I cannot confirm this is the right thing
873 * on BIG-ENDIAN machines
874 */
875 data = BA1READ4(sc, offset+ctr*4);
876 if (data != htole32(*(src+ctr))) {
877 printf("0x%06x: 0x%08x(0x%08x)\n",
878 offset+ctr*4, data, *(src+ctr));
879 *(src+ctr) = data;
880 ++err;
881 }
882 }
883 return (err);
884 }
885
886 int
cs4280_check_images(struct cs4280_softc * sc)887 cs4280_check_images(struct cs4280_softc *sc)
888 {
889 int idx, err;
890 u_int32_t offset = 0;
891
892 err = 0;
893 /*for (idx=0; idx < BA1_MEMORY_COUNT; ++idx) { */
894 for (idx = 0; idx < 1; ++idx) {
895 err = cs4280_checkimage(sc, &BA1Struct->map[offset],
896 BA1Struct->memory[idx].offset,
897 BA1Struct->memory[idx].size);
898 if (err != 0) {
899 printf("%s: check_image failed at %d\n",
900 sc->sc_dev.dv_xname, idx);
901 }
902 offset += BA1Struct->memory[idx].size / sizeof(u_int32_t);
903 }
904 return (err);
905 }
906
907 #endif
908
909 int
cs4280_attach_codec(void * sc_,struct ac97_codec_if * codec_if)910 cs4280_attach_codec(void *sc_, struct ac97_codec_if *codec_if)
911 {
912 struct cs4280_softc *sc = sc_;
913
914 sc->codec_if = codec_if;
915 return (0);
916 }
917
918 void
cs4280_reset_codec(void * sc_)919 cs4280_reset_codec(void *sc_)
920 {
921 struct cs4280_softc *sc = sc_;
922 int n;
923
924 /* Reset codec */
925 BA0WRITE4(sc, CS4280_ACCTL, 0);
926 delay(100); /* delay 100us */
927 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_RSTN);
928
929 /*
930 * It looks like we do the following procedure, too
931 */
932
933 /* Enable AC-link sync generation */
934 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_ESYN | ACCTL_RSTN);
935 delay(50*1000); /* XXX delay 50ms */
936
937 /* Assert valid frame signal */
938 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
939
940 /* Wait for valid AC97 input slot */
941 n = 0;
942 while (BA0READ4(sc, CS4280_ACISV) != (ACISV_ISV3 | ACISV_ISV4)) {
943 delay(1000);
944 if (++n > 1000) {
945 printf("reset_codec: AC97 inputs slot ready timeout\n");
946 return;
947 }
948 }
949 }
950
951
952 /* Processor Soft Reset */
953 void
cs4280_reset(void * sc_)954 cs4280_reset(void *sc_)
955 {
956 struct cs4280_softc *sc = sc_;
957
958 /* Set RSTSP bit in SPCR (also clear RUN, RUNFR, and DRQEN) */
959 BA1WRITE4(sc, CS4280_SPCR, SPCR_RSTSP);
960 delay(100);
961 /* Clear RSTSP bit in SPCR */
962 BA1WRITE4(sc, CS4280_SPCR, 0);
963 /* enable DMA request */
964 BA1WRITE4(sc, CS4280_SPCR, SPCR_DRQEN);
965 }
966
967 int
cs4280_open(void * addr,int flags)968 cs4280_open(void *addr, int flags)
969 {
970 return (0);
971 }
972
973 void
cs4280_close(void * addr)974 cs4280_close(void *addr)
975 {
976 struct cs4280_softc *sc = addr;
977
978 /* XXX: already called in audio_close() */
979 cs4280_halt_output(sc);
980 cs4280_halt_input(sc);
981
982 sc->sc_pintr = 0;
983 sc->sc_rintr = 0;
984 }
985
986 int
cs4280_set_params(void * addr,int setmode,int usemode,struct audio_params * play,struct audio_params * rec)987 cs4280_set_params(void *addr, int setmode, int usemode,
988 struct audio_params *play, struct audio_params *rec)
989 {
990 struct cs4280_softc *sc = addr;
991 struct audio_params *p;
992 int mode;
993
994 for (mode = AUMODE_RECORD; mode != -1;
995 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1 ) {
996 if ((setmode & mode) == 0)
997 continue;
998
999 p = mode == AUMODE_PLAY ? play : rec;
1000 if (p == play) {
1001 DPRINTFN(5,("play: sample=%ld precision=%d channels=%d\n",
1002 p->sample_rate, p->precision, p->channels));
1003 } else {
1004 DPRINTFN(5,("rec: sample=%ld precision=%d channels=%d\n",
1005 p->sample_rate, p->precision, p->channels));
1006 }
1007 /* play back data format may be 8- or 16-bit and
1008 * either stereo or mono.
1009 * playback rate may range from 8000Hz to 48000Hz
1010 *
1011 * capture data format must be 16bit stereo
1012 * and sample rate range from 11025Hz to 48000Hz.
1013 *
1014 * XXX: it looks like to work with 8000Hz,
1015 * although data sheets say lower limit is
1016 * 11025 Hz.
1017 */
1018 if (p->sample_rate < 8000)
1019 p->sample_rate = 8000;
1020 if (p->sample_rate > 48000)
1021 p->sample_rate = 48000;
1022 if (p->precision > 16)
1023 p->precision = 16;
1024 if (p->channels > 2)
1025 p->channels = 2;
1026
1027 /* capturing data is slinear */
1028 switch (p->encoding) {
1029 case AUDIO_ENCODING_SLINEAR_LE:
1030 break;
1031 default:
1032 return (EINVAL);
1033 }
1034 p->bps = AUDIO_BPS(p->precision);
1035 p->msb = 1;
1036 }
1037
1038 /* set sample rate */
1039 cs4280_set_dac_rate(sc, play->sample_rate);
1040 cs4280_set_adc_rate(sc, rec->sample_rate);
1041 return (0);
1042 }
1043
1044 int
cs4280_round_blocksize(void * hdl,int blk)1045 cs4280_round_blocksize(void *hdl, int blk)
1046 {
1047 return (blk < CS4280_ICHUNK ? CS4280_ICHUNK : blk & -CS4280_ICHUNK);
1048 }
1049
1050 int
cs4280_mixer_get_port(void * addr,mixer_ctrl_t * cp)1051 cs4280_mixer_get_port(void *addr, mixer_ctrl_t *cp)
1052 {
1053 struct cs4280_softc *sc = addr;
1054
1055 return (sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp));
1056 }
1057
1058 int
cs4280_query_devinfo(void * addr,mixer_devinfo_t * dip)1059 cs4280_query_devinfo(void *addr, mixer_devinfo_t *dip)
1060 {
1061 struct cs4280_softc *sc = addr;
1062
1063 return (sc->codec_if->vtbl->query_devinfo(sc->codec_if, dip));
1064 }
1065
1066 int
cs4280_get_portnum_by_name(struct cs4280_softc * sc,char * class,char * device,char * qualifier)1067 cs4280_get_portnum_by_name(struct cs4280_softc *sc, char *class, char *device,
1068 char *qualifier)
1069 {
1070 return (sc->codec_if->vtbl->get_portnum_by_name(sc->codec_if, class,
1071 device, qualifier));
1072 }
1073
1074 int
cs4280_halt_output(void * addr)1075 cs4280_halt_output(void *addr)
1076 {
1077 struct cs4280_softc *sc = addr;
1078 u_int32_t mem;
1079
1080 mtx_enter(&audio_lock);
1081 mem = BA1READ4(sc, CS4280_PCTL);
1082 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK);
1083 #ifdef DIAGNOSTIC
1084 sc->sc_prun = 0;
1085 #endif
1086 mtx_leave(&audio_lock);
1087 return (0);
1088 }
1089
1090 int
cs4280_halt_input(void * addr)1091 cs4280_halt_input(void *addr)
1092 {
1093 struct cs4280_softc *sc = addr;
1094 u_int32_t mem;
1095
1096 mtx_enter(&audio_lock);
1097 mem = BA1READ4(sc, CS4280_CCTL);
1098 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK);
1099 #ifdef DIAGNOSTIC
1100 sc->sc_rrun = 0;
1101 #endif
1102 mtx_leave(&audio_lock);
1103 return (0);
1104 }
1105
1106 int
cs4280_mixer_set_port(void * addr,mixer_ctrl_t * cp)1107 cs4280_mixer_set_port(void *addr, mixer_ctrl_t *cp)
1108 {
1109 struct cs4280_softc *sc = addr;
1110 int val;
1111
1112 val = sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp);
1113 DPRINTFN(3,("mixer_set_port: val=%d\n", val));
1114 return (val);
1115 }
1116
1117
1118 int
cs4280_freemem(struct cs4280_softc * sc,struct cs4280_dma * p)1119 cs4280_freemem(struct cs4280_softc *sc, struct cs4280_dma *p)
1120 {
1121 bus_dmamap_unload(sc->sc_dmatag, p->map);
1122 bus_dmamap_destroy(sc->sc_dmatag, p->map);
1123 bus_dmamem_unmap(sc->sc_dmatag, p->addr, p->size);
1124 bus_dmamem_free(sc->sc_dmatag, p->segs, p->nsegs);
1125 return (0);
1126 }
1127
1128 int
cs4280_allocmem(struct cs4280_softc * sc,size_t size,size_t align,struct cs4280_dma * p)1129 cs4280_allocmem(struct cs4280_softc *sc, size_t size, size_t align,
1130 struct cs4280_dma *p)
1131 {
1132 int error;
1133
1134 /* XXX */
1135 p->size = size;
1136 error = bus_dmamem_alloc(sc->sc_dmatag, p->size, align, 0,
1137 p->segs, sizeof(p->segs)/sizeof(p->segs[0]),
1138 &p->nsegs, BUS_DMA_NOWAIT);
1139 if (error) {
1140 printf("%s: unable to allocate dma, error=%d\n",
1141 sc->sc_dev.dv_xname, error);
1142 return (error);
1143 }
1144
1145 error = bus_dmamem_map(sc->sc_dmatag, p->segs, p->nsegs, p->size,
1146 &p->addr, BUS_DMA_NOWAIT|BUS_DMA_COHERENT);
1147 if (error) {
1148 printf("%s: unable to map dma, error=%d\n",
1149 sc->sc_dev.dv_xname, error);
1150 goto free;
1151 }
1152
1153 error = bus_dmamap_create(sc->sc_dmatag, p->size, 1, p->size,
1154 0, BUS_DMA_NOWAIT, &p->map);
1155 if (error) {
1156 printf("%s: unable to create dma map, error=%d\n",
1157 sc->sc_dev.dv_xname, error);
1158 goto unmap;
1159 }
1160
1161 error = bus_dmamap_load(sc->sc_dmatag, p->map, p->addr, p->size, NULL,
1162 BUS_DMA_NOWAIT);
1163 if (error) {
1164 printf("%s: unable to load dma map, error=%d\n",
1165 sc->sc_dev.dv_xname, error);
1166 goto destroy;
1167 }
1168 return (0);
1169
1170 destroy:
1171 bus_dmamap_destroy(sc->sc_dmatag, p->map);
1172 unmap:
1173 bus_dmamem_unmap(sc->sc_dmatag, p->addr, p->size);
1174 free:
1175 bus_dmamem_free(sc->sc_dmatag, p->segs, p->nsegs);
1176 return (error);
1177 }
1178
1179
1180 void *
cs4280_malloc(void * addr,int direction,size_t size,int pool,int flags)1181 cs4280_malloc(void *addr, int direction, size_t size, int pool, int flags)
1182 {
1183 struct cs4280_softc *sc = addr;
1184 struct cs4280_dma *p;
1185 caddr_t q;
1186 int error;
1187
1188 DPRINTFN(5,("cs4280_malloc: size=%d pool=%d flags=%d\n", size, pool, flags));
1189 q = malloc(size, pool, flags);
1190 if (!q)
1191 return (0);
1192 p = malloc(sizeof(*p), pool, flags);
1193 if (!p) {
1194 free(q,pool, 0);
1195 return (0);
1196 }
1197 /*
1198 * cs4280 has fixed 4kB buffer
1199 */
1200 error = cs4280_allocmem(sc, CS4280_DCHUNK, CS4280_DALIGN, p);
1201
1202 if (error) {
1203 free(q, pool, 0);
1204 free(p, pool, 0);
1205 return (0);
1206 }
1207
1208 p->next = sc->sc_dmas;
1209 sc->sc_dmas = p;
1210 p->dum = q; /* return to audio driver */
1211
1212 return (p->dum);
1213 }
1214
1215 void
cs4280_free(void * addr,void * ptr,int pool)1216 cs4280_free(void *addr, void *ptr, int pool)
1217 {
1218 struct cs4280_softc *sc = addr;
1219 struct cs4280_dma **pp, *p;
1220
1221 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) {
1222 if (BUFADDR(p) == ptr) {
1223 cs4280_freemem(sc, p);
1224 *pp = p->next;
1225 free(p->dum, pool, 0);
1226 free(p, pool, 0);
1227 return;
1228 }
1229 }
1230 }
1231
1232 int
cs4280_trigger_output(void * addr,void * start,void * end,int blksize,void (* intr)(void *),void * arg,struct audio_params * param)1233 cs4280_trigger_output(void *addr, void *start, void *end, int blksize,
1234 void (*intr)(void *), void *arg, struct audio_params *param)
1235 {
1236 struct cs4280_softc *sc = addr;
1237 u_int32_t pfie, pctl, mem, pdtc;
1238 struct cs4280_dma *p;
1239
1240 #ifdef DIAGNOSTIC
1241 if (sc->sc_prun)
1242 printf("cs4280_trigger_output: already running\n");
1243 sc->sc_prun = 1;
1244 #endif
1245 DPRINTF(("cs4280_trigger_output: sc=%p start=%p end=%p "
1246 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg));
1247 sc->sc_pintr = intr;
1248 sc->sc_parg = arg;
1249
1250 /* stop playback DMA */
1251 mem = BA1READ4(sc, CS4280_PCTL);
1252 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK);
1253
1254 /* setup PDTC */
1255 pdtc = BA1READ4(sc, CS4280_PDTC);
1256 pdtc &= ~PDTC_MASK;
1257 pdtc |= CS4280_MK_PDTC(param->precision * param->channels);
1258 BA1WRITE4(sc, CS4280_PDTC, pdtc);
1259
1260 DPRINTF(("param: precision=%d channels=%d encoding=%d\n",
1261 param->precision, param->channels,
1262 param->encoding));
1263 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next)
1264 ;
1265 if (p == NULL) {
1266 printf("cs4280_trigger_output: bad addr %p\n", start);
1267 return (EINVAL);
1268 }
1269 if (DMAADDR(p) % CS4280_DALIGN != 0 ) {
1270 printf("cs4280_trigger_output: DMAADDR(p)=0x%lx does not start"
1271 "4kB align\n", DMAADDR(p));
1272 return (EINVAL);
1273 }
1274
1275 sc->sc_pcount = blksize / CS4280_ICHUNK; /* CS4280_ICHUNK is fixed hardware blksize*/
1276 sc->sc_ps = (char *)start;
1277 sc->sc_pe = (char *)end;
1278 sc->sc_pdma = p;
1279 sc->sc_pbuf = KERNADDR(p);
1280 sc->sc_pi = 0;
1281 sc->sc_pn = sc->sc_ps;
1282 if (blksize >= CS4280_DCHUNK) {
1283 sc->sc_pn = sc->sc_ps + CS4280_DCHUNK;
1284 memcpy(sc->sc_pbuf, start, CS4280_DCHUNK);
1285 ++sc->sc_pi;
1286 } else {
1287 sc->sc_pn = sc->sc_ps + CS4280_ICHUNK;
1288 memcpy(sc->sc_pbuf, start, CS4280_ICHUNK);
1289 }
1290
1291 /* initiate playback dma */
1292 mtx_enter(&audio_lock);
1293 BA1WRITE4(sc, CS4280_PBA, DMAADDR(p));
1294
1295 /* set PFIE */
1296 pfie = BA1READ4(sc, CS4280_PFIE) & ~PFIE_MASK;
1297
1298 if (param->precision == 8)
1299 pfie |= PFIE_8BIT;
1300 if (param->channels == 1)
1301 pfie |= PFIE_MONO;
1302
1303 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE ||
1304 param->encoding == AUDIO_ENCODING_SLINEAR_BE)
1305 pfie |= PFIE_SWAPPED;
1306 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE ||
1307 param->encoding == AUDIO_ENCODING_ULINEAR_LE)
1308 pfie |= PFIE_UNSIGNED;
1309
1310 BA1WRITE4(sc, CS4280_PFIE, pfie | PFIE_PI_ENABLE);
1311
1312 cs4280_set_dac_rate(sc, param->sample_rate);
1313
1314 pctl = BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK;
1315 pctl |= sc->pctl;
1316 BA1WRITE4(sc, CS4280_PCTL, pctl);
1317 mtx_leave(&audio_lock);
1318 return (0);
1319 }
1320
1321 int
cs4280_trigger_input(void * addr,void * start,void * end,int blksize,void (* intr)(void *),void * arg,struct audio_params * param)1322 cs4280_trigger_input(void *addr, void *start, void *end, int blksize,
1323 void (*intr)(void *), void *arg, struct audio_params *param)
1324 {
1325 struct cs4280_softc *sc = addr;
1326 u_int32_t cctl, cie;
1327 struct cs4280_dma *p;
1328
1329 #ifdef DIAGNOSTIC
1330 if (sc->sc_rrun)
1331 printf("cs4280_trigger_input: already running\n");
1332 sc->sc_rrun = 1;
1333 #endif
1334 DPRINTF(("cs4280_trigger_input: sc=%p start=%p end=%p "
1335 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg));
1336 sc->sc_rintr = intr;
1337 sc->sc_rarg = arg;
1338
1339 sc->sc_ri = 0;
1340 sc->sc_rcount = blksize / CS4280_ICHUNK; /* CS4280_ICHUNK is fixed hardware blksize*/
1341 sc->sc_rs = (char *)start;
1342 sc->sc_re = (char *)end;
1343 sc->sc_rn = sc->sc_rs;
1344
1345 /* setup format information for internal converter */
1346 sc->sc_rparam = 0;
1347 if (param->precision == 8) {
1348 sc->sc_rparam += CF_8BIT;
1349 sc->sc_rcount <<= 1;
1350 }
1351 if (param->channels == 1) {
1352 sc->sc_rparam += CF_MONO;
1353 sc->sc_rcount <<= 1;
1354 }
1355
1356 /* stop capture DMA */
1357 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK;
1358 BA1WRITE4(sc, CS4280_CCTL, cctl);
1359
1360 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next)
1361 ;
1362 if (!p) {
1363 printf("cs4280_trigger_input: bad addr %p\n", start);
1364 return (EINVAL);
1365 }
1366 if (DMAADDR(p) % CS4280_DALIGN != 0) {
1367 printf("cs4280_trigger_input: DMAADDR(p)=0x%lx does not start"
1368 "4kB align\n", DMAADDR(p));
1369 return (EINVAL);
1370 }
1371 sc->sc_rdma = p;
1372 sc->sc_rbuf = KERNADDR(p);
1373
1374 /* initiate capture dma */
1375 mtx_enter(&audio_lock);
1376 BA1WRITE4(sc, CS4280_CBA, DMAADDR(p));
1377
1378 /* set CIE */
1379 cie = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK;
1380 BA1WRITE4(sc, CS4280_CIE, cie | CIE_CI_ENABLE);
1381
1382 cs4280_set_adc_rate(sc, param->sample_rate);
1383
1384 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK;
1385 cctl |= sc->cctl;
1386 BA1WRITE4(sc, CS4280_CCTL, cctl);
1387 mtx_leave(&audio_lock);
1388 return (0);
1389 }
1390
1391
1392 int
cs4280_init(struct cs4280_softc * sc,int init)1393 cs4280_init(struct cs4280_softc *sc, int init)
1394 {
1395 int n;
1396 u_int32_t mem;
1397
1398 /* Start PLL out in known state */
1399 BA0WRITE4(sc, CS4280_CLKCR1, 0);
1400 /* Start serial ports out in known state */
1401 BA0WRITE4(sc, CS4280_SERMC1, 0);
1402
1403 /* Specify type of CODEC */
1404 /* XXX should no be here */
1405 #define SERACC_CODEC_TYPE_1_03
1406 #ifdef SERACC_CODEC_TYPE_1_03
1407 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_1_03); /* AC 97 1.03 */
1408 #else
1409 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_2_0); /* AC 97 2.0 */
1410 #endif
1411
1412 /* Reset codec */
1413 BA0WRITE4(sc, CS4280_ACCTL, 0);
1414 delay(100); /* delay 100us */
1415 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_RSTN);
1416
1417 /* Enable AC-link sync generation */
1418 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_ESYN | ACCTL_RSTN);
1419 delay(50*1000); /* delay 50ms */
1420
1421 /* Set the serial port timing configuration */
1422 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_PTC_AC97);
1423
1424 /* Setup clock control */
1425 BA0WRITE4(sc, CS4280_PLLCC, PLLCC_CDR_STATE|PLLCC_LPF_STATE);
1426 BA0WRITE4(sc, CS4280_PLLM, PLLM_STATE);
1427 BA0WRITE4(sc, CS4280_CLKCR2, CLKCR2_PDIVS_8);
1428
1429 /* Power up the PLL */
1430 BA0WRITE4(sc, CS4280_CLKCR1, CLKCR1_PLLP);
1431 delay(50*1000); /* delay 50ms */
1432
1433 /* Turn on clock */
1434 mem = BA0READ4(sc, CS4280_CLKCR1) | CLKCR1_SWCE;
1435 BA0WRITE4(sc, CS4280_CLKCR1, mem);
1436
1437 /* Set the serial port FIFO pointer to the
1438 * first sample in FIFO. (not documented) */
1439 cs4280_clear_fifos(sc);
1440
1441 #if 0
1442 /* Set the serial port FIFO pointer to the first sample in the FIFO */
1443 BA0WRITE4(sc, CS4280_SERBSP, 0);
1444 #endif
1445
1446 /* Configure the serial port */
1447 BA0WRITE4(sc, CS4280_SERC1, SERC1_SO1EN | SERC1_SO1F_AC97);
1448 BA0WRITE4(sc, CS4280_SERC2, SERC2_SI1EN | SERC2_SI1F_AC97);
1449 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_MSPE | SERMC1_PTC_AC97);
1450
1451 /* Wait for CODEC ready */
1452 n = 0;
1453 while ((BA0READ4(sc, CS4280_ACSTS) & ACSTS_CRDY) == 0) {
1454 delay(125);
1455 if (++n > 1000) {
1456 printf("%s: codec ready timeout\n",
1457 sc->sc_dev.dv_xname);
1458 return(1);
1459 }
1460 }
1461
1462 /* Assert valid frame signal */
1463 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
1464
1465 /* Wait for valid AC97 input slot */
1466 n = 0;
1467 while ((BA0READ4(sc, CS4280_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) !=
1468 (ACISV_ISV3 | ACISV_ISV4)) {
1469 delay(1000);
1470 if (++n > 1000) {
1471 printf("AC97 inputs slot ready timeout\n");
1472 return(1);
1473 }
1474 }
1475
1476 /* Set AC97 output slot valid signals */
1477 BA0WRITE4(sc, CS4280_ACOSV, ACOSV_SLV3 | ACOSV_SLV4);
1478
1479 /* reset the processor */
1480 cs4280_reset(sc);
1481 return (0);
1482 }
1483
1484 int
cs4280_init2(struct cs4280_softc * sc,int init)1485 cs4280_init2(struct cs4280_softc *sc, int init)
1486 {
1487 int n;
1488 u_int32_t mem;
1489
1490 /* Download the image to the processor */
1491 if (cs4280_download_image(sc) != 0) {
1492 printf("%s: image download error\n", sc->sc_dev.dv_xname);
1493 return(1);
1494 }
1495
1496 /* Save playback parameter and then write zero.
1497 * this ensures that DMA doesn't immediately occur upon
1498 * starting the processor core
1499 */
1500 mem = BA1READ4(sc, CS4280_PCTL);
1501 sc->pctl = mem & PCTL_MASK; /* save startup value */
1502 cs4280_halt_output(sc);
1503
1504 /* Save capture parameter and then write zero.
1505 * this ensures that DMA doesn't immediately occur upon
1506 * starting the processor core
1507 */
1508 mem = BA1READ4(sc, CS4280_CCTL);
1509 sc->cctl = mem & CCTL_MASK; /* save startup value */
1510 cs4280_halt_input(sc);
1511
1512 /* MSH: need to power up ADC and DAC? */
1513
1514 /* Processor Startup Procedure */
1515 BA1WRITE4(sc, CS4280_FRMT, FRMT_FTV);
1516 BA1WRITE4(sc, CS4280_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN);
1517
1518 /* Monitor RUNFR bit in SPCR for 1 to 0 transition */
1519 n = 0;
1520 while (BA1READ4(sc, CS4280_SPCR) & SPCR_RUNFR) {
1521 delay(10);
1522 if (++n > 1000) {
1523 printf("SPCR 1->0 transition timeout\n");
1524 return(1);
1525 }
1526 }
1527
1528 n = 0;
1529 while (!(BA1READ4(sc, CS4280_SPCS) & SPCS_SPRUN)) {
1530 delay(10);
1531 if (++n > 1000) {
1532 printf("SPCS 0->1 transition timeout\n");
1533 return(1);
1534 }
1535 }
1536 /* Processor is now running !!! */
1537
1538 /* Setup volume */
1539 BA1WRITE4(sc, CS4280_PVOL, 0x80008000);
1540 BA1WRITE4(sc, CS4280_CVOL, 0x80008000);
1541
1542 /* Interrupt enable */
1543 BA0WRITE4(sc, CS4280_HICR, HICR_IEV|HICR_CHGM);
1544
1545 /* playback interrupt enable */
1546 mem = BA1READ4(sc, CS4280_PFIE) & ~PFIE_PI_MASK;
1547 mem |= PFIE_PI_ENABLE;
1548 BA1WRITE4(sc, CS4280_PFIE, mem);
1549 /* capture interrupt enable */
1550 mem = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK;
1551 mem |= CIE_CI_ENABLE;
1552 BA1WRITE4(sc, CS4280_CIE, mem);
1553
1554 #if NMIDI > 0
1555 /* Reset midi port */
1556 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK;
1557 BA0WRITE4(sc, CS4280_MIDCR, mem | MIDCR_MRST);
1558 DPRINTF(("midi reset: 0x%x\n", BA0READ4(sc, CS4280_MIDCR)));
1559 /* midi interrupt enable */
1560 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE;
1561 BA0WRITE4(sc, CS4280_MIDCR, mem);
1562 #endif
1563 return(0);
1564 }
1565
1566 int
cs4280_activate(struct device * self,int act)1567 cs4280_activate(struct device *self, int act)
1568 {
1569 struct cs4280_softc *sc = (struct cs4280_softc *)self;
1570 int rv = 0;
1571
1572 switch (act) {
1573 case DVACT_SUSPEND:
1574 rv = config_activate_children(self, act);
1575 /* should I powerdown here ? */
1576 cs4280_write_codec(sc, AC97_REG_POWER, CS4280_POWER_DOWN_ALL);
1577 break;
1578 case DVACT_RESUME:
1579 cs4280_close(sc);
1580 cs4280_init(sc, 0);
1581 cs4280_init2(sc, 0);
1582 ac97_resume(&sc->host_if, sc->codec_if);
1583 rv = config_activate_children(self, act);
1584 break;
1585 default:
1586 rv = config_activate_children(self, act);
1587 break;
1588 }
1589 return (rv);
1590 }
1591
1592 void
cs4280_clear_fifos(struct cs4280_softc * sc)1593 cs4280_clear_fifos(struct cs4280_softc *sc)
1594 {
1595 int pd = 0, cnt, n;
1596 u_int32_t mem;
1597
1598 /*
1599 * If device power down, power up the device and keep power down
1600 * state.
1601 */
1602 mem = BA0READ4(sc, CS4280_CLKCR1);
1603 if (!(mem & CLKCR1_SWCE)) {
1604 printf("cs4280_clear_fifo: power down found.\n");
1605 BA0WRITE4(sc, CS4280_CLKCR1, mem | CLKCR1_SWCE);
1606 pd = 1;
1607 }
1608 BA0WRITE4(sc, CS4280_SERBWP, 0);
1609 for (cnt = 0; cnt < 256; cnt++) {
1610 n = 0;
1611 while (BA0READ4(sc, CS4280_SERBST) & SERBST_WBSY) {
1612 delay(1000);
1613 if (++n > 1000) {
1614 printf("clear_fifo: fist timeout cnt=%d\n", cnt);
1615 break;
1616 }
1617 }
1618 BA0WRITE4(sc, CS4280_SERBAD, cnt);
1619 BA0WRITE4(sc, CS4280_SERBCM, SERBCM_WRC);
1620 }
1621 if (pd)
1622 BA0WRITE4(sc, CS4280_CLKCR1, mem);
1623 }
1624
1625 #if NMIDI > 0
1626 int
cs4280_midi_open(void * addr,int flags,void (* iintr)(void,int),void (* ointr)(void *),void * arg)1627 cs4280_midi_open(void *addr, int flags, void (*iintr)(void, int),
1628 void (*ointr)(void *), void *arg)
1629 {
1630 struct cs4280_softc *sc = addr;
1631 u_int32_t mem;
1632
1633 DPRINTF(("midi_open\n"));
1634 sc->sc_iintr = iintr;
1635 sc->sc_ointr = ointr;
1636 sc->sc_arg = arg;
1637
1638 /* midi interrupt enable */
1639 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK;
1640 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE | MIDCR_MLB;
1641 BA0WRITE4(sc, CS4280_MIDCR, mem);
1642 #ifdef CS4280_DEBUG
1643 if (mem != BA0READ4(sc, CS4280_MIDCR)) {
1644 DPRINTF(("midi_open: MIDCR=%d\n", BA0READ4(sc, CS4280_MIDCR)));
1645 return(EINVAL);
1646 }
1647 DPRINTF(("MIDCR=0x%x\n", BA0READ4(sc, CS4280_MIDCR)));
1648 #endif
1649 return (0);
1650 }
1651
1652 void
cs4280_midi_close(void * addr)1653 cs4280_midi_close(void *addr)
1654 {
1655 struct cs4280_softc *sc = addr;
1656 u_int32_t mem;
1657
1658 DPRINTF(("midi_close\n"));
1659 mem = BA0READ4(sc, CS4280_MIDCR);
1660 mem &= ~MIDCR_MASK;
1661 BA0WRITE4(sc, CS4280_MIDCR, mem);
1662
1663 sc->sc_iintr = 0;
1664 sc->sc_ointr = 0;
1665 }
1666
1667 int
cs4280_midi_output(void * addr,int d)1668 cs4280_midi_output(void *addr, int d)
1669 {
1670 struct cs4280_softc *sc = addr;
1671 u_int32_t mem;
1672 int x;
1673
1674 for (x = 0; x != MIDI_BUSY_WAIT; x++) {
1675 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) {
1676 mem = BA0READ4(sc, CS4280_MIDWP) & ~MIDWP_MASK;
1677 mem |= d & MIDWP_MASK;
1678 DPRINTFN(5,("midi_output d=0x%08x",d));
1679 BA0WRITE4(sc, CS4280_MIDWP, mem);
1680 if (mem != BA0READ4(sc, CS4280_MIDWP)) {
1681 DPRINTF(("Bad write data: %d %d",
1682 mem, BA0READ4(sc, CS4280_MIDWP)));
1683 return(EIO);
1684 }
1685 return (0);
1686 }
1687 delay(MIDI_BUSY_DELAY);
1688 }
1689 return (EIO);
1690 }
1691
1692 void
cs4280_midi_getinfo(void * addr,struct midi_info * mi)1693 cs4280_midi_getinfo(void *addr, struct midi_info *mi)
1694 {
1695 mi->name = "CS4280 MIDI UART";
1696 mi->props = MIDI_PROP_CAN_INPUT | MIDI_PROP_OUT_INTR;
1697 }
1698
1699 #endif
1700