1 /*-
2 * Copyright (c) 2000 Orion Hodson <O.Hodson@cs.ucl.ac.uk>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 /*
28 * The order of pokes in the initiation sequence is based on Linux
29 * driver by Thomas Sailer, gw boynton (wesb@crystal.cirrus.com), tom
30 * woller (twoller@crystal.cirrus.com). Shingo Watanabe (nabe@nabechan.org)
31 * contributed towards power management.
32 */
33
34 #ifdef HAVE_KERNEL_OPTION_HEADERS
35 #include "opt_snd.h"
36 #endif
37
38 #include <dev/sound/pcm/sound.h>
39 #include <dev/sound/pcm/ac97.h>
40
41 #include <bus/pci/pcireg.h>
42 #include <bus/pci/pcivar.h>
43
44 #include <dev/sound/pci/cs4281.h>
45
46 SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/cs4281.c 274035 2014-11-03 11:11:45Z bapt $");
47
48 #define CS4281_DEFAULT_BUFSZ 16384
49
50 /* Max fifo size for full duplex is 64 */
51 #define CS4281_FIFO_SIZE 15
52
53 /* DMA Engine Indices */
54 #define CS4281_DMA_PLAY 0
55 #define CS4281_DMA_REC 1
56
57 /* Misc */
58
59 #define inline __inline
60
61 #ifndef DEB
62 #define DEB(x) /* x */
63 #endif /* DEB */
64
65 /* ------------------------------------------------------------------------- */
66 /* Structures */
67
68 struct sc_info;
69
70 /* channel registers */
71 struct sc_chinfo {
72 struct sc_info *parent;
73
74 struct snd_dbuf *buffer;
75 struct pcm_channel *channel;
76
77 u_int32_t spd, fmt, bps, blksz;
78
79 int dma_setup, dma_active, dma_chan;
80 };
81
82 /* device private data */
83 struct sc_info {
84 device_t dev;
85 u_int32_t type;
86
87 bus_space_tag_t st;
88 bus_space_handle_t sh;
89 bus_dma_tag_t parent_dmat;
90
91 struct resource *reg, *irq, *mem;
92 int regtype, regid, irqid, memid;
93 void *ih;
94
95 int power;
96 unsigned long bufsz;
97 struct sc_chinfo pch;
98 struct sc_chinfo rch;
99 };
100
101 /* -------------------------------------------------------------------- */
102 /* prototypes */
103
104 /* ADC/DAC control */
105 static u_int32_t adcdac_go(struct sc_chinfo *ch, u_int32_t go);
106 static void adcdac_prog(struct sc_chinfo *ch);
107
108 /* power management and interrupt control */
109 static void cs4281_intr(void *);
110 static int cs4281_power(struct sc_info *, int);
111 static int cs4281_init(struct sc_info *);
112
113 /* talk to the card */
114 static u_int32_t cs4281_rd(struct sc_info *, int);
115 static void cs4281_wr(struct sc_info *, int, u_int32_t);
116
117 /* misc */
118 static u_int8_t cs4281_rate_to_rv(u_int32_t);
119 static u_int32_t cs4281_format_to_dmr(u_int32_t);
120 static u_int32_t cs4281_format_to_bps(u_int32_t);
121
122 /* -------------------------------------------------------------------- */
123 /* formats (do not add formats without editing cs_fmt_tab) */
124
125 static u_int32_t cs4281_fmts[] = {
126 SND_FORMAT(AFMT_U8, 1, 0),
127 SND_FORMAT(AFMT_U8, 2, 0),
128 SND_FORMAT(AFMT_S8, 1, 0),
129 SND_FORMAT(AFMT_S8, 2, 0),
130 SND_FORMAT(AFMT_S16_LE, 1, 0),
131 SND_FORMAT(AFMT_S16_LE, 2, 0),
132 SND_FORMAT(AFMT_U16_LE, 1, 0),
133 SND_FORMAT(AFMT_U16_LE, 2, 0),
134 SND_FORMAT(AFMT_S16_BE, 1, 0),
135 SND_FORMAT(AFMT_S16_BE, 2, 0),
136 SND_FORMAT(AFMT_U16_BE, 1, 0),
137 SND_FORMAT(AFMT_U16_BE, 2, 0),
138 0
139 };
140
141 static struct pcmchan_caps cs4281_caps = {6024, 48000, cs4281_fmts, 0};
142
143 /* -------------------------------------------------------------------- */
144 /* Hardware */
145
146 static inline u_int32_t
cs4281_rd(struct sc_info * sc,int regno)147 cs4281_rd(struct sc_info *sc, int regno)
148 {
149 return bus_space_read_4(sc->st, sc->sh, regno);
150 }
151
152 static inline void
cs4281_wr(struct sc_info * sc,int regno,u_int32_t data)153 cs4281_wr(struct sc_info *sc, int regno, u_int32_t data)
154 {
155 bus_space_write_4(sc->st, sc->sh, regno, data);
156 DELAY(100);
157 }
158
159 static inline void
cs4281_clr4(struct sc_info * sc,int regno,u_int32_t mask)160 cs4281_clr4(struct sc_info *sc, int regno, u_int32_t mask)
161 {
162 u_int32_t r;
163 r = cs4281_rd(sc, regno);
164 cs4281_wr(sc, regno, r & ~mask);
165 }
166
167 static inline void
cs4281_set4(struct sc_info * sc,int regno,u_int32_t mask)168 cs4281_set4(struct sc_info *sc, int regno, u_int32_t mask)
169 {
170 u_int32_t v;
171 v = cs4281_rd(sc, regno);
172 cs4281_wr(sc, regno, v | mask);
173 }
174
175 static int
cs4281_waitset(struct sc_info * sc,int regno,u_int32_t mask,int tries)176 cs4281_waitset(struct sc_info *sc, int regno, u_int32_t mask, int tries)
177 {
178 u_int32_t v;
179
180 while (tries > 0) {
181 DELAY(100);
182 v = cs4281_rd(sc, regno);
183 if ((v & mask) == mask) break;
184 tries --;
185 }
186 return tries;
187 }
188
189 static int
cs4281_waitclr(struct sc_info * sc,int regno,u_int32_t mask,int tries)190 cs4281_waitclr(struct sc_info *sc, int regno, u_int32_t mask, int tries)
191 {
192 u_int32_t v;
193
194 while (tries > 0) {
195 DELAY(100);
196 v = ~ cs4281_rd(sc, regno);
197 if (v & mask) break;
198 tries --;
199 }
200 return tries;
201 }
202
203 /* ------------------------------------------------------------------------- */
204 /* Register value mapping functions */
205
206 static u_int32_t cs4281_rates[] = {48000, 44100, 22050, 16000, 11025, 8000};
207 #define CS4281_NUM_RATES sizeof(cs4281_rates)/sizeof(cs4281_rates[0])
208
209 static u_int8_t
cs4281_rate_to_rv(u_int32_t rate)210 cs4281_rate_to_rv(u_int32_t rate)
211 {
212 u_int32_t v;
213
214 for (v = 0; v < CS4281_NUM_RATES; v++) {
215 if (rate == cs4281_rates[v]) return v;
216 }
217
218 v = 1536000 / rate;
219 if (v > 255 || v < 32) v = 5; /* default to 8k */
220 return v;
221 }
222
223 static u_int32_t
cs4281_rv_to_rate(u_int8_t rv)224 cs4281_rv_to_rate(u_int8_t rv)
225 {
226 u_int32_t r;
227
228 if (rv < CS4281_NUM_RATES) return cs4281_rates[rv];
229 r = 1536000 / rv;
230 return r;
231 }
232
233 static inline u_int32_t
cs4281_format_to_dmr(u_int32_t format)234 cs4281_format_to_dmr(u_int32_t format)
235 {
236 u_int32_t dmr = 0;
237 if (AFMT_8BIT & format) dmr |= CS4281PCI_DMR_SIZE8;
238 if (AFMT_CHANNEL(format) < 2) dmr |= CS4281PCI_DMR_MONO;
239 if (AFMT_BIGENDIAN & format) dmr |= CS4281PCI_DMR_BEND;
240 if (!(AFMT_SIGNED & format)) dmr |= CS4281PCI_DMR_USIGN;
241 return dmr;
242 }
243
244 static inline u_int32_t
cs4281_format_to_bps(u_int32_t format)245 cs4281_format_to_bps(u_int32_t format)
246 {
247 return ((AFMT_8BIT & format) ? 1 : 2) *
248 ((AFMT_CHANNEL(format) > 1) ? 2 : 1);
249 }
250
251 /* -------------------------------------------------------------------- */
252 /* ac97 codec */
253
254 static int
cs4281_rdcd(kobj_t obj,void * devinfo,int regno)255 cs4281_rdcd(kobj_t obj, void *devinfo, int regno)
256 {
257 struct sc_info *sc = (struct sc_info *)devinfo;
258 int codecno;
259
260 codecno = regno >> 8;
261 regno &= 0xff;
262
263 /* Remove old state */
264 cs4281_rd(sc, CS4281PCI_ACSDA);
265
266 /* Fill in AC97 register value request form */
267 cs4281_wr(sc, CS4281PCI_ACCAD, regno);
268 cs4281_wr(sc, CS4281PCI_ACCDA, 0);
269 cs4281_wr(sc, CS4281PCI_ACCTL, CS4281PCI_ACCTL_ESYN |
270 CS4281PCI_ACCTL_VFRM | CS4281PCI_ACCTL_DCV |
271 CS4281PCI_ACCTL_CRW);
272
273 /* Wait for read to complete */
274 if (cs4281_waitclr(sc, CS4281PCI_ACCTL, CS4281PCI_ACCTL_DCV, 250) == 0) {
275 device_printf(sc->dev, "cs4281_rdcd: DCV did not go\n");
276 return -1;
277 }
278
279 /* Wait for valid status */
280 if (cs4281_waitset(sc, CS4281PCI_ACSTS, CS4281PCI_ACSTS_VSTS, 250) == 0) {
281 device_printf(sc->dev,"cs4281_rdcd: VSTS did not come\n");
282 return -1;
283 }
284
285 return cs4281_rd(sc, CS4281PCI_ACSDA);
286 }
287
288 static int
cs4281_wrcd(kobj_t obj,void * devinfo,int regno,u_int32_t data)289 cs4281_wrcd(kobj_t obj, void *devinfo, int regno, u_int32_t data)
290 {
291 struct sc_info *sc = (struct sc_info *)devinfo;
292 int codecno;
293
294 codecno = regno >> 8;
295 regno &= 0xff;
296
297 cs4281_wr(sc, CS4281PCI_ACCAD, regno);
298 cs4281_wr(sc, CS4281PCI_ACCDA, data);
299 cs4281_wr(sc, CS4281PCI_ACCTL, CS4281PCI_ACCTL_ESYN |
300 CS4281PCI_ACCTL_VFRM | CS4281PCI_ACCTL_DCV);
301
302 if (cs4281_waitclr(sc, CS4281PCI_ACCTL, CS4281PCI_ACCTL_DCV, 250) == 0) {
303 device_printf(sc->dev,"cs4281_wrcd: DCV did not go\n");
304 }
305
306 return 0;
307 }
308
309 static kobj_method_t cs4281_ac97_methods[] = {
310 KOBJMETHOD(ac97_read, cs4281_rdcd),
311 KOBJMETHOD(ac97_write, cs4281_wrcd),
312 KOBJMETHOD_END
313 };
314 AC97_DECLARE(cs4281_ac97);
315
316 /* ------------------------------------------------------------------------- */
317 /* shared rec/play channel interface */
318
319 static void *
cs4281chan_init(kobj_t obj,void * devinfo,struct snd_dbuf * b,struct pcm_channel * c,int dir)320 cs4281chan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
321 {
322 struct sc_info *sc = devinfo;
323 struct sc_chinfo *ch = (dir == PCMDIR_PLAY) ? &sc->pch : &sc->rch;
324
325 ch->buffer = b;
326 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, 0, sc->bufsz) != 0) {
327 return NULL;
328 }
329 ch->parent = sc;
330 ch->channel = c;
331
332 ch->fmt = SND_FORMAT(AFMT_U8, 1, 0);
333 ch->spd = DSP_DEFAULT_SPEED;
334 ch->bps = 1;
335 ch->blksz = sndbuf_getsize(ch->buffer);
336
337 ch->dma_chan = (dir == PCMDIR_PLAY) ? CS4281_DMA_PLAY : CS4281_DMA_REC;
338 ch->dma_setup = 0;
339
340 adcdac_go(ch, 0);
341 adcdac_prog(ch);
342
343 return ch;
344 }
345
346 static u_int32_t
cs4281chan_setblocksize(kobj_t obj,void * data,u_int32_t blocksize)347 cs4281chan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
348 {
349 struct sc_chinfo *ch = data;
350 struct sc_info *sc = ch->parent;
351 u_int32_t go;
352
353 go = adcdac_go(ch, 0);
354
355 /* 2 interrupts are possible and used in buffer (half-empty,empty),
356 * hence factor of 2. */
357 ch->blksz = MIN(blocksize, sc->bufsz / 2);
358 sndbuf_resize(ch->buffer, 2, ch->blksz);
359 ch->dma_setup = 0;
360 adcdac_prog(ch);
361 adcdac_go(ch, go);
362
363 DEB(printf("cs4281chan_setblocksize: blksz %d Setting %d\n", blocksize, ch->blksz));
364
365 return ch->blksz;
366 }
367
368 static u_int32_t
cs4281chan_setspeed(kobj_t obj,void * data,u_int32_t speed)369 cs4281chan_setspeed(kobj_t obj, void *data, u_int32_t speed)
370 {
371 struct sc_chinfo *ch = data;
372 struct sc_info *sc = ch->parent;
373 u_int32_t go, v, r;
374
375 go = adcdac_go(ch, 0); /* pause */
376 r = (ch->dma_chan == CS4281_DMA_PLAY) ? CS4281PCI_DACSR : CS4281PCI_ADCSR;
377 v = cs4281_rate_to_rv(speed);
378 cs4281_wr(sc, r, v);
379 adcdac_go(ch, go); /* unpause */
380
381 ch->spd = cs4281_rv_to_rate(v);
382 return ch->spd;
383 }
384
385 static int
cs4281chan_setformat(kobj_t obj,void * data,u_int32_t format)386 cs4281chan_setformat(kobj_t obj, void *data, u_int32_t format)
387 {
388 struct sc_chinfo *ch = data;
389 struct sc_info *sc = ch->parent;
390 u_int32_t v, go;
391
392 go = adcdac_go(ch, 0); /* pause */
393
394 if (ch->dma_chan == CS4281_DMA_PLAY)
395 v = CS4281PCI_DMR_TR_PLAY;
396 else
397 v = CS4281PCI_DMR_TR_REC;
398 v |= CS4281PCI_DMR_DMA | CS4281PCI_DMR_AUTO;
399 v |= cs4281_format_to_dmr(format);
400 cs4281_wr(sc, CS4281PCI_DMR(ch->dma_chan), v);
401
402 adcdac_go(ch, go); /* unpause */
403
404 ch->fmt = format;
405 ch->bps = cs4281_format_to_bps(format);
406 ch->dma_setup = 0;
407
408 return 0;
409 }
410
411 static u_int32_t
cs4281chan_getptr(kobj_t obj,void * data)412 cs4281chan_getptr(kobj_t obj, void *data)
413 {
414 struct sc_chinfo *ch = data;
415 struct sc_info *sc = ch->parent;
416 u_int32_t dba, dca, ptr;
417 int sz;
418
419 sz = sndbuf_getsize(ch->buffer);
420 dba = cs4281_rd(sc, CS4281PCI_DBA(ch->dma_chan));
421 dca = cs4281_rd(sc, CS4281PCI_DCA(ch->dma_chan));
422 ptr = (dca - dba + sz) % sz;
423
424 return ptr;
425 }
426
427 static int
cs4281chan_trigger(kobj_t obj,void * data,int go)428 cs4281chan_trigger(kobj_t obj, void *data, int go)
429 {
430 struct sc_chinfo *ch = data;
431
432 switch(go) {
433 case PCMTRIG_START:
434 adcdac_prog(ch);
435 adcdac_go(ch, 1);
436 break;
437 case PCMTRIG_STOP:
438 case PCMTRIG_ABORT:
439 adcdac_go(ch, 0);
440 break;
441 default:
442 break;
443 }
444
445 /* return 0 if ok */
446 return 0;
447 }
448
449 static struct pcmchan_caps *
cs4281chan_getcaps(kobj_t obj,void * data)450 cs4281chan_getcaps(kobj_t obj, void *data)
451 {
452 return &cs4281_caps;
453 }
454
455 static kobj_method_t cs4281chan_methods[] = {
456 KOBJMETHOD(channel_init, cs4281chan_init),
457 KOBJMETHOD(channel_setformat, cs4281chan_setformat),
458 KOBJMETHOD(channel_setspeed, cs4281chan_setspeed),
459 KOBJMETHOD(channel_setblocksize, cs4281chan_setblocksize),
460 KOBJMETHOD(channel_trigger, cs4281chan_trigger),
461 KOBJMETHOD(channel_getptr, cs4281chan_getptr),
462 KOBJMETHOD(channel_getcaps, cs4281chan_getcaps),
463 KOBJMETHOD_END
464 };
465 CHANNEL_DECLARE(cs4281chan);
466
467 /* -------------------------------------------------------------------- */
468 /* ADC/DAC control */
469
470 /* adcdac_go enables/disable DMA channel, returns non-zero if DMA was
471 * active before call */
472
473 static u_int32_t
adcdac_go(struct sc_chinfo * ch,u_int32_t go)474 adcdac_go(struct sc_chinfo *ch, u_int32_t go)
475 {
476 struct sc_info *sc = ch->parent;
477 u_int32_t going;
478
479 going = !(cs4281_rd(sc, CS4281PCI_DCR(ch->dma_chan)) & CS4281PCI_DCR_MSK);
480
481 if (go)
482 cs4281_clr4(sc, CS4281PCI_DCR(ch->dma_chan), CS4281PCI_DCR_MSK);
483 else
484 cs4281_set4(sc, CS4281PCI_DCR(ch->dma_chan), CS4281PCI_DCR_MSK);
485
486 cs4281_wr(sc, CS4281PCI_HICR, CS4281PCI_HICR_EOI);
487
488 return going;
489 }
490
491 static void
adcdac_prog(struct sc_chinfo * ch)492 adcdac_prog(struct sc_chinfo *ch)
493 {
494 struct sc_info *sc = ch->parent;
495 u_int32_t go;
496
497 if (!ch->dma_setup) {
498 go = adcdac_go(ch, 0);
499 cs4281_wr(sc, CS4281PCI_DBA(ch->dma_chan),
500 sndbuf_getbufaddr(ch->buffer));
501 cs4281_wr(sc, CS4281PCI_DBC(ch->dma_chan),
502 sndbuf_getsize(ch->buffer) / ch->bps - 1);
503 ch->dma_setup = 1;
504 adcdac_go(ch, go);
505 }
506 }
507
508 /* -------------------------------------------------------------------- */
509 /* The interrupt handler */
510
511 static void
cs4281_intr(void * p)512 cs4281_intr(void *p)
513 {
514 struct sc_info *sc = (struct sc_info *)p;
515 u_int32_t hisr;
516
517 hisr = cs4281_rd(sc, CS4281PCI_HISR);
518
519 if (hisr == 0) return;
520
521 if (hisr & CS4281PCI_HISR_DMA(CS4281_DMA_PLAY)) {
522 chn_intr(sc->pch.channel);
523 cs4281_rd(sc, CS4281PCI_HDSR(CS4281_DMA_PLAY)); /* Clear interrupt */
524 }
525
526 if (hisr & CS4281PCI_HISR_DMA(CS4281_DMA_REC)) {
527 chn_intr(sc->rch.channel);
528 cs4281_rd(sc, CS4281PCI_HDSR(CS4281_DMA_REC)); /* Clear interrupt */
529 }
530
531 /* Signal End-of-Interrupt */
532 cs4281_wr(sc, CS4281PCI_HICR, CS4281PCI_HICR_EOI);
533 }
534
535 /* -------------------------------------------------------------------- */
536 /* power management related */
537
538 static int
cs4281_power(struct sc_info * sc,int state)539 cs4281_power(struct sc_info *sc, int state)
540 {
541
542 switch (state) {
543 case 0:
544 /* Permit r/w access to all BA0 registers */
545 cs4281_wr(sc, CS4281PCI_CWPR, CS4281PCI_CWPR_MAGIC);
546 /* Power on */
547 cs4281_clr4(sc, CS4281PCI_EPPMC, CS4281PCI_EPPMC_FPDN);
548 break;
549 case 3:
550 /* Power off card and codec */
551 cs4281_set4(sc, CS4281PCI_EPPMC, CS4281PCI_EPPMC_FPDN);
552 cs4281_clr4(sc, CS4281PCI_SPMC, CS4281PCI_SPMC_RSTN);
553 break;
554 }
555
556 DEB(printf("cs4281_power %d -> %d\n", sc->power, state));
557 sc->power = state;
558
559 return 0;
560 }
561
562 static int
cs4281_init(struct sc_info * sc)563 cs4281_init(struct sc_info *sc)
564 {
565 u_int32_t i, v;
566
567 /* (0) Blast clock register and serial port */
568 cs4281_wr(sc, CS4281PCI_CLKCR1, 0);
569 cs4281_wr(sc, CS4281PCI_SERMC, 0);
570
571 /* (1) Make ESYN 0 to turn sync pulse on AC97 link */
572 cs4281_wr(sc, CS4281PCI_ACCTL, 0);
573 DELAY(50);
574
575 /* (2) Effect Reset */
576 cs4281_wr(sc, CS4281PCI_SPMC, 0);
577 DELAY(100);
578 cs4281_wr(sc, CS4281PCI_SPMC, CS4281PCI_SPMC_RSTN);
579 /* Wait 50ms for ABITCLK to become stable */
580 DELAY(50000);
581
582 /* (3) Enable Sound System Clocks */
583 cs4281_wr(sc, CS4281PCI_CLKCR1, CS4281PCI_CLKCR1_DLLP);
584 DELAY(50000); /* Wait for PLL to stabilize */
585 cs4281_wr(sc, CS4281PCI_CLKCR1,
586 CS4281PCI_CLKCR1_DLLP | CS4281PCI_CLKCR1_SWCE);
587
588 /* (4) Power Up - this combination is essential. */
589 cs4281_set4(sc, CS4281PCI_SSPM,
590 CS4281PCI_SSPM_ACLEN | CS4281PCI_SSPM_PSRCEN |
591 CS4281PCI_SSPM_CSRCEN | CS4281PCI_SSPM_MIXEN);
592
593 /* (5) Wait for clock stabilization */
594 if (cs4281_waitset(sc,
595 CS4281PCI_CLKCR1,
596 CS4281PCI_CLKCR1_DLLRDY,
597 250) == 0) {
598 device_printf(sc->dev, "Clock stabilization failed\n");
599 return -1;
600 }
601
602 /* (6) Enable ASYNC generation. */
603 cs4281_wr(sc, CS4281PCI_ACCTL,CS4281PCI_ACCTL_ESYN);
604
605 /* Wait to allow AC97 to start generating clock bit */
606 DELAY(50000);
607
608 /* Set AC97 timing */
609 cs4281_wr(sc, CS4281PCI_SERMC, CS4281PCI_SERMC_PTC_AC97);
610
611 /* (7) Wait for AC97 ready signal */
612 if (cs4281_waitset(sc, CS4281PCI_ACSTS, CS4281PCI_ACSTS_CRDY, 250) == 0) {
613 device_printf(sc->dev, "codec did not avail\n");
614 return -1;
615 }
616
617 /* (8) Assert valid frame signal to begin sending commands to
618 * AC97 codec */
619 cs4281_wr(sc,
620 CS4281PCI_ACCTL,
621 CS4281PCI_ACCTL_VFRM | CS4281PCI_ACCTL_ESYN);
622
623 /* (9) Wait for codec calibration */
624 for(i = 0 ; i < 1000; i++) {
625 DELAY(10000);
626 v = cs4281_rdcd(0, sc, AC97_REG_POWER);
627 if ((v & 0x0f) == 0x0f) {
628 break;
629 }
630 }
631 if (i == 1000) {
632 device_printf(sc->dev, "codec failed to calibrate\n");
633 return -1;
634 }
635
636 /* (10) Set AC97 timing */
637 cs4281_wr(sc, CS4281PCI_SERMC, CS4281PCI_SERMC_PTC_AC97);
638
639 /* (11) Wait for valid data to arrive */
640 if (cs4281_waitset(sc,
641 CS4281PCI_ACISV,
642 CS4281PCI_ACISV_ISV(3) | CS4281PCI_ACISV_ISV(4),
643 10000) == 0) {
644 device_printf(sc->dev, "cs4281 never got valid data\n");
645 return -1;
646 }
647
648 /* (12) Start digital data transfer of audio data to codec */
649 cs4281_wr(sc,
650 CS4281PCI_ACOSV,
651 CS4281PCI_ACOSV_SLV(3) | CS4281PCI_ACOSV_SLV(4));
652
653 /* Set Master and headphone to max */
654 cs4281_wrcd(0, sc, AC97_MIX_AUXOUT, 0);
655 cs4281_wrcd(0, sc, AC97_MIX_MASTER, 0);
656
657 /* Power on the DAC */
658 v = cs4281_rdcd(0, sc, AC97_REG_POWER) & 0xfdff;
659 cs4281_wrcd(0, sc, AC97_REG_POWER, v);
660
661 /* Wait until DAC state ready */
662 for(i = 0; i < 320; i++) {
663 DELAY(100);
664 v = cs4281_rdcd(0, sc, AC97_REG_POWER);
665 if (v & 0x02) break;
666 }
667
668 /* Power on the ADC */
669 v = cs4281_rdcd(0, sc, AC97_REG_POWER) & 0xfeff;
670 cs4281_wrcd(0, sc, AC97_REG_POWER, v);
671
672 /* Wait until ADC state ready */
673 for(i = 0; i < 320; i++) {
674 DELAY(100);
675 v = cs4281_rdcd(0, sc, AC97_REG_POWER);
676 if (v & 0x01) break;
677 }
678
679 /* FIFO configuration (driver is DMA orientated, implicit FIFO) */
680 /* Play FIFO */
681
682 v = CS4281PCI_FCR_RS(CS4281PCI_RPCM_PLAY_SLOT) |
683 CS4281PCI_FCR_LS(CS4281PCI_LPCM_PLAY_SLOT) |
684 CS4281PCI_FCR_SZ(CS4281_FIFO_SIZE)|
685 CS4281PCI_FCR_OF(0);
686 cs4281_wr(sc, CS4281PCI_FCR(CS4281_DMA_PLAY), v);
687
688 cs4281_wr(sc, CS4281PCI_FCR(CS4281_DMA_PLAY), v | CS4281PCI_FCR_FEN);
689
690 /* Record FIFO */
691 v = CS4281PCI_FCR_RS(CS4281PCI_RPCM_REC_SLOT) |
692 CS4281PCI_FCR_LS(CS4281PCI_LPCM_REC_SLOT) |
693 CS4281PCI_FCR_SZ(CS4281_FIFO_SIZE)|
694 CS4281PCI_FCR_OF(CS4281_FIFO_SIZE + 1);
695 cs4281_wr(sc, CS4281PCI_FCR(CS4281_DMA_REC), v | CS4281PCI_FCR_PSH);
696 cs4281_wr(sc, CS4281PCI_FCR(CS4281_DMA_REC), v | CS4281PCI_FCR_FEN);
697
698 /* Match AC97 slots to FIFOs */
699 v = CS4281PCI_SRCSA_PLSS(CS4281PCI_LPCM_PLAY_SLOT) |
700 CS4281PCI_SRCSA_PRSS(CS4281PCI_RPCM_PLAY_SLOT) |
701 CS4281PCI_SRCSA_CLSS(CS4281PCI_LPCM_REC_SLOT) |
702 CS4281PCI_SRCSA_CRSS(CS4281PCI_RPCM_REC_SLOT);
703 cs4281_wr(sc, CS4281PCI_SRCSA, v);
704
705 /* Set Auto-Initialize and set directions */
706 cs4281_wr(sc,
707 CS4281PCI_DMR(CS4281_DMA_PLAY),
708 CS4281PCI_DMR_DMA |
709 CS4281PCI_DMR_AUTO |
710 CS4281PCI_DMR_TR_PLAY);
711 cs4281_wr(sc,
712 CS4281PCI_DMR(CS4281_DMA_REC),
713 CS4281PCI_DMR_DMA |
714 CS4281PCI_DMR_AUTO |
715 CS4281PCI_DMR_TR_REC);
716
717 /* Enable half and empty buffer interrupts keeping DMA paused */
718 cs4281_wr(sc,
719 CS4281PCI_DCR(CS4281_DMA_PLAY),
720 CS4281PCI_DCR_TCIE | CS4281PCI_DCR_HTCIE | CS4281PCI_DCR_MSK);
721 cs4281_wr(sc,
722 CS4281PCI_DCR(CS4281_DMA_REC),
723 CS4281PCI_DCR_TCIE | CS4281PCI_DCR_HTCIE | CS4281PCI_DCR_MSK);
724
725 /* Enable Interrupts */
726 cs4281_clr4(sc,
727 CS4281PCI_HIMR,
728 CS4281PCI_HIMR_DMAI |
729 CS4281PCI_HIMR_DMA(CS4281_DMA_PLAY) |
730 CS4281PCI_HIMR_DMA(CS4281_DMA_REC));
731
732 /* Set playback volume */
733 cs4281_wr(sc, CS4281PCI_PPLVC, 7);
734 cs4281_wr(sc, CS4281PCI_PPRVC, 7);
735
736 return 0;
737 }
738
739 /* -------------------------------------------------------------------- */
740 /* Probe and attach the card */
741
742 static int
cs4281_pci_probe(device_t dev)743 cs4281_pci_probe(device_t dev)
744 {
745 char *s = NULL;
746
747 switch (pci_get_devid(dev)) {
748 case CS4281_PCI_ID:
749 s = "Crystal Semiconductor CS4281";
750 break;
751 }
752
753 if (s)
754 device_set_desc(dev, s);
755 return s ? BUS_PROBE_DEFAULT : ENXIO;
756 }
757
758 static int
cs4281_pci_attach(device_t dev)759 cs4281_pci_attach(device_t dev)
760 {
761 struct sc_info *sc;
762 struct ac97_info *codec = NULL;
763 char status[SND_STATUSLEN];
764
765 sc = kmalloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO);
766 sc->dev = dev;
767 sc->type = pci_get_devid(dev);
768
769 pci_enable_busmaster(dev);
770
771 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
772 /* Reset the power state. */
773 device_printf(dev, "chip is in D%d power mode "
774 "-- setting to D0\n", pci_get_powerstate(dev));
775
776 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
777 }
778
779 sc->regid = PCIR_BAR(0);
780 sc->regtype = SYS_RES_MEMORY;
781 sc->reg = bus_alloc_resource(dev, sc->regtype, &sc->regid,
782 0, ~0, CS4281PCI_BA0_SIZE, RF_ACTIVE);
783 if (!sc->reg) {
784 sc->regtype = SYS_RES_IOPORT;
785 sc->reg = bus_alloc_resource(dev, sc->regtype, &sc->regid,
786 0, ~0, CS4281PCI_BA0_SIZE, RF_ACTIVE);
787 if (!sc->reg) {
788 device_printf(dev, "unable to allocate register space\n");
789 goto bad;
790 }
791 }
792 sc->st = rman_get_bustag(sc->reg);
793 sc->sh = rman_get_bushandle(sc->reg);
794
795 sc->memid = PCIR_BAR(1);
796 sc->mem = bus_alloc_resource(dev, SYS_RES_MEMORY, &sc->memid, 0,
797 ~0, CS4281PCI_BA1_SIZE, RF_ACTIVE);
798 if (sc->mem == NULL) {
799 device_printf(dev, "unable to allocate fifo space\n");
800 goto bad;
801 }
802
803 sc->irqid = 0;
804 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid,
805 RF_ACTIVE | RF_SHAREABLE);
806 if (!sc->irq) {
807 device_printf(dev, "unable to allocate interrupt\n");
808 goto bad;
809 }
810
811 if (snd_setup_intr(dev, sc->irq, 0, cs4281_intr, sc, &sc->ih)) {
812 device_printf(dev, "unable to setup interrupt\n");
813 goto bad;
814 }
815
816 sc->bufsz = pcm_getbuffersize(dev, 4096, CS4281_DEFAULT_BUFSZ, 65536);
817
818 if (bus_dma_tag_create(/*parent*/bus_get_dma_tag(dev), /*alignment*/2,
819 /*boundary*/0,
820 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
821 /*highaddr*/BUS_SPACE_MAXADDR,
822 /*maxsize*/sc->bufsz, /*nsegments*/1,
823 /*maxsegz*/0x3ffff,
824 /*flags*/0,
825 &sc->parent_dmat) != 0) {
826 device_printf(dev, "unable to create dma tag\n");
827 goto bad;
828 }
829
830 /* power up */
831 cs4281_power(sc, 0);
832
833 /* init chip */
834 if (cs4281_init(sc) == -1) {
835 device_printf(dev, "unable to initialize the card\n");
836 goto bad;
837 }
838
839 /* create/init mixer */
840 codec = AC97_CREATE(dev, sc, cs4281_ac97);
841 if (codec == NULL)
842 goto bad;
843
844 mixer_init(dev, ac97_getmixerclass(), codec);
845
846 if (pcm_register(dev, sc, 1, 1))
847 goto bad;
848
849 pcm_addchan(dev, PCMDIR_PLAY, &cs4281chan_class, sc);
850 pcm_addchan(dev, PCMDIR_REC, &cs4281chan_class, sc);
851
852 ksnprintf(status, SND_STATUSLEN, "at %s 0x%lx irq %ld %s",
853 (sc->regtype == SYS_RES_IOPORT)? "io" : "memory",
854 rman_get_start(sc->reg), rman_get_start(sc->irq),PCM_KLDSTRING(snd_cs4281));
855 pcm_setstatus(dev, status);
856
857 return 0;
858
859 bad:
860 if (codec)
861 ac97_destroy(codec);
862 if (sc->reg)
863 bus_release_resource(dev, sc->regtype, sc->regid, sc->reg);
864 if (sc->mem)
865 bus_release_resource(dev, SYS_RES_MEMORY, sc->memid, sc->mem);
866 if (sc->ih)
867 bus_teardown_intr(dev, sc->irq, sc->ih);
868 if (sc->irq)
869 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
870 if (sc->parent_dmat)
871 bus_dma_tag_destroy(sc->parent_dmat);
872 kfree(sc, M_DEVBUF);
873
874 return ENXIO;
875 }
876
877 static int
cs4281_pci_detach(device_t dev)878 cs4281_pci_detach(device_t dev)
879 {
880 int r;
881 struct sc_info *sc;
882
883 r = pcm_unregister(dev);
884 if (r)
885 return r;
886
887 sc = pcm_getdevinfo(dev);
888
889 /* power off */
890 cs4281_power(sc, 3);
891
892 bus_release_resource(dev, sc->regtype, sc->regid, sc->reg);
893 bus_release_resource(dev, SYS_RES_MEMORY, sc->memid, sc->mem);
894 bus_teardown_intr(dev, sc->irq, sc->ih);
895 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
896 bus_dma_tag_destroy(sc->parent_dmat);
897 kfree(sc, M_DEVBUF);
898
899 return 0;
900 }
901
902 static int
cs4281_pci_suspend(device_t dev)903 cs4281_pci_suspend(device_t dev)
904 {
905 struct sc_info *sc;
906
907 sc = pcm_getdevinfo(dev);
908
909 sc->rch.dma_active = adcdac_go(&sc->rch, 0);
910 sc->pch.dma_active = adcdac_go(&sc->pch, 0);
911
912 cs4281_power(sc, 3);
913
914 return 0;
915 }
916
917 static int
cs4281_pci_resume(device_t dev)918 cs4281_pci_resume(device_t dev)
919 {
920 struct sc_info *sc;
921
922 sc = pcm_getdevinfo(dev);
923
924 /* power up */
925 cs4281_power(sc, 0);
926
927 /* initialize chip */
928 if (cs4281_init(sc) == -1) {
929 device_printf(dev, "unable to reinitialize the card\n");
930 return ENXIO;
931 }
932
933 /* restore mixer state */
934 if (mixer_reinit(dev) == -1) {
935 device_printf(dev, "unable to reinitialize the mixer\n");
936 return ENXIO;
937 }
938
939 /* restore chip state */
940 cs4281chan_setspeed(NULL, &sc->rch, sc->rch.spd);
941 cs4281chan_setblocksize(NULL, &sc->rch, sc->rch.blksz);
942 cs4281chan_setformat(NULL, &sc->rch, sc->rch.fmt);
943 adcdac_go(&sc->rch, sc->rch.dma_active);
944
945 cs4281chan_setspeed(NULL, &sc->pch, sc->pch.spd);
946 cs4281chan_setblocksize(NULL, &sc->pch, sc->pch.blksz);
947 cs4281chan_setformat(NULL, &sc->pch, sc->pch.fmt);
948 adcdac_go(&sc->pch, sc->pch.dma_active);
949
950 return 0;
951 }
952
953 static device_method_t cs4281_methods[] = {
954 /* Device interface */
955 DEVMETHOD(device_probe, cs4281_pci_probe),
956 DEVMETHOD(device_attach, cs4281_pci_attach),
957 DEVMETHOD(device_detach, cs4281_pci_detach),
958 DEVMETHOD(device_suspend, cs4281_pci_suspend),
959 DEVMETHOD(device_resume, cs4281_pci_resume),
960 { 0, 0 }
961 };
962
963 static driver_t cs4281_driver = {
964 "pcm",
965 cs4281_methods,
966 PCM_SOFTC_SIZE,
967 };
968
969 DRIVER_MODULE(snd_cs4281, pci, cs4281_driver, pcm_devclass, NULL, NULL);
970 MODULE_DEPEND(snd_cs4281, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
971 MODULE_VERSION(snd_cs4281, 1);
972