Searched defs:csrr (Results 1 – 20 of 20) sorted by relevance
| /dports/devel/wasm3/wasm3-0.5.0/platforms/embedded/fomu/include/ |
| H A D | system.h | 32 #define csrr(reg) ({ unsigned long __tmp; \ macro
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| /dports/audio/supercollider/SuperCollider-3.11.0-Source/external_libraries/boost/boost/config/compiler/ |
| H A D | xlcpp_zos.hpp | 131
132 #define BOOST_NO_CXX11_UNIFIED_INITIALIZATION_SYNTAX
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| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/MC/RISCV/ |
| H A D | rvi-aliases-valid.s | 188 csrr x8, 0x150 label
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| /dports/devel/llvm11/llvm-11.0.1.src/test/MC/RISCV/ |
| H A D | rvi-aliases-valid.s | 188 csrr x8, 0x150 label
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| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/MC/RISCV/ |
| H A D | rvi-aliases-valid.s | 212 csrr x8, 0x150 label
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| /dports/devel/llvm10/llvm-10.0.1.src/test/MC/RISCV/ |
| H A D | rvi-aliases-valid.s | 188 csrr x8, 0x150 label
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| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/MC/RISCV/ |
| H A D | rvi-aliases-valid.s | 212 csrr x8, 0x150 label
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| /dports/devel/llvm90/llvm-9.0.1.src/test/MC/RISCV/ |
| H A D | rvi-aliases-valid.s | 188 csrr x8, 0x150 label
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| /dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/MC/RISCV/ |
| H A D | rvi-aliases-valid.s | 188 csrr x8, 0x150 label
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| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/MC/RISCV/ |
| H A D | rvi-aliases-valid.s | 188 csrr x8, 0x150 label
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| /dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/MC/RISCV/ |
| H A D | rvi-aliases-valid.s | 212 csrr x8, 0x150 label
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| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/MC/RISCV/ |
| H A D | rvi-aliases-valid.s | 212 csrr x8, 0x150 label
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| /dports/graphics/llvm-mesa/llvm-13.0.1.src/test/MC/RISCV/ |
| H A D | rvi-aliases-valid.s | 212 csrr x8, 0x150 label
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| /dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/MC/RISCV/ |
| H A D | rvi-aliases-valid.s | 212 csrr x8, 0x150 label
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| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/MC/RISCV/ |
| H A D | rvi-aliases-valid.s | 212 csrr x8, 0x150 label
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| /dports/emulators/riscv-isa-sim/riscv-isa-sim-4f12984/riscv/ |
| H A D | opcodes.h | 124 static uint32_t csrr(unsigned int rd, unsigned int csr) { in csrr() function
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| /dports/devel/openocd/openocd-0.11.0/src/target/riscv/ |
| H A D | opcodes.h | 131 static uint32_t csrr(unsigned int rd, unsigned int csr) in csrr() function
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| /dports/emulators/mess/mame-mame0226/src/mame/video/ |
| H A D | mcd212.h | 142 uint8_t csrr; member
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| /dports/emulators/mame/mame-mame0226/src/mame/video/ |
| H A D | mcd212.h | 142 uint8_t csrr; member
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| /dports/lang/v8/v8-9.6.180.12/src/codegen/riscv64/ |
| H A D | assembler-riscv64.h | 1010 void csrr(Register rd, ControlStatusReg csr) { csrrs(rd, csr, zero_reg); } in csrr() function
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