1 /* $OpenBSD: athnvar.h,v 1.42 2021/04/15 18:25:43 stsp Exp $ */ 2 3 /*- 4 * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifdef notyet 20 #define ATHN_BT_COEXISTENCE 1 21 #endif 22 23 #ifdef ATHN_DEBUG 24 #define DPRINTF(x) do { if (athn_debug > 0) printf x; } while (0) 25 #define DPRINTFN(n, x) do { if (athn_debug >= (n)) printf x; } while (0) 26 extern int athn_debug; 27 #else 28 #define DPRINTF(x) 29 #define DPRINTFN(n, x) 30 #endif 31 32 #define LE_READ_4(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24) 33 #define LE_READ_2(p) ((p)[0] | (p)[1] << 8) 34 35 #define ATHN_RXBUFSZ 3872 36 #define ATHN_TXBUFSZ 4096 37 38 #define ATHN_NRXBUFS 64 39 #define ATHN_NTXBUFS 64 /* Shared between all Tx queues. */ 40 41 struct athn_rx_radiotap_header { 42 struct ieee80211_radiotap_header wr_ihdr; 43 uint64_t wr_tsft; 44 uint8_t wr_flags; 45 uint8_t wr_rate; 46 uint16_t wr_chan_freq; 47 uint16_t wr_chan_flags; 48 int8_t wr_dbm_antsignal; 49 uint8_t wr_antenna; 50 } __packed; 51 52 #define ATHN_RX_RADIOTAP_PRESENT \ 53 (1 << IEEE80211_RADIOTAP_TSFT | \ 54 1 << IEEE80211_RADIOTAP_FLAGS | \ 55 1 << IEEE80211_RADIOTAP_RATE | \ 56 1 << IEEE80211_RADIOTAP_CHANNEL | \ 57 1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL | \ 58 1 << IEEE80211_RADIOTAP_ANTENNA) 59 60 struct athn_tx_radiotap_header { 61 struct ieee80211_radiotap_header wt_ihdr; 62 uint8_t wt_flags; 63 uint8_t wt_rate; 64 uint16_t wt_chan_freq; 65 uint16_t wt_chan_flags; 66 } __packed; 67 68 #define ATHN_TX_RADIOTAP_PRESENT \ 69 (1 << IEEE80211_RADIOTAP_FLAGS | \ 70 1 << IEEE80211_RADIOTAP_RATE | \ 71 1 << IEEE80211_RADIOTAP_CHANNEL) 72 73 struct athn_tx_buf { 74 SIMPLEQ_ENTRY(athn_tx_buf) bf_list; 75 76 void *bf_descs; 77 bus_dmamap_t bf_map; 78 bus_addr_t bf_daddr; 79 80 struct mbuf *bf_m; 81 struct ieee80211_node *bf_ni; 82 int bf_txmcs; 83 int bf_txflags; 84 #define ATHN_TXFLAG_PAPRD (1 << 0) 85 #define ATHN_TXFLAG_CAB (1 << 1) 86 }; 87 88 struct athn_txq { 89 SIMPLEQ_HEAD(, athn_tx_buf) head; 90 void *lastds; 91 struct athn_tx_buf *wait; 92 int queued; 93 }; 94 95 struct athn_rx_buf { 96 SIMPLEQ_ENTRY(athn_rx_buf) bf_list; 97 98 void *bf_desc; 99 bus_dmamap_t bf_map; 100 101 struct mbuf *bf_m; 102 bus_addr_t bf_daddr; 103 }; 104 105 struct athn_rxq { 106 struct athn_rx_buf *bf; 107 108 void *descs; 109 void *lastds; 110 bus_dmamap_t map; 111 bus_dma_segment_t seg; 112 int count; 113 114 SIMPLEQ_HEAD(, athn_rx_buf) head; 115 }; 116 117 /* Software rate indexes. */ 118 #define ATHN_RIDX_CCK1 0 119 #define ATHN_RIDX_CCK2 1 120 #define ATHN_RIDX_OFDM6 4 121 #define ATHN_RIDX_MCS0 12 122 #define ATHN_RIDX_MCS8 (ATHN_RIDX_MCS0 + 8) 123 #define ATHN_RIDX_MCS15 27 124 #define ATHN_RIDX_MAX 27 125 #define ATHN_MCS_MAX 15 126 #define ATHN_NUM_MCS (ATHN_MCS_MAX + 1) 127 #define ATHN_IS_HT_RIDX(ridx) ((ridx) >= ATHN_RIDX_MCS0) 128 #define ATHN_IS_MIMO_RIDX(ridx) ((ridx) >= ATHN_RIDX_MCS8) 129 130 static const struct athn_rate { 131 uint16_t rate; /* Rate in 500Kbps unit. */ 132 uint8_t hwrate; /* HW representation. */ 133 uint8_t rspridx; /* Control Response Frame rate index. */ 134 enum ieee80211_phytype phy; 135 } athn_rates[] = { 136 { 2, 0x1b, 0, IEEE80211_T_DS }, 137 { 4, 0x1a, 1, IEEE80211_T_DS }, 138 { 11, 0x19, 1, IEEE80211_T_DS }, 139 { 22, 0x18, 1, IEEE80211_T_DS }, 140 { 12, 0x0b, 4, IEEE80211_T_OFDM }, 141 { 18, 0x0f, 4, IEEE80211_T_OFDM }, 142 { 24, 0x0a, 6, IEEE80211_T_OFDM }, 143 { 36, 0x0e, 6, IEEE80211_T_OFDM }, 144 { 48, 0x09, 8, IEEE80211_T_OFDM }, 145 { 72, 0x0d, 8, IEEE80211_T_OFDM }, 146 { 96, 0x08, 8, IEEE80211_T_OFDM }, 147 { 108, 0x0c, 8, IEEE80211_T_OFDM }, 148 { 13, 0x80, 4, IEEE80211_T_OFDM }, 149 { 26, 0x81, 6, IEEE80211_T_OFDM }, 150 { 39, 0x82, 6, IEEE80211_T_OFDM }, 151 { 52, 0x83, 8, IEEE80211_T_OFDM }, 152 { 78, 0x84, 8, IEEE80211_T_OFDM }, 153 { 104, 0x85, 8, IEEE80211_T_OFDM }, 154 { 117, 0x86, 8, IEEE80211_T_OFDM }, 155 { 130, 0x87, 8, IEEE80211_T_OFDM }, 156 { 26, 0x88, 4, IEEE80211_T_OFDM }, 157 { 52, 0x89, 6, IEEE80211_T_OFDM }, 158 { 78, 0x8a, 8, IEEE80211_T_OFDM }, 159 { 104, 0x8b, 8, IEEE80211_T_OFDM }, 160 { 156, 0x8c, 8, IEEE80211_T_OFDM }, 161 { 208, 0x8d, 8, IEEE80211_T_OFDM }, 162 { 234, 0x8e, 8, IEEE80211_T_OFDM }, 163 { 260, 0x8f, 8, IEEE80211_T_OFDM } 164 }; 165 166 struct athn_series { 167 uint16_t dur; 168 uint8_t hwrate; 169 }; 170 171 struct athn_pier { 172 uint8_t fbin; 173 const uint8_t *pwr[AR_PD_GAINS_IN_MASK]; 174 const uint8_t *vpd[AR_PD_GAINS_IN_MASK]; 175 }; 176 177 /* 178 * Structures used to store initialization values. 179 */ 180 struct athn_ini { 181 int nregs; 182 const uint16_t *regs; 183 const uint32_t *vals_5g20; 184 const uint32_t *vals_5g40; 185 const uint32_t *vals_2g40; 186 const uint32_t *vals_2g20; 187 int ncmregs; 188 const uint16_t *cmregs; 189 const uint32_t *cmvals; 190 int nfastregs; 191 const uint16_t *fastregs; 192 const uint32_t *fastvals_5g20; 193 const uint32_t *fastvals_5g40; 194 }; 195 196 struct athn_gain { 197 int nregs; 198 const uint16_t *regs; 199 const uint32_t *vals_5g; 200 const uint32_t *vals_2g; 201 }; 202 203 struct athn_addac { 204 int nvals; 205 const uint32_t *vals; 206 }; 207 208 struct athn_serdes { 209 int nvals; 210 const uint32_t *regs; 211 const uint32_t *vals; 212 }; 213 214 /* Rx queue software indexes. */ 215 #define ATHN_QID_LP 0 216 #define ATHN_QID_HP 1 217 218 /* Tx queue software indexes. */ 219 #define ATHN_QID_AC_BE 0 220 #define ATHN_QID_PSPOLL 1 221 #define ATHN_QID_AC_BK 2 222 #define ATHN_QID_AC_VI 3 223 #define ATHN_QID_AC_VO 4 224 #define ATHN_QID_UAPSD 5 225 #define ATHN_QID_CAB 6 226 #define ATHN_QID_BEACON 7 227 #define ATHN_QID_COUNT 8 228 229 /* Map Access Category to Tx queue Id. */ 230 static const uint8_t athn_ac2qid[EDCA_NUM_AC] = { 231 ATHN_QID_AC_BE, /* EDCA_AC_BE */ 232 ATHN_QID_AC_BK, /* EDCA_AC_BK */ 233 ATHN_QID_AC_VI, /* EDCA_AC_VI */ 234 ATHN_QID_AC_VO /* EDCA_AC_VO */ 235 }; 236 237 static const uint8_t athn_5ghz_chans[] = { 238 /* UNII 1. */ 239 36, 40, 44, 48, 240 /* UNII 2. */ 241 52, 56, 60, 64, 242 /* Middle band. */ 243 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 244 /* UNII 3. */ 245 149, 153, 157, 161, 165 246 }; 247 248 /* Number of data bits per OFDM symbol for MCS[0-15]. */ 249 /* See tables 20-29, 20-30, 20-33, 20-34. */ 250 static const uint16_t ar_mcs_ndbps[][2] = { 251 /* 20MHz 40MHz */ 252 { 26, 54 }, /* MCS0 */ 253 { 52, 108 }, /* MCS1 */ 254 { 78, 162 }, /* MCS2 */ 255 { 104, 216 }, /* MCS3 */ 256 { 156, 324 }, /* MCS4 */ 257 { 208, 432 }, /* MCS5 */ 258 { 234, 486 }, /* MCS6 */ 259 { 260, 540 }, /* MCS7 */ 260 { 26, 108 }, /* MCS8 */ 261 { 52, 216 }, /* MCS9 */ 262 { 78, 324 }, /* MCS10 */ 263 { 104, 432 }, /* MCS11 */ 264 { 156, 648 }, /* MCS12 */ 265 { 208, 864 }, /* MCS13 */ 266 { 234, 972 }, /* MCS14 */ 267 { 260, 1080 } /* MCS15 */ 268 }; 269 270 #define ATHN_POWER_OFDM6 0 271 #define ATHN_POWER_OFDM9 1 272 #define ATHN_POWER_OFDM12 2 273 #define ATHN_POWER_OFDM18 3 274 #define ATHN_POWER_OFDM24 4 275 #define ATHN_POWER_OFDM36 5 276 #define ATHN_POWER_OFDM48 6 277 #define ATHN_POWER_OFDM54 7 278 #define ATHN_POWER_CCK1_LP 8 279 #define ATHN_POWER_CCK2_LP 9 280 #define ATHN_POWER_CCK2_SP 10 281 #define ATHN_POWER_CCK55_LP 11 282 #define ATHN_POWER_CCK55_SP 12 283 #define ATHN_POWER_CCK11_LP 13 284 #define ATHN_POWER_CCK11_SP 14 285 #define ATHN_POWER_XR 15 286 #define ATHN_POWER_HT20(mcs) (16 + (mcs)) 287 #define ATHN_POWER_HT40(mcs) (40 + (mcs)) 288 #define ATHN_POWER_CCK_DUP 64 289 #define ATHN_POWER_OFDM_DUP 65 290 #define ATHN_POWER_CCK_EXT 66 291 #define ATHN_POWER_OFDM_EXT 67 292 #define ATHN_POWER_COUNT 68 293 294 #define ATHN_NUM_LEGACY_RATES IEEE80211_RATE_MAXSIZE 295 #define ATHN_NUM_RATES (ATHN_NUM_LEGACY_RATES + ATHN_NUM_MCS) 296 struct athn_node { 297 struct ieee80211_node ni; 298 struct ieee80211_amrr_node amn; 299 struct ieee80211_ra_node rn; 300 uint8_t ridx[ATHN_NUM_RATES]; 301 uint8_t fallback[ATHN_NUM_RATES]; 302 uint8_t sta_index; 303 }; 304 305 /* 306 * Adaptive noise immunity state. 307 */ 308 #define ATHN_ANI_PERIOD 100 309 #define ATHN_ANI_RSSI_THR_HIGH 40 310 #define ATHN_ANI_RSSI_THR_LOW 7 311 struct athn_ani { 312 uint8_t noise_immunity_level; 313 uint8_t spur_immunity_level; 314 uint8_t firstep_level; 315 uint8_t ofdm_weak_signal; 316 uint8_t cck_weak_signal; 317 318 uint32_t listen_time; 319 320 uint32_t ofdm_trig_high; 321 uint32_t ofdm_trig_low; 322 323 int32_t cck_trig_high; 324 int32_t cck_trig_low; 325 326 uint32_t ofdm_phy_err_base; 327 uint32_t cck_phy_err_base; 328 uint32_t ofdm_phy_err_count; 329 uint32_t cck_phy_err_count; 330 331 uint32_t cyccnt; 332 uint32_t txfcnt; 333 uint32_t rxfcnt; 334 }; 335 336 struct athn_iq_cal { 337 uint32_t pwr_meas_i; 338 uint32_t pwr_meas_q; 339 int32_t iq_corr_meas; 340 }; 341 342 struct athn_adc_cal { 343 uint32_t pwr_meas_odd_i; 344 uint32_t pwr_meas_even_i; 345 uint32_t pwr_meas_odd_q; 346 uint32_t pwr_meas_even_q; 347 }; 348 349 struct athn_calib { 350 int nsamples; 351 struct athn_iq_cal iq[AR_MAX_CHAINS]; 352 struct athn_adc_cal adc_gain[AR_MAX_CHAINS]; 353 struct athn_adc_cal adc_dc_offset[AR_MAX_CHAINS]; 354 }; 355 356 #define ATHN_NF_CAL_HIST_MAX 5 357 358 struct athn_softc; 359 360 struct athn_ops { 361 /* Bus callbacks. */ 362 uint32_t (*read)(struct athn_softc *, uint32_t); 363 void (*write)(struct athn_softc *, uint32_t, uint32_t); 364 void (*write_barrier)(struct athn_softc *); 365 366 void (*setup)(struct athn_softc *); 367 void (*set_txpower)(struct athn_softc *, struct ieee80211_channel *, 368 struct ieee80211_channel *); 369 void (*spur_mitigate)(struct athn_softc *, 370 struct ieee80211_channel *, struct ieee80211_channel *); 371 const struct ar_spur_chan * 372 (*get_spur_chans)(struct athn_softc *, int); 373 void (*init_from_rom)(struct athn_softc *, 374 struct ieee80211_channel *, struct ieee80211_channel *); 375 int (*set_synth)(struct athn_softc *, struct ieee80211_channel *, 376 struct ieee80211_channel *); 377 int (*read_rom_data)(struct athn_softc *, uint32_t, void *, int); 378 const uint8_t * 379 (*get_rom_template)(struct athn_softc *, uint8_t); 380 void (*swap_rom)(struct athn_softc *); 381 void (*olpc_init)(struct athn_softc *); 382 void (*olpc_temp_compensation)(struct athn_softc *); 383 /* GPIO callbacks. */ 384 int (*gpio_read)(struct athn_softc *, int); 385 void (*gpio_write)(struct athn_softc *, int, int); 386 void (*gpio_config_input)(struct athn_softc *, int); 387 void (*gpio_config_output)(struct athn_softc *, int, int); 388 void (*rfsilent_init)(struct athn_softc *); 389 /* DMA callbacks. */ 390 int (*dma_alloc)(struct athn_softc *); 391 void (*dma_free)(struct athn_softc *); 392 void (*rx_enable)(struct athn_softc *); 393 int (*intr)(struct athn_softc *); 394 int (*tx)(struct athn_softc *, struct mbuf *, 395 struct ieee80211_node *, int); 396 /* PHY callbacks. */ 397 void (*set_rf_mode)(struct athn_softc *, 398 struct ieee80211_channel *); 399 int (*rf_bus_request)(struct athn_softc *); 400 void (*rf_bus_release)(struct athn_softc *); 401 void (*set_phy)(struct athn_softc *, struct ieee80211_channel *, 402 struct ieee80211_channel *); 403 void (*set_delta_slope)(struct athn_softc *, 404 struct ieee80211_channel *, struct ieee80211_channel *); 405 void (*enable_antenna_diversity)(struct athn_softc *); 406 void (*init_baseband)(struct athn_softc *); 407 void (*disable_phy)(struct athn_softc *); 408 void (*set_rxchains)(struct athn_softc *); 409 void (*noisefloor_calib)(struct athn_softc *); 410 void (*init_noisefloor_calib)(struct athn_softc *); 411 int (*get_noisefloor)(struct athn_softc *); 412 void (*apply_noisefloor)(struct athn_softc *); 413 void (*do_calib)(struct athn_softc *); 414 void (*next_calib)(struct athn_softc *); 415 void (*hw_init)(struct athn_softc *, struct ieee80211_channel *, 416 struct ieee80211_channel *); 417 void (*get_paprd_masks)(struct athn_softc *sc, 418 struct ieee80211_channel *, uint32_t *, uint32_t *); 419 /* ANI callbacks. */ 420 void (*set_noise_immunity_level)(struct athn_softc *, int); 421 void (*enable_ofdm_weak_signal)(struct athn_softc *); 422 void (*disable_ofdm_weak_signal)(struct athn_softc *); 423 void (*set_cck_weak_signal)(struct athn_softc *, int); 424 void (*set_firstep_level)(struct athn_softc *, int); 425 void (*set_spur_immunity_level)(struct athn_softc *, int); 426 }; 427 428 struct athn_softc { 429 struct device sc_dev; 430 struct ieee80211com sc_ic; 431 432 int (*sc_enable)(struct athn_softc *); 433 void (*sc_disable)(struct athn_softc *); 434 void (*sc_power)(struct athn_softc *, int); 435 void (*sc_disable_aspm)(struct athn_softc *); 436 void (*sc_enable_extsynch)( 437 struct athn_softc *); 438 439 int (*sc_newstate)(struct ieee80211com *, 440 enum ieee80211_state, int); 441 442 bus_dma_tag_t sc_dmat; 443 444 struct timeout scan_to; 445 struct timeout calib_to; 446 struct ieee80211_amrr amrr; 447 448 u_int flags; 449 #define ATHN_FLAG_PCIE (1 << 0) 450 #define ATHN_FLAG_USB (1 << 1) 451 #define ATHN_FLAG_OLPC (1 << 2) 452 #define ATHN_FLAG_PAPRD (1 << 3) 453 #define ATHN_FLAG_FAST_PLL_CLOCK (1 << 4) 454 #define ATHN_FLAG_RFSILENT (1 << 5) 455 #define ATHN_FLAG_RFSILENT_REVERSED (1 << 6) 456 #define ATHN_FLAG_BTCOEX2WIRE (1 << 7) 457 #define ATHN_FLAG_BTCOEX3WIRE (1 << 8) 458 /* Shortcut. */ 459 #define ATHN_FLAG_BTCOEX (ATHN_FLAG_BTCOEX2WIRE | ATHN_FLAG_BTCOEX3WIRE) 460 #define ATHN_FLAG_11A (1 << 9) 461 #define ATHN_FLAG_11G (1 << 10) 462 #define ATHN_FLAG_11N (1 << 11) 463 #define ATHN_FLAG_AN_TOP2_FIXUP (1 << 12) 464 #define ATHN_FLAG_NON_ENTERPRISE (1 << 13) 465 #define ATHN_FLAG_3TREDUCE_CHAIN (1 << 14) 466 467 uint8_t ngpiopins; 468 int led_pin; 469 int rfsilent_pin; 470 int led_state; 471 uint32_t isync; 472 uint32_t imask; 473 474 uint16_t mac_ver; 475 uint8_t mac_rev; 476 uint8_t rf_rev; 477 uint16_t eep_rev; 478 479 uint8_t txchainmask; 480 uint8_t rxchainmask; 481 uint8_t ntxchains; 482 uint8_t nrxchains; 483 484 uint8_t sup_calib_mask; 485 uint8_t cur_calib_mask; 486 #define ATHN_CAL_IQ (1 << 0) 487 #define ATHN_CAL_ADC_GAIN (1 << 1) 488 #define ATHN_CAL_ADC_DC (1 << 2) 489 #define ATHN_CAL_TEMP (1 << 3) 490 491 struct ieee80211_channel *curchan; 492 struct ieee80211_channel *curchanext; 493 494 /* Open Loop Power Control. */ 495 int8_t tx_gain_tbl[AR9280_TX_GAIN_TABLE_SIZE]; 496 int8_t pdadc; 497 int8_t tcomp; 498 int olpc_ticks; 499 int iqcal_ticks; 500 501 /* PA predistortion. */ 502 uint16_t gain1[AR_MAX_CHAINS]; 503 uint32_t txgain[AR9003_TX_GAIN_TABLE_SIZE]; 504 int16_t pa_in[AR_MAX_CHAINS] 505 [AR9003_PAPRD_MEM_TAB_SIZE]; 506 int16_t angle[AR_MAX_CHAINS] 507 [AR9003_PAPRD_MEM_TAB_SIZE]; 508 int32_t trainpow; 509 uint8_t paprd_curchain; 510 511 uint32_t rwbuf[64]; 512 513 int kc_entries; 514 515 void *eep; 516 const void *eep_def; 517 uint32_t eep_base; 518 uint32_t eep_size; 519 520 struct athn_rxq rxq[2]; 521 struct athn_txq txq[31]; 522 523 void *descs; 524 bus_dmamap_t map; 525 bus_dma_segment_t seg; 526 SIMPLEQ_HEAD(, athn_tx_buf) txbufs; 527 struct athn_tx_buf *bcnbuf; 528 struct athn_tx_buf txpool[ATHN_NTXBUFS]; 529 530 bus_dmamap_t txsmap; 531 bus_dma_segment_t txsseg; 532 void *txsring; 533 int txscur; 534 535 int sc_if_flags; 536 int sc_tx_timer; 537 538 const struct athn_ini *ini; 539 const struct athn_gain *rx_gain; 540 const struct athn_gain *tx_gain; 541 const struct athn_addac *addac; 542 const struct athn_serdes *serdes; 543 uint32_t workaround; 544 uint32_t obs_off; 545 uint32_t gpio_input_en_off; 546 547 struct athn_ops ops; 548 549 int fixed_ridx; 550 551 int16_t cca_min_2g; 552 int16_t cca_max_2g; 553 int16_t cca_min_5g; 554 int16_t cca_max_5g; 555 struct { 556 int16_t nf[AR_MAX_CHAINS]; 557 int16_t nf_ext[AR_MAX_CHAINS]; 558 } nf_hist[ATHN_NF_CAL_HIST_MAX]; 559 int nf_hist_cur; 560 int nf_hist_nvalid; 561 int16_t nf_priv[AR_MAX_CHAINS]; 562 int16_t nf_ext_priv[AR_MAX_CHAINS]; 563 int nf_calib_pending; 564 int nf_calib_ticks; 565 int pa_calib_ticks; 566 567 struct athn_calib calib; 568 struct athn_ani ani; 569 570 #if NBPFILTER > 0 571 caddr_t sc_drvbpf; 572 573 union { 574 struct athn_rx_radiotap_header th; 575 uint8_t pad[IEEE80211_RADIOTAP_HDRLEN]; 576 } sc_rxtapu; 577 #define sc_rxtap sc_rxtapu.th 578 int sc_rxtap_len; 579 580 union { 581 struct athn_tx_radiotap_header th; 582 uint8_t pad[IEEE80211_RADIOTAP_HDRLEN]; 583 } sc_txtapu; 584 #define sc_txtap sc_txtapu.th 585 int sc_txtap_len; 586 #endif 587 }; 588 589 extern int athn_attach(struct athn_softc *); 590 extern void athn_detach(struct athn_softc *); 591 extern void athn_suspend(struct athn_softc *); 592 extern void athn_wakeup(struct athn_softc *); 593 extern int athn_intr(void *); 594