1 /* $NetBSD: pciide_common.c,v 1.61 2016/07/07 06:55:41 msaitoh Exp $ */
2
3
4 /*
5 * Copyright (c) 1999, 2000, 2001, 2003 Manuel Bouyer.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 *
27 */
28
29
30 /*
31 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved.
32 *
33 * Redistribution and use in source and binary forms, with or without
34 * modification, are permitted provided that the following conditions
35 * are met:
36 * 1. Redistributions of source code must retain the above copyright
37 * notice, this list of conditions and the following disclaimer.
38 * 2. Redistributions in binary form must reproduce the above copyright
39 * notice, this list of conditions and the following disclaimer in the
40 * documentation and/or other materials provided with the distribution.
41 * 3. All advertising materials mentioning features or use of this software
42 * must display the following acknowledgement:
43 * This product includes software developed by Christopher G. Demetriou
44 * for the NetBSD Project.
45 * 4. The name of the author may not be used to endorse or promote products
46 * derived from this software without specific prior written permission
47 *
48 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
49 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
50 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
51 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
52 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
53 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
54 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
55 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
56 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
57 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
58 */
59
60 /*
61 * PCI IDE controller driver.
62 *
63 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD
64 * sys/dev/pci/ppb.c, revision 1.16).
65 *
66 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and
67 * "Programming Interface for Bus Master IDE Controller, Revision 1.0
68 * 5/16/94" from the PCI SIG.
69 *
70 */
71
72 #include <sys/cdefs.h>
73 __KERNEL_RCSID(0, "$NetBSD: pciide_common.c,v 1.61 2016/07/07 06:55:41 msaitoh Exp $");
74
75 #include <sys/param.h>
76 #include <sys/malloc.h>
77
78 #include <dev/pci/pcireg.h>
79 #include <dev/pci/pcivar.h>
80 #include <dev/pci/pcidevs.h>
81 #include <dev/pci/pciidereg.h>
82 #include <dev/pci/pciidevar.h>
83
84 #include <dev/ic/wdcreg.h>
85
86 #ifdef ATADEBUG
87 int atadebug_pciide_mask = 0;
88 #endif
89
90 #if NATA_DMA
91 static const char dmaerrfmt[] =
92 "%s:%d: unable to %s table DMA map for drive %d, error=%d\n";
93 #endif
94
95 /* Default product description for devices not known from this controller */
96 const struct pciide_product_desc default_product_desc = {
97 0,
98 0,
99 "Generic PCI IDE controller",
100 default_chip_map,
101 };
102
103 const struct pciide_product_desc *
pciide_lookup_product(pcireg_t id,const struct pciide_product_desc * pp)104 pciide_lookup_product(pcireg_t id, const struct pciide_product_desc *pp)
105 {
106 for (; pp->chip_map != NULL; pp++)
107 if (PCI_PRODUCT(id) == pp->ide_product)
108 break;
109
110 if (pp->chip_map == NULL)
111 return NULL;
112 return pp;
113 }
114
115 void
pciide_common_attach(struct pciide_softc * sc,const struct pci_attach_args * pa,const struct pciide_product_desc * pp)116 pciide_common_attach(struct pciide_softc *sc, const struct pci_attach_args *pa,
117 const struct pciide_product_desc *pp)
118 {
119 pci_chipset_tag_t pc = pa->pa_pc;
120 pcitag_t tag = pa->pa_tag;
121 #if NATA_DMA
122 pcireg_t csr;
123 #endif
124 const char *displaydev = NULL;
125 int dontprint = 0;
126
127 sc->sc_pci_id = pa->pa_id;
128 if (pp == NULL) {
129 /* should only happen for generic pciide devices */
130 sc->sc_pp = &default_product_desc;
131 } else {
132 sc->sc_pp = pp;
133 /* if ide_name == NULL, printf is done in chip-specific map */
134 if (pp->ide_name)
135 displaydev = pp->ide_name;
136 else
137 dontprint = 1;
138 }
139
140 if (dontprint) {
141 aprint_naive("disk controller\n");
142 aprint_normal("\n"); /* ??? */
143 } else
144 pci_aprint_devinfo_fancy(pa, "disk controller", displaydev, 1);
145
146 sc->sc_pc = pa->pa_pc;
147 sc->sc_tag = pa->pa_tag;
148
149 #if NATA_DMA
150 /* Set up DMA defaults; these might be adjusted by chip_map. */
151 sc->sc_dma_maxsegsz = IDEDMA_BYTE_COUNT_MAX;
152 sc->sc_dma_boundary = IDEDMA_BYTE_COUNT_ALIGN;
153 #endif
154
155 #ifdef ATADEBUG
156 if (atadebug_pciide_mask & DEBUG_PROBE)
157 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL);
158 #endif
159 sc->sc_pp->chip_map(sc, pa);
160
161 #if NATA_DMA
162 if (sc->sc_dma_ok) {
163 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
164 csr |= PCI_COMMAND_MASTER_ENABLE;
165 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr);
166 }
167 #endif
168 ATADEBUG_PRINT(("pciide: command/status register=%x\n",
169 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE);
170 }
171
172 int
pciide_common_detach(struct pciide_softc * sc,int flags)173 pciide_common_detach(struct pciide_softc *sc, int flags)
174 {
175 struct pciide_channel *cp;
176 struct ata_channel *wdc_cp;
177 struct wdc_regs *wdr;
178 int channel, drive;
179 int rv;
180
181 rv = wdcdetach(sc->sc_wdcdev.sc_atac.atac_dev, flags);
182 if (rv)
183 return rv;
184
185 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
186 channel++) {
187 cp = &sc->pciide_channels[channel];
188 wdc_cp = &cp->ata_channel;
189 wdr = CHAN_TO_WDC_REGS(wdc_cp);
190
191 if (wdc_cp->ch_flags & ATACH_DISABLED)
192 continue;
193
194 if (wdr->cmd_ios != 0)
195 bus_space_unmap(wdr->cmd_iot,
196 wdr->cmd_baseioh, wdr->cmd_ios);
197 if (cp->compat != 0) {
198 if (wdr->ctl_ios != 0)
199 bus_space_unmap(wdr->ctl_iot,
200 wdr->ctl_ioh, wdr->ctl_ios);
201 } else {
202 if (cp->ctl_ios != 0)
203 bus_space_unmap(wdr->ctl_iot,
204 cp->ctl_baseioh, cp->ctl_ios);
205 }
206
207 for (drive = 0; drive < sc->sc_wdcdev.wdc_maxdrives; drive++) {
208 #if NATA_DMA
209 pciide_dma_table_teardown(sc, channel, drive);
210 #endif
211 }
212
213 free(cp->ata_channel.ch_queue, M_DEVBUF);
214 cp->ata_channel.atabus = NULL;
215 }
216
217 #if NATA_DMA
218 if (sc->sc_dma_ios != 0)
219 bus_space_unmap(sc->sc_dma_iot, sc->sc_dma_ioh, sc->sc_dma_ios);
220 if (sc->sc_ba5_ss != 0)
221 bus_space_unmap(sc->sc_ba5_st, sc->sc_ba5_sh, sc->sc_ba5_ss);
222 #endif
223
224 return 0;
225 }
226
227 int
pciide_detach(device_t self,int flags)228 pciide_detach(device_t self, int flags)
229 {
230 struct pciide_softc *sc = device_private(self);
231 struct pciide_channel *cp;
232 int channel;
233 #ifndef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_DISESTABLISH
234 bool has_compat_chan;
235
236 has_compat_chan = false;
237 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
238 channel++) {
239 cp = &sc->pciide_channels[channel];
240 if (cp->compat != 0) {
241 has_compat_chan = true;
242 }
243 }
244
245 if (has_compat_chan != false)
246 return EBUSY;
247 #endif
248
249 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
250 channel++) {
251 cp = &sc->pciide_channels[channel];
252 if (cp->compat != 0)
253 if (cp->ih != NULL) {
254 pciide_unmap_compat_intr(sc->sc_pc, cp, channel);
255 cp->ih = NULL;
256 }
257 }
258
259 if (sc->sc_pci_ih != NULL) {
260 pci_intr_disestablish(sc->sc_pc, sc->sc_pci_ih);
261 sc->sc_pci_ih = NULL;
262 }
263
264 return pciide_common_detach(sc, flags);
265 }
266
267 /* tell whether the chip is enabled or not */
268 int
pciide_chipen(struct pciide_softc * sc,const struct pci_attach_args * pa)269 pciide_chipen(struct pciide_softc *sc, const struct pci_attach_args *pa)
270 {
271 pcireg_t csr;
272
273 if ((pa->pa_flags & PCI_FLAGS_IO_OKAY) == 0) {
274 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
275 "I/O access disabled at bridge\n");
276 return 0;
277 }
278 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG);
279 if ((csr & PCI_COMMAND_IO_ENABLE) == 0) {
280 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
281 "I/O access disabled at device\n");
282 return 0;
283 }
284 return 1;
285 }
286
287 void
pciide_mapregs_compat(const struct pci_attach_args * pa,struct pciide_channel * cp,int compatchan)288 pciide_mapregs_compat(const struct pci_attach_args *pa,
289 struct pciide_channel *cp, int compatchan)
290 {
291 struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel);
292 struct ata_channel *wdc_cp = &cp->ata_channel;
293 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(wdc_cp);
294 int i;
295
296 cp->compat = 1;
297
298 wdr->cmd_iot = pa->pa_iot;
299 if (bus_space_map(wdr->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan),
300 PCIIDE_COMPAT_CMD_SIZE, 0, &wdr->cmd_baseioh) != 0) {
301 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
302 "couldn't map %s channel cmd regs\n", cp->name);
303 goto bad;
304 }
305 wdr->cmd_ios = PCIIDE_COMPAT_CMD_SIZE;
306
307 wdr->ctl_iot = pa->pa_iot;
308 if (bus_space_map(wdr->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan),
309 PCIIDE_COMPAT_CTL_SIZE, 0, &wdr->ctl_ioh) != 0) {
310 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
311 "couldn't map %s channel ctl regs\n", cp->name);
312 bus_space_unmap(wdr->cmd_iot, wdr->cmd_baseioh, wdr->cmd_ios);
313 goto bad;
314 }
315 wdr->ctl_ios = PCIIDE_COMPAT_CTL_SIZE;
316
317 for (i = 0; i < WDC_NREG; i++) {
318 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, i,
319 i == 0 ? 4 : 1, &wdr->cmd_iohs[i]) != 0) {
320 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
321 "couldn't subregion %s channel cmd regs\n",
322 cp->name);
323 goto bad;
324 }
325 }
326 wdc_init_shadow_regs(wdc_cp);
327 wdr->data32iot = wdr->cmd_iot;
328 wdr->data32ioh = wdr->cmd_iohs[0];
329 return;
330
331 bad:
332 cp->ata_channel.ch_flags |= ATACH_DISABLED;
333 return;
334 }
335
336 void
pciide_mapregs_native(const struct pci_attach_args * pa,struct pciide_channel * cp,int (* pci_intr)(void *))337 pciide_mapregs_native(const struct pci_attach_args *pa,
338 struct pciide_channel *cp, int (*pci_intr)(void *))
339 {
340 struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel);
341 struct ata_channel *wdc_cp = &cp->ata_channel;
342 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(wdc_cp);
343 const char *intrstr;
344 pci_intr_handle_t intrhandle;
345 int i;
346 char intrbuf[PCI_INTRSTR_LEN];
347
348 cp->compat = 0;
349
350 if (sc->sc_pci_ih == NULL) {
351 if (pci_intr_map(pa, &intrhandle) != 0) {
352 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
353 "couldn't map native-PCI interrupt\n");
354 goto bad;
355 }
356 intrstr = pci_intr_string(pa->pa_pc, intrhandle, intrbuf, sizeof(intrbuf));
357 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc,
358 intrhandle, IPL_BIO, pci_intr, sc);
359 if (sc->sc_pci_ih != NULL) {
360 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
361 "using %s for native-PCI interrupt\n",
362 intrstr ? intrstr : "unknown interrupt");
363 } else {
364 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
365 "couldn't establish native-PCI interrupt");
366 if (intrstr != NULL)
367 aprint_error(" at %s", intrstr);
368 aprint_error("\n");
369 goto bad;
370 }
371 }
372 cp->ih = sc->sc_pci_ih;
373 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->ch_channel),
374 PCI_MAPREG_TYPE_IO, 0,
375 &wdr->cmd_iot, &wdr->cmd_baseioh, NULL, &wdr->cmd_ios) != 0) {
376 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
377 "couldn't map %s channel cmd regs\n", cp->name);
378 goto bad;
379 }
380
381 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->ch_channel),
382 PCI_MAPREG_TYPE_IO, 0,
383 &wdr->ctl_iot, &cp->ctl_baseioh, NULL, &cp->ctl_ios) != 0) {
384 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
385 "couldn't map %s channel ctl regs\n", cp->name);
386 bus_space_unmap(wdr->cmd_iot, wdr->cmd_baseioh, wdr->cmd_ios);
387 goto bad;
388 }
389 /*
390 * In native mode, 4 bytes of I/O space are mapped for the control
391 * register, the control register is at offset 2. Pass the generic
392 * code a handle for only one byte at the right offset.
393 */
394 if (bus_space_subregion(wdr->ctl_iot, cp->ctl_baseioh, 2, 1,
395 &wdr->ctl_ioh) != 0) {
396 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
397 "unable to subregion %s channel ctl regs\n", cp->name);
398 bus_space_unmap(wdr->cmd_iot, wdr->cmd_baseioh, wdr->cmd_ios);
399 bus_space_unmap(wdr->cmd_iot, cp->ctl_baseioh, cp->ctl_ios);
400 goto bad;
401 }
402
403 for (i = 0; i < WDC_NREG; i++) {
404 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, i,
405 i == 0 ? 4 : 1, &wdr->cmd_iohs[i]) != 0) {
406 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
407 "couldn't subregion %s channel cmd regs\n",
408 cp->name);
409 goto bad;
410 }
411 }
412 wdc_init_shadow_regs(wdc_cp);
413 wdr->data32iot = wdr->cmd_iot;
414 wdr->data32ioh = wdr->cmd_iohs[0];
415 return;
416
417 bad:
418 cp->ata_channel.ch_flags |= ATACH_DISABLED;
419 return;
420 }
421
422 #if NATA_DMA
423 void
pciide_mapreg_dma(struct pciide_softc * sc,const struct pci_attach_args * pa)424 pciide_mapreg_dma(struct pciide_softc *sc, const struct pci_attach_args *pa)
425 {
426 pcireg_t maptype;
427 bus_addr_t addr;
428 struct pciide_channel *pc;
429 int reg, chan;
430 bus_size_t size;
431
432 /*
433 * Map DMA registers
434 *
435 * Note that sc_dma_ok is the right variable to test to see if
436 * DMA can be done. If the interface doesn't support DMA,
437 * sc_dma_ok will never be non-zero. If the DMA regs couldn't
438 * be mapped, it'll be zero. I.e., sc_dma_ok will only be
439 * non-zero if the interface supports DMA and the registers
440 * could be mapped.
441 *
442 * XXX Note that despite the fact that the Bus Master IDE specs
443 * XXX say that "The bus master IDE function uses 16 bytes of IO
444 * XXX space," some controllers (at least the United
445 * XXX Microelectronics UM8886BF) place it in memory space.
446 */
447 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag,
448 PCIIDE_REG_BUS_MASTER_DMA);
449
450 switch (maptype) {
451 case PCI_MAPREG_TYPE_IO:
452 sc->sc_dma_ok = (pci_mapreg_info(pa->pa_pc, pa->pa_tag,
453 PCIIDE_REG_BUS_MASTER_DMA, PCI_MAPREG_TYPE_IO,
454 &addr, NULL, NULL) == 0);
455 if (sc->sc_dma_ok == 0) {
456 aprint_verbose(
457 ", but unused (couldn't query registers)");
458 break;
459 }
460 if ((sc->sc_pp->ide_flags & IDE_16BIT_IOSPACE)
461 && addr >= 0x10000) {
462 sc->sc_dma_ok = 0;
463 aprint_verbose(
464 ", but unused (registers at unsafe address "
465 "%#lx)", (unsigned long)addr);
466 break;
467 }
468 /* FALLTHROUGH */
469
470 case PCI_MAPREG_MEM_TYPE_32BIT:
471 sc->sc_dma_ok = (pci_mapreg_map(pa,
472 PCIIDE_REG_BUS_MASTER_DMA, maptype, 0,
473 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, &sc->sc_dma_ios)
474 == 0);
475 sc->sc_dmat = pa->pa_dmat;
476 if (sc->sc_dma_ok == 0) {
477 aprint_verbose(", but unused (couldn't map registers)");
478 } else {
479 sc->sc_wdcdev.dma_arg = sc;
480 sc->sc_wdcdev.dma_init = pciide_dma_init;
481 sc->sc_wdcdev.dma_start = pciide_dma_start;
482 sc->sc_wdcdev.dma_finish = pciide_dma_finish;
483 }
484
485 if (device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags &
486 PCIIDE_OPTIONS_NODMA) {
487 aprint_verbose(
488 ", but unused (forced off by config file)");
489 sc->sc_dma_ok = 0;
490 }
491 break;
492
493 default:
494 sc->sc_dma_ok = 0;
495 aprint_verbose(
496 ", but unsupported register maptype (0x%x)", maptype);
497 }
498
499 if (sc->sc_dma_ok == 0)
500 return;
501
502 /*
503 * Set up the default handles for the DMA registers.
504 * Just reserve 32 bits for each handle, unless space
505 * doesn't permit it.
506 */
507 for (chan = 0; chan < PCIIDE_NUM_CHANNELS; chan++) {
508 pc = &sc->pciide_channels[chan];
509 for (reg = 0; reg < IDEDMA_NREGS; reg++) {
510 size = 4;
511 if (size > (IDEDMA_SCH_OFFSET - reg))
512 size = IDEDMA_SCH_OFFSET - reg;
513 if (bus_space_subregion(sc->sc_dma_iot, sc->sc_dma_ioh,
514 IDEDMA_SCH_OFFSET * chan + reg, size,
515 &pc->dma_iohs[reg]) != 0) {
516 sc->sc_dma_ok = 0;
517 aprint_verbose(", but can't subregion offset %d "
518 "size %lu", reg, (u_long)size);
519 return;
520 }
521 }
522 }
523 }
524 #endif /* NATA_DMA */
525
526 int
pciide_compat_intr(void * arg)527 pciide_compat_intr(void *arg)
528 {
529 struct pciide_channel *cp = arg;
530
531 #ifdef DIAGNOSTIC
532 /* should only be called for a compat channel */
533 if (cp->compat == 0)
534 panic("pciide compat intr called for non-compat chan %p", cp);
535 #endif
536 return (wdcintr(&cp->ata_channel));
537 }
538
539 int
pciide_pci_intr(void * arg)540 pciide_pci_intr(void *arg)
541 {
542 struct pciide_softc *sc = arg;
543 struct pciide_channel *cp;
544 struct ata_channel *wdc_cp;
545 int i, rv, crv;
546
547 rv = 0;
548 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) {
549 cp = &sc->pciide_channels[i];
550 wdc_cp = &cp->ata_channel;
551
552 /* If a compat channel skip. */
553 if (cp->compat)
554 continue;
555 /* if this channel not waiting for intr, skip */
556 if ((wdc_cp->ch_flags & ATACH_IRQ_WAIT) == 0)
557 continue;
558
559 crv = wdcintr(wdc_cp);
560 if (crv == 0)
561 ; /* leave rv alone */
562 else if (crv == 1)
563 rv = 1; /* claim the intr */
564 else if (rv == 0) /* crv should be -1 in this case */
565 rv = crv; /* if we've done no better, take it */
566 }
567 return (rv);
568 }
569
570 #if NATA_DMA
571 void
pciide_channel_dma_setup(struct pciide_channel * cp)572 pciide_channel_dma_setup(struct pciide_channel *cp)
573 {
574 int drive, s;
575 struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel);
576 struct ata_drive_datas *drvp;
577
578 KASSERT(cp->ata_channel.ch_ndrives != 0);
579
580 for (drive = 0; drive < cp->ata_channel.ch_ndrives; drive++) {
581 drvp = &cp->ata_channel.ch_drive[drive];
582 /* If no drive, skip */
583 if (drvp->drive_type == ATA_DRIVET_NONE)
584 continue;
585 /* setup DMA if needed */
586 if (((drvp->drive_flags & ATA_DRIVE_DMA) == 0 &&
587 (drvp->drive_flags & ATA_DRIVE_UDMA) == 0) ||
588 sc->sc_dma_ok == 0) {
589 s = splbio();
590 drvp->drive_flags &= ~(ATA_DRIVE_DMA | ATA_DRIVE_UDMA);
591 splx(s);
592 continue;
593 }
594 if (pciide_dma_table_setup(sc, cp->ata_channel.ch_channel,
595 drive) != 0) {
596 /* Abort DMA setup */
597 s = splbio();
598 drvp->drive_flags &= ~(ATA_DRIVE_DMA | ATA_DRIVE_UDMA);
599 splx(s);
600 continue;
601 }
602 }
603 }
604
605 #define NIDEDMA_TABLES(sc) \
606 (MAXPHYS/(min((sc)->sc_dma_maxsegsz, PAGE_SIZE)) + 1)
607
608 int
pciide_dma_table_setup(struct pciide_softc * sc,int channel,int drive)609 pciide_dma_table_setup(struct pciide_softc *sc, int channel, int drive)
610 {
611 int error;
612 const bus_size_t dma_table_size =
613 sizeof(struct idedma_table) * NIDEDMA_TABLES(sc);
614 struct pciide_dma_maps *dma_maps =
615 &sc->pciide_channels[channel].dma_maps[drive];
616
617 /* If table was already allocated, just return */
618 if (dma_maps->dma_table)
619 return 0;
620
621 /* Allocate memory for the DMA tables and map it */
622 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size,
623 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &dma_maps->dmamap_table_seg,
624 1, &dma_maps->dmamap_table_nseg, BUS_DMA_NOWAIT)) != 0) {
625 aprint_error(dmaerrfmt,
626 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel,
627 "allocate", drive, error);
628 return error;
629 }
630 if ((error = bus_dmamem_map(sc->sc_dmat, &dma_maps->dmamap_table_seg,
631 dma_maps->dmamap_table_nseg, dma_table_size,
632 (void **)&dma_maps->dma_table,
633 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) {
634 aprint_error(dmaerrfmt,
635 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel,
636 "map", drive, error);
637 return error;
638 }
639 ATADEBUG_PRINT(("pciide_dma_table_setup: table at %p len %lu, "
640 "phy 0x%lx\n", dma_maps->dma_table, (u_long)dma_table_size,
641 (unsigned long)dma_maps->dmamap_table_seg.ds_addr), DEBUG_PROBE);
642 /* Create and load table DMA map for this disk */
643 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size,
644 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT,
645 &dma_maps->dmamap_table)) != 0) {
646 aprint_error(dmaerrfmt,
647 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel,
648 "create", drive, error);
649 return error;
650 }
651 if ((error = bus_dmamap_load(sc->sc_dmat,
652 dma_maps->dmamap_table,
653 dma_maps->dma_table,
654 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) {
655 aprint_error(dmaerrfmt,
656 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel,
657 "load", drive, error);
658 return error;
659 }
660 ATADEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n",
661 (unsigned long)dma_maps->dmamap_table->dm_segs[0].ds_addr),
662 DEBUG_PROBE);
663 /* Create a xfer DMA map for this drive */
664 if ((error = bus_dmamap_create(sc->sc_dmat, MAXPHYS,
665 NIDEDMA_TABLES(sc), sc->sc_dma_maxsegsz, sc->sc_dma_boundary,
666 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW,
667 &dma_maps->dmamap_xfer)) != 0) {
668 aprint_error(dmaerrfmt,
669 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel,
670 "create xfer", drive, error);
671 return error;
672 }
673 return 0;
674 }
675
676 void
pciide_dma_table_teardown(struct pciide_softc * sc,int channel,int drive)677 pciide_dma_table_teardown(struct pciide_softc *sc, int channel, int drive)
678 {
679 struct pciide_channel *cp;
680 struct pciide_dma_maps *dma_maps;
681
682 cp = &sc->pciide_channels[channel];
683 dma_maps = &cp->dma_maps[drive];
684
685 if (dma_maps->dma_table == NULL)
686 return;
687
688 bus_dmamap_destroy(sc->sc_dmat, dma_maps->dmamap_xfer);
689 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_table);
690 bus_dmamap_destroy(sc->sc_dmat, dma_maps->dmamap_table);
691 bus_dmamem_unmap(sc->sc_dmat, dma_maps->dma_table,
692 sizeof(struct idedma_table) * NIDEDMA_TABLES(sc));
693 bus_dmamem_free(sc->sc_dmat, &dma_maps->dmamap_table_seg,
694 dma_maps->dmamap_table_nseg);
695
696 dma_maps->dma_table = NULL;
697
698 return;
699 }
700
701 int
pciide_dma_dmamap_setup(struct pciide_softc * sc,int channel,int drive,void * databuf,size_t datalen,int flags)702 pciide_dma_dmamap_setup(struct pciide_softc *sc, int channel, int drive,
703 void *databuf, size_t datalen, int flags)
704 {
705 int error, seg;
706 struct pciide_channel *cp = &sc->pciide_channels[channel];
707 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive];
708
709 error = bus_dmamap_load(sc->sc_dmat,
710 dma_maps->dmamap_xfer,
711 databuf, datalen, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING |
712 ((flags & WDC_DMA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE));
713 if (error) {
714 aprint_error(dmaerrfmt,
715 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel,
716 "load xfer", drive, error);
717 return error;
718 }
719
720 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0,
721 dma_maps->dmamap_xfer->dm_mapsize,
722 (flags & WDC_DMA_READ) ?
723 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
724
725 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) {
726 #ifdef DIAGNOSTIC
727 /* A segment must not cross a 64k boundary */
728 {
729 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr;
730 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len;
731 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) !=
732 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) {
733 printf("pciide_dma: segment %d physical addr 0x%lx"
734 " len 0x%lx not properly aligned\n",
735 seg, phys, len);
736 panic("pciide_dma: buf align");
737 }
738 }
739 #endif
740 dma_maps->dma_table[seg].base_addr =
741 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr);
742 dma_maps->dma_table[seg].byte_count =
743 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len &
744 IDEDMA_BYTE_COUNT_MASK);
745 ATADEBUG_PRINT(("\t seg %d len %d addr 0x%x\n",
746 seg, le32toh(dma_maps->dma_table[seg].byte_count),
747 le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA);
748
749 }
750 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |=
751 htole32(IDEDMA_BYTE_COUNT_EOT);
752
753 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0,
754 dma_maps->dmamap_table->dm_mapsize,
755 BUS_DMASYNC_PREWRITE);
756
757 #ifdef DIAGNOSTIC
758 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) {
759 printf("pciide_dma_dmamap_setup: addr 0x%lx "
760 "not properly aligned\n",
761 (u_long)dma_maps->dmamap_table->dm_segs[0].ds_addr);
762 panic("pciide_dma_init: table align");
763 }
764 #endif
765 /* remember flags */
766 dma_maps->dma_flags = flags;
767
768 return 0;
769 }
770
771 int
pciide_dma_init(void * v,int channel,int drive,void * databuf,size_t datalen,int flags)772 pciide_dma_init(void *v, int channel, int drive, void *databuf, size_t datalen,
773 int flags)
774 {
775 struct pciide_softc *sc = v;
776 int error;
777 struct pciide_channel *cp = &sc->pciide_channels[channel];
778 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive];
779
780 if ((error = pciide_dma_dmamap_setup(sc, channel, drive,
781 databuf, datalen, flags)) != 0)
782 return error;
783 /* Maps are ready. Start DMA function */
784 /* Clear status bits */
785 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0,
786 bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0));
787 /* Write table addr */
788 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_TBL], 0,
789 dma_maps->dmamap_table->dm_segs[0].ds_addr);
790 /* set read/write */
791 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0,
792 ((flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE : 0) | cp->idedma_cmd);
793 return 0;
794 }
795
796 void
pciide_dma_start(void * v,int channel,int drive)797 pciide_dma_start(void *v, int channel, int drive)
798 {
799 struct pciide_softc *sc = v;
800 struct pciide_channel *cp = &sc->pciide_channels[channel];
801
802 ATADEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS);
803 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0,
804 bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0)
805 | IDEDMA_CMD_START);
806 }
807
808 int
pciide_dma_finish(void * v,int channel,int drive,int force)809 pciide_dma_finish(void *v, int channel, int drive, int force)
810 {
811 struct pciide_softc *sc = v;
812 u_int8_t status;
813 int error = 0;
814 struct pciide_channel *cp = &sc->pciide_channels[channel];
815 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive];
816
817 status = bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0);
818 ATADEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status),
819 DEBUG_XFERS);
820
821 if (force == WDC_DMAEND_END && (status & IDEDMA_CTL_INTR) == 0)
822 return WDC_DMAST_NOIRQ;
823
824 /* stop DMA channel */
825 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0,
826 bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0)
827 & ~IDEDMA_CMD_START);
828
829 /* Unload the map of the data buffer */
830 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0,
831 dma_maps->dmamap_xfer->dm_mapsize,
832 (dma_maps->dma_flags & WDC_DMA_READ) ?
833 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
834 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer);
835
836 if ((status & IDEDMA_CTL_ERR) != 0 && force != WDC_DMAEND_ABRT_QUIET) {
837 aprint_error("%s:%d:%d: bus-master DMA error: status=0x%x\n",
838 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel,
839 drive, status);
840 error |= WDC_DMAST_ERR;
841 }
842
843 if ((status & IDEDMA_CTL_INTR) == 0 && force != WDC_DMAEND_ABRT_QUIET) {
844 aprint_error("%s:%d:%d: bus-master DMA error: missing "
845 "interrupt, status=0x%x\n",
846 device_xname(sc->sc_wdcdev.sc_atac.atac_dev),
847 channel, drive, status);
848 error |= WDC_DMAST_NOIRQ;
849 }
850
851 if ((status & IDEDMA_CTL_ACT) != 0 && force != WDC_DMAEND_ABRT_QUIET) {
852 /* data underrun, may be a valid condition for ATAPI */
853 error |= WDC_DMAST_UNDER;
854 }
855 return error;
856 }
857
858 void
pciide_irqack(struct ata_channel * chp)859 pciide_irqack(struct ata_channel *chp)
860 {
861 struct pciide_channel *cp = CHAN_TO_PCHAN(chp);
862 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
863
864 /* clear status bits in IDE DMA registers */
865 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0,
866 bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0));
867 }
868 #endif /* NATA_DMA */
869
870 /* some common code used by several chip_map */
871 int
pciide_chansetup(struct pciide_softc * sc,int channel,pcireg_t interface)872 pciide_chansetup(struct pciide_softc *sc, int channel, pcireg_t interface)
873 {
874 struct pciide_channel *cp = &sc->pciide_channels[channel];
875 sc->wdc_chanarray[channel] = &cp->ata_channel;
876 cp->name = PCIIDE_CHANNEL_NAME(channel);
877 cp->ata_channel.ch_channel = channel;
878 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac;
879 cp->ata_channel.ch_queue =
880 malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT|M_ZERO);
881 if (cp->ata_channel.ch_queue == NULL) {
882 aprint_error("%s %s channel: "
883 "can't allocate memory for command queue",
884 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), cp->name);
885 return 0;
886 }
887 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
888 "%s channel %s to %s mode\n", cp->name,
889 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ?
890 "configured" : "wired",
891 (interface & PCIIDE_INTERFACE_PCI(channel)) ?
892 "native-PCI" : "compatibility");
893 return 1;
894 }
895
896 /* some common code used by several chip channel_map */
897 void
pciide_mapchan(const struct pci_attach_args * pa,struct pciide_channel * cp,pcireg_t interface,int (* pci_intr)(void *))898 pciide_mapchan(const struct pci_attach_args *pa, struct pciide_channel *cp,
899 pcireg_t interface, int (*pci_intr)(void *))
900 {
901 struct ata_channel *wdc_cp = &cp->ata_channel;
902
903 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->ch_channel))
904 pciide_mapregs_native(pa, cp, pci_intr);
905 else {
906 pciide_mapregs_compat(pa, cp, wdc_cp->ch_channel);
907 if ((cp->ata_channel.ch_flags & ATACH_DISABLED) == 0)
908 pciide_map_compat_intr(pa, cp, wdc_cp->ch_channel);
909 }
910 wdcattach(wdc_cp);
911 }
912
913 /*
914 * generic code to map the compat intr.
915 */
916 void
pciide_map_compat_intr(const struct pci_attach_args * pa,struct pciide_channel * cp,int compatchan)917 pciide_map_compat_intr(const struct pci_attach_args *pa,
918 struct pciide_channel *cp, int compatchan)
919 {
920 struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel);
921
922 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH
923 cp->ih =
924 pciide_machdep_compat_intr_establish(sc->sc_wdcdev.sc_atac.atac_dev,
925 pa, compatchan, pciide_compat_intr, cp);
926 if (cp->ih == NULL) {
927 #endif
928 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
929 "no compatibility interrupt for use by %s "
930 "channel\n", cp->name);
931 cp->ata_channel.ch_flags |= ATACH_DISABLED;
932 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH
933 }
934 #endif
935 }
936
937 void
pciide_unmap_compat_intr(pci_chipset_tag_t pc,struct pciide_channel * cp,int compatchan)938 pciide_unmap_compat_intr(pci_chipset_tag_t pc, struct pciide_channel *cp,
939 int compatchan)
940 {
941 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_DISESTABLISH
942 struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel);
943
944 pciide_machdep_compat_intr_disestablish(sc->sc_wdcdev.sc_atac.atac_dev,
945 sc->sc_pc, compatchan, cp->ih);
946 #endif
947 }
948
949 void
default_chip_map(struct pciide_softc * sc,const struct pci_attach_args * pa)950 default_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa)
951 {
952 struct pciide_channel *cp;
953 pcireg_t interface = PCI_INTERFACE(pa->pa_class);
954 pcireg_t csr;
955 int channel;
956 #if NATA_DMA
957 int drive;
958 u_int8_t idedma_ctl;
959 #endif
960 const char *failreason;
961 struct wdc_regs *wdr;
962
963 if (pciide_chipen(sc, pa) == 0)
964 return;
965
966 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) {
967 #if NATA_DMA
968 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
969 "bus-master DMA support present");
970 if (sc->sc_pp == &default_product_desc &&
971 (device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags &
972 PCIIDE_OPTIONS_DMA) == 0) {
973 aprint_verbose(", but unused (no driver support)");
974 sc->sc_dma_ok = 0;
975 } else {
976 pciide_mapreg_dma(sc, pa);
977 if (sc->sc_dma_ok != 0)
978 aprint_verbose(", used without full driver "
979 "support");
980 }
981 #else
982 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
983 "bus-master DMA support present, but unused (no driver "
984 "support)");
985 #endif /* NATA_DMA */
986 } else {
987 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
988 "hardware does not support DMA");
989 #if NATA_DMA
990 sc->sc_dma_ok = 0;
991 #endif
992 }
993 aprint_verbose("\n");
994 #if NATA_DMA
995 if (sc->sc_dma_ok) {
996 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA;
997 sc->sc_wdcdev.irqack = pciide_irqack;
998 }
999 #endif
1000 sc->sc_wdcdev.sc_atac.atac_pio_cap = 0;
1001 #if NATA_DMA
1002 sc->sc_wdcdev.sc_atac.atac_dma_cap = 0;
1003 #endif
1004
1005 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
1006 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
1007 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16;
1008 sc->sc_wdcdev.wdc_maxdrives = 2;
1009
1010 wdc_allocate_regs(&sc->sc_wdcdev);
1011
1012 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
1013 channel++) {
1014 cp = &sc->pciide_channels[channel];
1015 if (pciide_chansetup(sc, channel, interface) == 0)
1016 continue;
1017 wdr = CHAN_TO_WDC_REGS(&cp->ata_channel);
1018 if (interface & PCIIDE_INTERFACE_PCI(channel))
1019 pciide_mapregs_native(pa, cp, pciide_pci_intr);
1020 else
1021 pciide_mapregs_compat(pa, cp,
1022 cp->ata_channel.ch_channel);
1023 if (cp->ata_channel.ch_flags & ATACH_DISABLED)
1024 continue;
1025 /*
1026 * Check to see if something appears to be there.
1027 */
1028 failreason = NULL;
1029 /*
1030 * In native mode, always enable the controller. It's
1031 * not possible to have an ISA board using the same address
1032 * anyway.
1033 */
1034 if (interface & PCIIDE_INTERFACE_PCI(channel)) {
1035 wdcattach(&cp->ata_channel);
1036 continue;
1037 }
1038 if (!wdcprobe(&cp->ata_channel)) {
1039 failreason = "not responding; disabled or no drives?";
1040 goto next;
1041 }
1042 /*
1043 * Now, make sure it's actually attributable to this PCI IDE
1044 * channel by trying to access the channel again while the
1045 * PCI IDE controller's I/O space is disabled. (If the
1046 * channel no longer appears to be there, it belongs to
1047 * this controller.) YUCK!
1048 */
1049 csr = pci_conf_read(sc->sc_pc, sc->sc_tag,
1050 PCI_COMMAND_STATUS_REG);
1051 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG,
1052 csr & ~PCI_COMMAND_IO_ENABLE);
1053 if (wdcprobe(&cp->ata_channel))
1054 failreason = "other hardware responding at addresses";
1055 pci_conf_write(sc->sc_pc, sc->sc_tag,
1056 PCI_COMMAND_STATUS_REG, csr);
1057 next:
1058 if (failreason) {
1059 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
1060 "%s channel ignored (%s)\n", cp->name, failreason);
1061 cp->ata_channel.ch_flags |= ATACH_DISABLED;
1062 bus_space_unmap(wdr->cmd_iot, wdr->cmd_baseioh,
1063 wdr->cmd_ios);
1064 bus_space_unmap(wdr->ctl_iot, wdr->ctl_ioh,
1065 wdr->ctl_ios);
1066 } else {
1067 pciide_map_compat_intr(pa, cp,
1068 cp->ata_channel.ch_channel);
1069 wdcattach(&cp->ata_channel);
1070 }
1071 }
1072
1073 #if NATA_DMA
1074 if (sc->sc_dma_ok == 0)
1075 return;
1076
1077 /* Allocate DMA maps */
1078 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
1079 channel++) {
1080 idedma_ctl = 0;
1081 cp = &sc->pciide_channels[channel];
1082 for (drive = 0; drive < sc->sc_wdcdev.wdc_maxdrives; drive++) {
1083 /*
1084 * we have not probed the drives yet, allocate
1085 * ressources for all of them.
1086 */
1087 if (pciide_dma_table_setup(sc, channel, drive) != 0) {
1088 /* Abort DMA setup */
1089 aprint_error(
1090 "%s:%d:%d: can't allocate DMA maps, "
1091 "using PIO transfers\n",
1092 device_xname(
1093 sc->sc_wdcdev.sc_atac.atac_dev),
1094 channel, drive);
1095 sc->sc_dma_ok = 0;
1096 sc->sc_wdcdev.sc_atac.atac_cap &= ~ATAC_CAP_DMA;
1097 sc->sc_wdcdev.irqack = NULL;
1098 break;
1099 }
1100 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
1101 }
1102 if (idedma_ctl != 0) {
1103 /* Add software bits in status register */
1104 bus_space_write_1(sc->sc_dma_iot,
1105 cp->dma_iohs[IDEDMA_CTL], 0, idedma_ctl);
1106 }
1107 }
1108 #endif /* NATA_DMA */
1109 }
1110
1111 void
sata_setup_channel(struct ata_channel * chp)1112 sata_setup_channel(struct ata_channel *chp)
1113 {
1114 #if NATA_DMA
1115 struct ata_drive_datas *drvp;
1116 int drive;
1117 #if NATA_UDMA
1118 int s;
1119 #endif
1120 u_int32_t idedma_ctl;
1121 struct pciide_channel *cp = CHAN_TO_PCHAN(chp);
1122 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
1123
1124 /* setup DMA if needed */
1125 pciide_channel_dma_setup(cp);
1126
1127 idedma_ctl = 0;
1128
1129 KASSERT(cp->ata_channel.ch_ndrives != 0);
1130 for (drive = 0; drive < cp->ata_channel.ch_ndrives; drive++) {
1131 drvp = &chp->ch_drive[drive];
1132 /* If no drive, skip */
1133 if (drvp->drive_type == ATA_DRIVET_NONE)
1134 continue;
1135 #if NATA_UDMA
1136 if (drvp->drive_flags & ATA_DRIVE_UDMA) {
1137 /* use Ultra/DMA */
1138 s = splbio();
1139 drvp->drive_flags &= ~ATA_DRIVE_DMA;
1140 splx(s);
1141 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
1142 } else
1143 #endif /* NATA_UDMA */
1144 if (drvp->drive_flags & ATA_DRIVE_DMA) {
1145 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
1146 }
1147 }
1148
1149 /*
1150 * Nothing to do to setup modes; it is meaningless in S-ATA
1151 * (but many S-ATA drives still want to get the SET_FEATURE
1152 * command).
1153 */
1154 if (idedma_ctl != 0) {
1155 /* Add software bits in status register */
1156 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0,
1157 idedma_ctl);
1158 }
1159 #endif /* NATA_DMA */
1160 }
1161