1 /* 2 * Copyright 2012-16 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DAL_CLK_MGR_H__ 27 #define __DAL_CLK_MGR_H__ 28 29 #include "dc.h" 30 #include "dm_pp_smu.h" 31 32 #define DCN_MINIMUM_DISPCLK_Khz 100000 33 #define DCN_MINIMUM_DPPCLK_Khz 100000 34 35 /* Constants */ 36 #define DDR4_DRAM_WIDTH 64 37 #define WM_A 0 38 #define WM_B 1 39 #define WM_C 2 40 #define WM_D 3 41 #define WM_SET_COUNT 4 42 43 #define DCN_MINIMUM_DISPCLK_Khz 100000 44 #define DCN_MINIMUM_DPPCLK_Khz 100000 45 46 struct dcn3_clk_internal { 47 int dummy; 48 /*TODO: 49 uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk 50 uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk 51 uint32_t CLK1_CLK2_CURRENT_CNT; //dprefclk 52 uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk 53 uint32_t CLK1_CLK3_DS_CNTL; //dcf_deep_sleep_divider 54 uint32_t CLK1_CLK3_ALLOW_DS; //dcf_deep_sleep_allow 55 56 uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass 57 uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass 58 uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass 59 uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass 60 */ 61 }; 62 63 struct dcn301_clk_internal { 64 int dummy; 65 uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk 66 uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk 67 uint32_t CLK1_CLK2_CURRENT_CNT; //dprefclk 68 uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk 69 uint32_t CLK1_CLK3_DS_CNTL; //dcf_deep_sleep_divider 70 uint32_t CLK1_CLK3_ALLOW_DS; //dcf_deep_sleep_allow 71 72 uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass 73 uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass 74 uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass 75 uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass 76 }; 77 78 /* Will these bw structures be ASIC specific? */ 79 80 #define MAX_NUM_DPM_LVL 8 81 #define WM_SET_COUNT 4 82 83 84 struct clk_limit_table_entry { 85 unsigned int voltage; /* milivolts withh 2 fractional bits */ 86 unsigned int dcfclk_mhz; 87 unsigned int fclk_mhz; 88 unsigned int memclk_mhz; 89 unsigned int socclk_mhz; 90 unsigned int dtbclk_mhz; 91 unsigned int dispclk_mhz; 92 unsigned int dppclk_mhz; 93 unsigned int phyclk_mhz; 94 unsigned int phyclk_d18_mhz; 95 unsigned int wck_ratio; 96 }; 97 98 struct clk_limit_num_entries { 99 unsigned int num_dcfclk_levels; 100 unsigned int num_fclk_levels; 101 unsigned int num_memclk_levels; 102 unsigned int num_socclk_levels; 103 unsigned int num_dtbclk_levels; 104 unsigned int num_dispclk_levels; 105 unsigned int num_dppclk_levels; 106 unsigned int num_phyclk_levels; 107 unsigned int num_phyclk_d18_levels; 108 }; 109 110 /* This table is contiguous */ 111 struct clk_limit_table { 112 struct clk_limit_table_entry entries[MAX_NUM_DPM_LVL]; 113 struct clk_limit_num_entries num_entries_per_clk; 114 unsigned int num_entries; /* highest populated dpm level for back compatibility */ 115 }; 116 117 struct wm_range_table_entry { 118 unsigned int wm_inst; 119 unsigned int wm_type; 120 double pstate_latency_us; 121 double sr_exit_time_us; 122 double sr_enter_plus_exit_time_us; 123 bool valid; 124 }; 125 126 struct nv_wm_range_entry { 127 bool valid; 128 129 struct { 130 uint8_t wm_type; 131 uint16_t min_dcfclk; 132 uint16_t max_dcfclk; 133 uint16_t min_uclk; 134 uint16_t max_uclk; 135 } pmfw_breakdown; 136 137 struct { 138 double pstate_latency_us; 139 double sr_exit_time_us; 140 double sr_enter_plus_exit_time_us; 141 double fclk_change_latency_us; 142 } dml_input; 143 }; 144 145 struct clk_log_info { 146 bool enabled; 147 char *pBuf; 148 unsigned int bufSize; 149 unsigned int *sum_chars_printed; 150 }; 151 152 struct clk_state_registers_and_bypass { 153 uint32_t dcfclk; 154 uint32_t dcf_deep_sleep_divider; 155 uint32_t dcf_deep_sleep_allow; 156 uint32_t dprefclk; 157 uint32_t dispclk; 158 uint32_t dppclk; 159 uint32_t dtbclk; 160 161 uint32_t dppclk_bypass; 162 uint32_t dcfclk_bypass; 163 uint32_t dprefclk_bypass; 164 uint32_t dispclk_bypass; 165 }; 166 167 struct rv1_clk_internal { 168 uint32_t CLK0_CLK8_CURRENT_CNT; //dcfclk 169 uint32_t CLK0_CLK8_DS_CNTL; //dcf_deep_sleep_divider 170 uint32_t CLK0_CLK8_ALLOW_DS; //dcf_deep_sleep_allow 171 uint32_t CLK0_CLK10_CURRENT_CNT; //dprefclk 172 uint32_t CLK0_CLK11_CURRENT_CNT; //dispclk 173 174 uint32_t CLK0_CLK8_BYPASS_CNTL; //dcfclk bypass 175 uint32_t CLK0_CLK10_BYPASS_CNTL; //dprefclk bypass 176 uint32_t CLK0_CLK11_BYPASS_CNTL; //dispclk bypass 177 }; 178 179 struct rn_clk_internal { 180 uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk 181 uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk 182 uint32_t CLK1_CLK2_CURRENT_CNT; //dprefclk 183 uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk 184 uint32_t CLK1_CLK3_DS_CNTL; //dcf_deep_sleep_divider 185 uint32_t CLK1_CLK3_ALLOW_DS; //dcf_deep_sleep_allow 186 187 uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass 188 uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass 189 uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass 190 uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass 191 192 }; 193 194 /* For dtn logging and debugging */ 195 struct clk_state_registers { 196 uint32_t CLK0_CLK8_CURRENT_CNT; //dcfclk 197 uint32_t CLK0_CLK8_DS_CNTL; //dcf_deep_sleep_divider 198 uint32_t CLK0_CLK8_ALLOW_DS; //dcf_deep_sleep_allow 199 uint32_t CLK0_CLK10_CURRENT_CNT; //dprefclk 200 uint32_t CLK0_CLK11_CURRENT_CNT; //dispclk 201 }; 202 203 /* TODO: combine this with the above */ 204 struct clk_bypass { 205 uint32_t dcfclk_bypass; 206 uint32_t dispclk_pypass; 207 uint32_t dprefclk_bypass; 208 }; 209 /* 210 * This table is not contiguous, can have holes, each 211 * entry correspond to one set of WM. For example if 212 * we have 2 DPM and LPDDR, we will WM set A, B and 213 * D occupied, C will be emptry. 214 */ 215 struct wm_table { 216 union { 217 struct nv_wm_range_entry nv_entries[WM_SET_COUNT]; 218 struct wm_range_table_entry entries[WM_SET_COUNT]; 219 }; 220 }; 221 222 struct dummy_pstate_entry { 223 unsigned int dram_speed_mts; 224 double dummy_pstate_latency_us; 225 }; 226 227 struct clk_bw_params { 228 unsigned int vram_type; 229 unsigned int num_channels; 230 unsigned int dram_channel_width_bytes; 231 unsigned int dispclk_vco_khz; 232 unsigned int dc_mode_softmax_memclk; 233 unsigned int max_memclk_mhz; 234 struct clk_limit_table clk_table; 235 struct wm_table wm_table; 236 struct dummy_pstate_entry dummy_pstate_table[4]; 237 struct clk_limit_table_entry dc_mode_limit; 238 }; 239 /* Public interfaces */ 240 241 struct clk_states { 242 uint32_t dprefclk_khz; 243 }; 244 245 struct clk_mgr_funcs { 246 /* 247 * This function should set new clocks based on the input "safe_to_lower". 248 * If safe_to_lower == false, then only clocks which are to be increased 249 * should changed. 250 * If safe_to_lower == true, then only clocks which are to be decreased 251 * should be changed. 252 */ 253 void (*update_clocks)(struct clk_mgr *clk_mgr, 254 struct dc_state *context, 255 bool safe_to_lower); 256 257 int (*get_dp_ref_clk_frequency)(struct clk_mgr *clk_mgr); 258 int (*get_dtb_ref_clk_frequency)(struct clk_mgr *clk_mgr); 259 260 void (*set_low_power_state)(struct clk_mgr *clk_mgr); 261 262 void (*init_clocks)(struct clk_mgr *clk_mgr); 263 264 void (*dump_clk_registers)(struct clk_state_registers_and_bypass *regs_and_bypass, 265 struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info); 266 267 void (*enable_pme_wa) (struct clk_mgr *clk_mgr); 268 void (*get_clock)(struct clk_mgr *clk_mgr, 269 struct dc_state *context, 270 enum dc_clock_type clock_type, 271 struct dc_clock_config *clock_cfg); 272 273 bool (*are_clock_states_equal) (struct dc_clocks *a, 274 struct dc_clocks *b); 275 void (*notify_wm_ranges)(struct clk_mgr *clk_mgr); 276 277 /* Notify clk_mgr of a change in link rate, update phyclk frequency if necessary */ 278 void (*notify_link_rate_change)(struct clk_mgr *clk_mgr, struct dc_link *link); 279 /* 280 * Send message to PMFW to set hard min memclk frequency 281 * When current_mode = false, set DPM0 282 * When current_mode = true, set required clock for current mode 283 */ 284 void (*set_hard_min_memclk)(struct clk_mgr *clk_mgr, bool current_mode); 285 286 /* Send message to PMFW to set hard max memclk frequency to highest DPM */ 287 void (*set_hard_max_memclk)(struct clk_mgr *clk_mgr); 288 289 /* Custom set a memclk freq range*/ 290 void (*set_max_memclk)(struct clk_mgr *clk_mgr, unsigned int memclk_mhz); 291 void (*set_min_memclk)(struct clk_mgr *clk_mgr, unsigned int memclk_mhz); 292 293 /* Get current memclk states from PMFW, update relevant structures */ 294 void (*get_memclk_states_from_smu)(struct clk_mgr *clk_mgr); 295 296 /* Get SMU present */ 297 bool (*is_smu_present)(struct clk_mgr *clk_mgr); 298 299 int (*get_dispclk_from_dentist)(struct clk_mgr *clk_mgr_base); 300 301 }; 302 303 struct clk_mgr { 304 struct dc_context *ctx; 305 struct clk_mgr_funcs *funcs; 306 struct dc_clocks clks; 307 bool psr_allow_active_cache; 308 bool force_smu_not_present; 309 bool dc_mode_softmax_enabled; 310 int dprefclk_khz; // Used by program pixel clock in clock source funcs, need to figureout where this goes 311 int dentist_vco_freq_khz; 312 struct clk_state_registers_and_bypass boot_snapshot; 313 struct clk_bw_params *bw_params; 314 struct pp_smu_wm_range_sets ranges; 315 }; 316 317 /* forward declarations */ 318 struct dccg; 319 320 struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg *dccg); 321 322 void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr); 323 324 void clk_mgr_exit_optimized_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr); 325 326 void clk_mgr_optimize_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr); 327 328 #endif /* __DAL_CLK_MGR_H__ */ 329