1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the 13 * next paragraph) shall be included in all copies or substantial portions 14 * of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR 20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Midhunchandra Kodiyath <midhunchandra.kodiyath@intel.com> 26 * 27 */ 28 29 #ifndef _MEDIA__DRIVER_HW_G75_H 30 #define _MEDIA__DRIVER_HW_G75_H 31 32 #include "media_drv_encoder.h" 33 #include "media_drv_hw.h" 34 #define NUM_OF_VP8_KERNELS 12 35 #define MAX_QP_VP8 128 36 extern MEDIA_KERNEL media_hybrid_vp8_kernels[NUM_OF_VP8_KERNELS]; 37 extern struct hw_codec_info gen75_hw_codec_info; 38 extern const BYTE rasterscan_48x40_vp8_g75[56]; 39 extern const UINT new_mv_skip_threshold_VP8_g75[128]; 40 extern const BYTE diamond_vp8_g75[56]; 41 extern const UINT16 mv_ref_cost_context_vp8_g75[6][4][2]; 42 extern const BYTE fullspiral_48x40_vp8_g75[56]; 43 extern const UINT single_su_vp8_g75[14]; 44 extern const UINT cost_table_vp8_g75[128][7]; 45 extern const UINT new_mv_skip_threshold_VP8_g75[128]; 46 extern const UINT16 quant_dc_vp8_g75[MAX_QP_VP8]; 47 extern const UINT16 quant_ac_vp8_g75[MAX_QP_VP8]; 48 extern const BYTE frame_i_vme_cost_vp8_g75[128][4]; 49 extern const UINT16 quant_dc2_vp8_g75[]; 50 extern const UINT16 quant_ac2_vp8_g75[]; 51 extern const UINT16 quant_dc_uv_vp8_g75[]; 52 extern const SURFACE_SET_PARAMS surface_set_params_init; 53 extern const BYTE brc_qpadjustment_distthreshold_maxframethreshold_distqpadjustment_IPB_vp8_g75[576]; 54 extern const BYTE brc_iframe_cost_table_vp8_g75 [512]; 55 extern const UINT16 brc_skip_mv_threshold_table_vp8_g75 [128]; 56 57 #define HSW_SCS_ZERO 0 58 #define HSW_SCS_ONE 1 59 #define HSW_SCS_RED 4 60 #define HSW_SCS_GREEN 5 61 #define HSW_SCS_BLUE 6 62 #define HSW_SCS_ALPHA 7 63 #define MAX_QP_VP8_G75 127 64 #define MB_CODE_SIZE_VP8 204 65 #define MB_MV_CODE_SIZE_VP8 64 66 #define MB_CODE_ALIGNMENT 32 67 #define MB_MV_ALIGNMENT 4096 68 #define DC_BIAS_SEGMENT_DEFAULT_VAL_VP8 1500 69 70 #define QUAND_INDEX_Y1_DC_VP8 0 71 #define QUAND_INDEX_UV_DC_VP8 1 72 #define QUAND_INDEX_UV_AC_VP8 2 73 #define QUAND_INDEX_Y2_DC_VP8 3 74 #define QUAND_INDEX_Y2_AC_VP8 4 75 76 // AVC_ME CURBE 77 #if 1 78 #define OBJECT_BUFFER_TO_MEDIA_RESOURCE_STRUCT(obj_buffer,obj_buffer_res) \ 79 { \ 80 obj_buffer_res->bo=obj_buffer->buffer_store->bo; \ 81 obj_buffer_res->bo_size=obj_buffer->size_element;/*need to fill this later*/ \ 82 obj_buffer_res->buf=NULL; \ 83 obj_buffer_res->surface_array_spacing=0; \ 84 } 85 #define OBJECT_SURFACE_TO_MEDIA_RESOURCE_STRUCT(surface_2d,obj_surface) \ 86 { \ 87 surface_2d.width=obj_surface->orig_width; \ 88 surface_2d.height=obj_surface->orig_height; \ 89 surface_2d.bo=obj_surface->bo; \ 90 surface_2d.bo_size=0; \ 91 surface_2d.pitch=obj_surface->width; \ 92 dri_bo_get_tiling(obj_surface->bo, &surface_2d.tiling, &surface_2d.swizzle); \ 93 surface_2d.buf=NULL; \ 94 surface_2d.surface_array_spacing=0; \ 95 surface_2d.cb_cr_pitch=obj_surface->cb_cr_pitch; \ 96 surface_2d.x_cb_offset=obj_surface->x_cb_offset; \ 97 surface_2d.y_cb_offset=obj_surface->y_cb_offset; \ 98 } 99 100 typedef enum _BINDING_TABLE_OFFSET_VP8_ME_G75 101 { 102 VP8_ME_MV_DATA_SURFACE_G75 = 0, 103 VP8_16xME_MV_DATA_SURFACE_G75 = 1, 104 VP8_ME_DISTORTION_SURFACE_G75 = 2, 105 VP8_ME_BRC_DISTORTION_SURFACE_G75 = 3, 106 VP8_ME_INTER_PRED_G75 = 4, 107 VP8_ME_LAST_REF_PIC_G75 = 5, 108 VP8_ME_GOLDEN_REF_PIC_G75 = 7, 109 VP8_ME_ALTERNATE_REF_PIC_G75 = 9, 110 VP8_ME_NUM_SURFACES_G75 = 10 111 } BINDING_TABLE_OFFSET_VP8_ME_G75; 112 113 typedef enum _BINDING_TABLE_OFFSET_VP8_MBPAK_G75 114 { 115 VP8_MBPAK_PER_MB_OUT_G75 = 0, 116 VP8_MBPAK_CURR_Y_G75 = 1, 117 VP8_MBPAK_CURR_UV_G75 = 2, 118 VP8_MBPAK_CURR_RECON_Y_G75 = 3, 119 VP8_MBPAK_CURR_RECON_UV_G75 = 4, 120 //phase1 surfaces 121 VP8_MBPAK_LAST_REF_Y_G75 = 5, 122 VP8_MBPAK_LAST_REF_UV_G75 = 6, 123 VP8_MBPAK_GOLDEN_REF_Y_G75 = 7, 124 VP8_MBPAK_GOLDEN_REF_UV_G75 = 8, 125 VP8_MBPAK_ALTERNATE_REF_Y_G75 = 9, 126 VP8_MBPAK_ALTERNATE_REF_UV_G75 = 10, 127 VP8_MBPAK_IND_MV_DATA_G75 = 11, 128 //Phase2 surfaces 129 VP8_MBPAK_ROW_BUFF_Y_G75 = 5, 130 VP8_MBPAK_ROW_BUFF_UV_G75 = 6, 131 VP8_MBPAK_COL_BUFF_Y_G75 = 7, 132 VP8_MBPAK_COL_BUFF_UV_G75 = 8, 133 VP8_MBPAK_DEBUG_STREAMOUT_G75 = 12, 134 VP8_MBPAK_NUM_SURFACES_G75 = 13 135 } BINDING_TABLE_OFFSET_VP8_MBPAK_G75; 136 137 typedef enum _BINDING_TABLE_OFFSET_VP8_BRC_INIT_RESET_G75 138 { 139 VP8_BRC_INIT_RESET_HISTORY_G75 = 0, 140 VP8_BRC_INIT_RESET_DISTORTION_G75 = 1, 141 VP8_BRC_INIT_RESET_NUM_SURFACES_G75 = 2 142 } BINDING_TABLE_OFFSET_VP8_BRC_INIT_RESET_G75; 143 144 typedef enum _BINDING_TABLE_OFFSET_VP8_BRC_UPDATE_G75 145 { 146 VP8_BRC_UPDATE_HISTORY_G75 = 0, 147 VP8_BRC_UPDATE_PAK_SURFACE_INDEX_G75 = 1, 148 VP8_BRC_UPDATE_MBPAK1_CURBE_WRITE_G75 = 2, 149 VP8_BRC_UPDATE_MBPAK2_CURBE_WRITE_G75 = 3, 150 VP8_BRC_UPDATE_MBENC_CURBE_READ_G75 = 4, 151 VP8_BRC_UPDATE_MBENC_CURBE_WRITE_G75 = 5, 152 VP8_BRC_UPDATE_DISTORTION_SURFACE_G75 = 6, 153 VP8_BRC_UPDATE_CONSTANT_DATA_G75 = 7, 154 VP8_BRC_UPDATE_MBPAK_TABLE_INDEX_G75 = 8, 155 VP8_BRC_UPDATE_SEGMENT_MAP_G75 = 9, 156 VP8_BRC_UPDATE_NUM_SURFACES_G75 = 10 157 } BINDING_TABLE_OFFSET_VP8_BRC_UPDATE_G75; 158 159 typedef struct _search_path_delta 160 { 161 BYTE search_path_delta_x:4; 162 BYTE search_path_delta_y:4; 163 } SEARCH_PATH_DELTA; 164 typedef struct _media_curbe_data_mbpak_p1_g75 165 { 166 // dw0 167 union 168 { 169 struct 170 { 171 UINT frame_width:16; 172 UINT frame_height:16; 173 }; 174 struct 175 { 176 UINT dw0_val; 177 }; 178 } dw0; 179 180 // dw1 181 union 182 { 183 struct 184 { 185 UINT:8; 186 UINT sharpness_level:8; 187 UINT:4; 188 UINT loop_filter_type:1; 189 UINT frame_type:1; 190 UINT recon_filter_type:3; 191 UINT clamping_flag:1; 192 UINT:6; 193 }; 194 struct 195 { 196 UINT dw1_val; 197 }; 198 } dw1; 199 200 // dw2 201 union 202 { 203 struct 204 { 205 UINT y_dc_q_mul_factor_segment0:16; 206 UINT y_ac_q_mul_factor_segment0:16; 207 }; 208 struct 209 { 210 UINT dw2_val; 211 }; 212 } dw2; 213 214 // dw3 215 union 216 { 217 struct 218 { 219 UINT y2_dc_q_mul_factor_segment0:16; 220 UINT y2_ac_q_mul_factor_segment0:16; 221 }; 222 struct 223 { 224 UINT dw3_val; 225 }; 226 } dw3; 227 228 // dw4 229 union 230 { 231 struct 232 { 233 UINT uv_dc_q_mul_factor_segment0:16; 234 UINT uv_ac_q_mul_factor_segment0:16; 235 }; 236 struct 237 { 238 UINT dw4_val; 239 }; 240 } dw4; 241 242 // dw5 243 union 244 { 245 struct 246 { 247 UINT y_dc_inv_q_mul_factor_segment0:16; 248 UINT y_ac_inv_q_mul_factor_segment0:16; 249 }; 250 struct 251 { 252 UINT dw5_val; 253 }; 254 } dw5; 255 256 // dw6 257 union 258 { 259 struct 260 { 261 UINT y2_dc_inv_q_mul_factor_segment0:16; 262 UINT y2_ac_inv_q_mul_factor_segment0:16; 263 }; 264 struct 265 { 266 UINT dw6_val; 267 }; 268 } dw6; 269 270 // dw7 271 union 272 { 273 struct 274 { 275 UINT uv_dc_inv_q_mul_factor_segment0:16; 276 UINT uv_ac_inv_q_mul_factor_segment0:16; 277 }; 278 struct 279 { 280 UINT dw7_val; 281 }; 282 } dw7; 283 284 // dw8 285 union 286 { 287 struct 288 { 289 UINT y2_dc_q_shift_factor_segment0:8; 290 UINT y2_ac_q_shift_factor_segment0:8; 291 UINT y_dc_q_shift_factor_segment0:8; 292 UINT y_ac_q_shift_factor_segment0:8; 293 }; 294 struct 295 { 296 UINT dw8_val; 297 }; 298 } dw8; 299 300 // dw9 301 union 302 { 303 struct 304 { 305 UINT uv_dc_q_shift_factor_segment0:8; 306 UINT uv_ac_q_shift_factor_segment0:8; 307 }; 308 struct 309 { 310 UINT dw9_val; 311 }; 312 } dw9; 313 314 // dw10 315 union 316 { 317 struct 318 { 319 UINT y_dc_q_mul_factor_segment1:16; 320 UINT y_ac_q_mul_factor_segment1:16; 321 }; 322 struct 323 { 324 UINT dw10_val; 325 }; 326 } dw10; 327 328 // dw11 329 union 330 { 331 struct 332 { 333 UINT y2_dc_q_mul_factor_segment1:16; 334 UINT y2_ac_q_mul_factor_segment1:16; 335 }; 336 struct 337 { 338 UINT dw11_val; 339 }; 340 } dw11; 341 342 // dw12 343 union 344 { 345 struct 346 { 347 UINT uv_dc_q_mul_factor_segment1:16; 348 UINT uv_ac_q_mul_factor_segment1:16; 349 }; 350 struct 351 { 352 UINT dw12_val; 353 }; 354 } dw12; 355 356 // dw13 357 union 358 { 359 struct 360 { 361 UINT y_dc_inv_q_mul_factor_segment1:16; 362 UINT y_ac_inv_q_mul_factor_segment1:16; 363 }; 364 struct 365 { 366 UINT dw13_val; 367 }; 368 } dw13; 369 370 // dw14 371 union 372 { 373 struct 374 { 375 UINT y2_dc_inv_q_mul_factor_segment1:16; 376 UINT y2_ac_inv_q_mul_factor_segment1:16; 377 }; 378 struct 379 { 380 UINT dw14_val; 381 }; 382 } dw14; 383 384 // dw15 385 union 386 { 387 struct 388 { 389 UINT uv_dc_inv_q_mul_factor_segment1:16; 390 UINT uv_ac_inv_q_mul_factor_segment1:16; 391 }; 392 struct 393 { 394 UINT dw15_val; 395 }; 396 } dw15; 397 398 // dw16 399 union 400 { 401 struct 402 { 403 UINT y2_dc_q_shift_factor_segment1:8; 404 UINT y2_ac_q_shift_factor_segment1:8; 405 UINT y_dc_q_shift_factor_segment1:8; 406 UINT y_ac_q_shift_factor_segment1:8; 407 }; 408 struct 409 { 410 UINT dw16_val; 411 }; 412 } dw16; 413 414 // dw17 415 union 416 { 417 struct 418 { 419 UINT uv_dc_q_shift_factor_segment1:8; 420 UINT uv_ac_q_shift_factor_segment1:8; 421 }; 422 struct 423 { 424 UINT dw17_val; 425 }; 426 } dw17; 427 428 // dw18 429 union 430 { 431 struct 432 { 433 UINT y_dc_q_mul_factor_segment2:16; 434 UINT y_ac_q_mul_factor_segment2:16; 435 }; 436 struct 437 { 438 UINT dw18_val; 439 }; 440 } dw18; 441 442 // dw19 443 union 444 { 445 struct 446 { 447 UINT y2_dc_q_mul_factor_segment2:16; 448 UINT y2_ac_q_mul_factor_segment2:16; 449 }; 450 struct 451 { 452 UINT dw19_val; 453 }; 454 } dw19; 455 456 // dw20 457 union 458 { 459 struct 460 { 461 UINT uv_dc_q_mul_factor_segment2:16; 462 UINT uv_ac_q_mul_factor_segment2:16; 463 }; 464 struct 465 { 466 UINT dw20_val; 467 }; 468 } dw20; 469 470 // dw21 471 union 472 { 473 struct 474 { 475 UINT y_dc_inv_q_mul_factor_segment2:16; 476 UINT y_ac_inv_q_mul_factor_segment2:16; 477 }; 478 struct 479 { 480 UINT dw21_val; 481 }; 482 } dw21; 483 484 // dw22 485 union 486 { 487 struct 488 { 489 UINT y2_dc_inv_q_mul_factor_segment2:16; 490 UINT y2_ac_inv_q_mul_factor_segment2:16; 491 }; 492 struct 493 { 494 UINT dw22_val; 495 }; 496 } dw22; 497 498 // dw23 499 union 500 { 501 struct 502 { 503 UINT uv_dc_inv_q_mul_factor_segment2:16; 504 UINT uv_ac_inv_q_mul_factor_segment2:16; 505 }; 506 struct 507 { 508 UINT dw23_val; 509 }; 510 } dw23; 511 512 // dw24 513 union 514 { 515 struct 516 { 517 UINT y2_dc_q_shift_factor_segment2:8; 518 UINT y2_ac_q_shift_factor_segment2:8; 519 UINT y_dc_q_shift_factor_segment2:8; 520 UINT y_ac_q_shift_factor_segment2:8; 521 }; 522 struct 523 { 524 UINT dw24_val; 525 }; 526 } dw24; 527 528 // dw25 529 union 530 { 531 struct 532 { 533 UINT uv_dc_q_shift_factor_segment2:8; 534 UINT uv_ac_q_shift_factor_segment2:8; 535 }; 536 struct 537 { 538 UINT dw25_val; 539 }; 540 } dw25; 541 542 // dw26 543 union 544 { 545 struct 546 { 547 UINT y_dc_q_mul_factor_segment3:16; 548 UINT y_ac_q_mul_factor_segment3:16; 549 }; 550 struct 551 { 552 UINT dw26_val; 553 }; 554 } dw26; 555 556 // dw27 557 union 558 { 559 struct 560 { 561 UINT y2_dc_q_mul_factor_segment3:16; 562 UINT y2_ac_q_mul_factor_segment3:16; 563 }; 564 struct 565 { 566 UINT dw27_val; 567 }; 568 } dw27; 569 570 // dw28 571 union 572 { 573 struct 574 { 575 UINT uv_dc_q_mul_factor_segment3:16; 576 UINT uv_ac_q_mul_factor_segment3:16; 577 }; 578 struct 579 { 580 UINT dw28_val; 581 }; 582 } dw28; 583 584 // dw29 585 union 586 { 587 struct 588 { 589 UINT y_dc_inv_q_mul_factor_segment3:16; 590 UINT y_ac_inv_q_mul_factor_segment3:16; 591 }; 592 struct 593 { 594 UINT dw29_val; 595 }; 596 } dw29; 597 598 // dw30 599 union 600 { 601 struct 602 { 603 UINT y2_dc_inv_q_mul_factor_segment3:16; 604 UINT y2_ac_inv_q_mul_factor_segment3:16; 605 }; 606 struct 607 { 608 UINT dw30_val; 609 }; 610 } dw30; 611 612 // dw31 613 union 614 { 615 struct 616 { 617 UINT uv_dc_inv_q_mul_factor_segment3:16; 618 UINT uv_ac_inv_q_mul_factor_segment3:16; 619 }; 620 struct 621 { 622 UINT dw31_val; 623 }; 624 } dw31; 625 626 // dw32 627 union 628 { 629 struct 630 { 631 UINT y2_dc_q_shift_factor_segment3:8; 632 UINT y2_ac_q_shift_factor_segment3:8; 633 UINT y_dc_q_shift_factor_segment3:8; 634 UINT y_ac_q_shift_factor_segment3:8; 635 }; 636 struct 637 { 638 UINT dw32_val; 639 }; 640 } dw32; 641 642 // dw33 643 union 644 { 645 struct 646 { 647 UINT uv_dc_q_shift_factor_segment3:8; 648 UINT uv_ac_q_shift_factor_segment3:8; 649 }; 650 struct 651 { 652 UINT dw33_val; 653 }; 654 } dw33; 655 656 // dw34 657 union 658 { 659 struct 660 { 661 UINT ref_frame_lf_delta0:8; 662 UINT ref_frame_lf_delta1:8; 663 UINT ref_frame_lf_delta2:8; 664 UINT ref_frame_lf_delta3:8; 665 }; 666 struct 667 { 668 UINT dw34_val; 669 }; 670 } dw34; 671 672 // dw35 673 union 674 { 675 struct 676 { 677 UINT mode_lf_delta0:8; 678 UINT mode_lf_delta1:8; 679 UINT mode_lf_delta2:8; 680 UINT mode_lf_delta3:8; 681 }; 682 struct 683 { 684 UINT dw35_val; 685 }; 686 } dw35; 687 688 // dw36 689 union 690 { 691 struct 692 { 693 694 UINT lf_level0:8; 695 UINT lf_level1:8; 696 UINT lf_level2:8; 697 UINT lf_level3:8; 698 }; 699 struct 700 { 701 UINT dw36_val; 702 }; 703 } dw36; 704 705 // dw37 706 union 707 { 708 struct 709 { 710 UINT dw37_val; 711 }; 712 } dw37; 713 714 // dw38 715 union 716 { 717 struct 718 { 719 UINT dw38_val; 720 }; 721 } dw38; 722 723 // dw39 724 union 725 { 726 struct 727 { 728 UINT dw39_val; 729 }; 730 } dw39; 731 732 // dw40 733 union 734 { 735 struct 736 { 737 UINT pak_per_mb_out_data_surf_bti:32; 738 }; 739 struct 740 { 741 UINT dw40_val; 742 }; 743 } dw40; 744 745 // dw41 746 union 747 { 748 struct 749 { 750 UINT mb_enc_curr_y_bti:32; 751 }; 752 struct 753 { 754 UINT dw41_val; 755 }; 756 } dw41; 757 758 // dw42 759 union 760 { 761 struct 762 { 763 UINT pak_recon_y_bti:32; 764 }; 765 struct 766 { 767 UINT dw42_val; 768 }; 769 } dw42; 770 771 // dw43 772 union 773 { 774 struct 775 { 776 UINT pak_last_ref_pic_y_bti:32; 777 }; 778 struct 779 { 780 UINT dw43_val; 781 }; 782 } dw43; 783 784 // dw44 785 union 786 { 787 struct 788 { 789 UINT pak_golden_ref_pic_y_bti:32; 790 }; 791 struct 792 { 793 UINT dw44_val; 794 }; 795 } dw44; 796 797 // dw45 798 union 799 { 800 struct 801 { 802 UINT pak_alternate_ref_pic_y_bti:32; 803 }; 804 struct 805 { 806 UINT dw45_val; 807 }; 808 } dw45; 809 810 // dw46 811 union 812 { 813 struct 814 { 815 UINT pak_ind_mv_data_bti:32; 816 }; 817 struct 818 { 819 UINT dw46_val; 820 }; 821 } dw46; 822 823 // dw47 824 union 825 { 826 struct 827 { 828 UINT pak_kernel_debug_bti:32; 829 }; 830 struct 831 { 832 UINT dw47_val; 833 }; 834 } dw47; 835 836 } MEDIA_CURBE_DATA_MBPAK_P1_G75; 837 838 typedef struct _media_curbe_data_mbpak_p2_g75 839 { 840 // dw0 841 union 842 { 843 struct 844 { 845 UINT frame_width:16; 846 UINT frame_height:16; 847 }; 848 struct 849 { 850 UINT dw0_val; 851 }; 852 } dw0; 853 854 // dw1 855 union 856 { 857 struct 858 { 859 UINT:8; 860 UINT sharpness_level:8; 861 UINT:4; 862 UINT loop_filter_type:1; 863 UINT frame_type:1; 864 UINT recon_filter_type:3; 865 UINT clamping_flag:1; 866 UINT:6; 867 }; 868 struct 869 { 870 UINT dw1_val; 871 }; 872 } dw1; 873 874 // dw2 875 union 876 { 877 struct 878 { 879 UINT y_dc_q_mul_factor_segment0:16; 880 UINT y_ac_q_mul_factor_segment0:16; 881 }; 882 struct 883 { 884 UINT dw2_val; 885 }; 886 } dw2; 887 888 // dw3 889 union 890 { 891 struct 892 { 893 UINT y2_dc_q_mul_factor_segment0:16; 894 UINT y2_ac_q_mul_factor_segment0:16; 895 }; 896 struct 897 { 898 UINT dw3_val; 899 }; 900 } dw3; 901 902 // dw4 903 union 904 { 905 struct 906 { 907 UINT uv_dc_q_mul_factor_segment0:16; 908 UINT uv_ac_q_mul_factor_segment0:16; 909 }; 910 struct 911 { 912 UINT dw4_val; 913 }; 914 } dw4; 915 916 // dw5 917 union 918 { 919 struct 920 { 921 UINT y_dc_inv_q_mul_factor_segment0:16; 922 UINT y_ac_inv_q_mul_factor_segment0:16; 923 }; 924 struct 925 { 926 UINT dw5_val; 927 }; 928 } dw5; 929 930 // dw6 931 union 932 { 933 struct 934 { 935 UINT y2_dc_inv_q_mul_factor_segment0:16; 936 UINT y2_ac_inv_q_mul_factor_segment0:16; 937 }; 938 struct 939 { 940 UINT dw6_val; 941 }; 942 } dw6; 943 944 // dw7 945 union 946 { 947 struct 948 { 949 UINT uv_dc_inv_q_mul_factor_segment0:16; 950 UINT uv_ac_inv_q_mul_factor_segment0:16; 951 }; 952 struct 953 { 954 UINT dw7_val; 955 }; 956 } dw7; 957 958 // dw8 959 union 960 { 961 struct 962 { 963 UINT y2_dc_q_shift_factor_segment0:8; 964 UINT y2_ac_q_shift_factor_segment0:8; 965 UINT y_dc_q_shift_factor_segment0:8; 966 UINT y_ac_q_shift_factor_segment0:8; 967 }; 968 struct 969 { 970 UINT dw8_val; 971 }; 972 } dw8; 973 974 // dw9 975 union 976 { 977 struct 978 { 979 UINT uv_dc_q_shift_factor_segment0:8; 980 UINT uv_ac_q_shift_factor_segment0:8; 981 }; 982 struct 983 { 984 UINT dw9_val; 985 }; 986 } dw9; 987 988 // dw10 989 union 990 { 991 struct 992 { 993 UINT y_dc_q_mul_factor_segment1:16; 994 UINT y_ac_q_mul_factor_segment1:16; 995 }; 996 struct 997 { 998 UINT dw10_val; 999 }; 1000 } dw10; 1001 1002 // dw11 1003 union 1004 { 1005 struct 1006 { 1007 UINT y2_dc_q_mul_factor_segment1:16; 1008 UINT y2_ac_q_mul_factor_segment1:16; 1009 }; 1010 struct 1011 { 1012 UINT dw11_val; 1013 }; 1014 } dw11; 1015 1016 // dw12 1017 union 1018 { 1019 struct 1020 { 1021 UINT uv_dc_q_mul_factor_segment1:16; 1022 UINT uv_ac_q_mul_factor_segment1:16; 1023 }; 1024 struct 1025 { 1026 UINT dw12_val; 1027 }; 1028 } dw12; 1029 1030 // dw13 1031 union 1032 { 1033 struct 1034 { 1035 UINT y_dc_inv_q_mul_factor_segment1:16; 1036 UINT y_ac_inv_q_mul_factor_segment1:16; 1037 }; 1038 struct 1039 { 1040 UINT dw13_val; 1041 }; 1042 } dw13; 1043 1044 // dw14 1045 union 1046 { 1047 struct 1048 { 1049 UINT y2_dc_inv_q_mul_factor_segment1:16; 1050 UINT y2_ac_inv_q_mul_factor_segment1:16; 1051 }; 1052 struct 1053 { 1054 UINT dw14_val; 1055 }; 1056 } dw14; 1057 1058 // dw15 1059 union 1060 { 1061 struct 1062 { 1063 UINT uv_dc_inv_q_mul_factor_segment1:16; 1064 UINT uv_ac_inv_q_mul_factor_segment1:16; 1065 }; 1066 struct 1067 { 1068 UINT dw15_val; 1069 }; 1070 } dw15; 1071 1072 // dw16 1073 union 1074 { 1075 struct 1076 { 1077 UINT y2_dc_q_shift_factor_segment1:8; 1078 UINT y2_ac_q_shift_factor_segment1:8; 1079 UINT y_dc_q_shift_factor_segment1:8; 1080 UINT y_ac_q_shift_factor_segment1:8; 1081 }; 1082 struct 1083 { 1084 UINT dw16_val; 1085 }; 1086 } dw16; 1087 1088 // dw17 1089 union 1090 { 1091 struct 1092 { 1093 UINT uv_dc_q_shift_factor_segment1:8; 1094 UINT uv_ac_q_shift_factor_segment1:8; 1095 }; 1096 struct 1097 { 1098 UINT dw17_val; 1099 }; 1100 } dw17; 1101 1102 // dw18 1103 union 1104 { 1105 struct 1106 { 1107 UINT y_dc_q_mul_factor_segment2:16; 1108 UINT y_ac_q_mul_factor_segment2:16; 1109 }; 1110 struct 1111 { 1112 UINT dw18_val; 1113 }; 1114 } dw18; 1115 1116 // dw19 1117 union 1118 { 1119 struct 1120 { 1121 UINT y2_dc_q_mul_factor_segment2:16; 1122 UINT y2_ac_q_mul_factor_segment2:16; 1123 }; 1124 struct 1125 { 1126 UINT dw19_val; 1127 }; 1128 } dw19; 1129 1130 // dw20 1131 union 1132 { 1133 struct 1134 { 1135 UINT uv_dc_q_mul_factor_segment2:16; 1136 UINT uv_ac_q_mul_factor_segment2:16; 1137 }; 1138 struct 1139 { 1140 UINT dw20_val; 1141 }; 1142 } dw20; 1143 1144 // dw21 1145 union 1146 { 1147 struct 1148 { 1149 UINT y_dc_inv_q_mul_factor_segment2:16; 1150 UINT y_ac_inv_q_mul_factor_segment2:16; 1151 }; 1152 struct 1153 { 1154 UINT dw21_val; 1155 }; 1156 } dw21; 1157 1158 // dw22 1159 union 1160 { 1161 struct 1162 { 1163 UINT y2_dc_inv_q_mul_factor_segment2:16; 1164 UINT y2_ac_inv_q_mul_factor_segment2:16; 1165 }; 1166 struct 1167 { 1168 UINT dw22_val; 1169 }; 1170 } dw22; 1171 1172 // dw23 1173 union 1174 { 1175 struct 1176 { 1177 UINT uv_dc_inv_q_mul_factor_segment2:16; 1178 UINT uv_ac_inv_q_mul_factor_segment2:16; 1179 }; 1180 struct 1181 { 1182 UINT dw23_val; 1183 }; 1184 } dw23; 1185 1186 // dw24 1187 union 1188 { 1189 struct 1190 { 1191 UINT y2_dc_q_shift_factor_segment2:8; 1192 UINT y2_ac_q_shift_factor_segment2:8; 1193 UINT y_dc_q_shift_factor_segment2:8; 1194 UINT y_ac_q_shift_factor_segment2:8; 1195 }; 1196 struct 1197 { 1198 UINT dw24_val; 1199 }; 1200 } dw24; 1201 1202 // dw25 1203 union 1204 { 1205 struct 1206 { 1207 UINT uv_dc_q_shift_factor_segment2:8; 1208 UINT uv_ac_q_shift_factor_segment2:8; 1209 }; 1210 struct 1211 { 1212 UINT dw25_val; 1213 }; 1214 } dw25; 1215 1216 // dw26 1217 union 1218 { 1219 struct 1220 { 1221 UINT y_dc_q_mul_factor_segment3:16; 1222 UINT y_ac_q_mul_factor_segment3:16; 1223 }; 1224 struct 1225 { 1226 UINT dw26_val; 1227 }; 1228 } dw26; 1229 1230 // dw27 1231 union 1232 { 1233 struct 1234 { 1235 UINT y2_dc_q_mul_factor_segment3:16; 1236 UINT y2_ac_q_mul_factor_segment3:16; 1237 }; 1238 struct 1239 { 1240 UINT dw27_val; 1241 }; 1242 } dw27; 1243 1244 // dw28 1245 union 1246 { 1247 struct 1248 { 1249 UINT uv_dc_q_mul_factor_segment3:16; 1250 UINT uv_ac_q_mul_factor_segment3:16; 1251 }; 1252 struct 1253 { 1254 UINT dw28_val; 1255 }; 1256 } dw28; 1257 1258 // dw29 1259 union 1260 { 1261 struct 1262 { 1263 UINT y_dc_inv_q_mul_factor_segment3:16; 1264 UINT y_ac_inv_q_mul_factor_segment3:16; 1265 }; 1266 struct 1267 { 1268 UINT dw29_val; 1269 }; 1270 } dw29; 1271 1272 // dw30 1273 union 1274 { 1275 struct 1276 { 1277 UINT y2_dc_inv_q_mul_factor_segment3:16; 1278 UINT y2_ac_inv_q_mul_factor_segment3:16; 1279 }; 1280 struct 1281 { 1282 UINT dw30_val; 1283 }; 1284 } dw30; 1285 1286 // dw31 1287 union 1288 { 1289 struct 1290 { 1291 UINT uv_dc_inv_q_mul_factor_segment3:16; 1292 UINT uv_ac_inv_q_mul_factor_segment3:16; 1293 }; 1294 struct 1295 { 1296 UINT dw31_val; 1297 }; 1298 } dw31; 1299 1300 // dw32 1301 union 1302 { 1303 struct 1304 { 1305 UINT y2_dc_q_shift_factor_segment3:8; 1306 UINT y2_ac_q_shift_factor_segment3:8; 1307 UINT y_dc_q_shift_factor_segment3:8; 1308 UINT y_ac_q_shift_factor_segment3:8; 1309 }; 1310 struct 1311 { 1312 UINT dw32_val; 1313 }; 1314 } dw32; 1315 1316 // dw33 1317 union 1318 { 1319 struct 1320 { 1321 UINT uv_dc_q_shift_factor_segment3:8; 1322 UINT uv_ac_q_shift_factor_segment3:8; 1323 }; 1324 struct 1325 { 1326 UINT dw33_val; 1327 }; 1328 } dw33; 1329 1330 // dw34 1331 union 1332 { 1333 struct 1334 { 1335 UINT ref_frame_lf_delta0:8; 1336 UINT ref_frame_lf_delta1:8; 1337 UINT ref_frame_lf_delta2:8; 1338 UINT ref_frame_lf_delta3:8; 1339 }; 1340 struct 1341 { 1342 UINT dw34_val; 1343 }; 1344 } dw34; 1345 1346 // dw35 1347 union 1348 { 1349 struct 1350 { 1351 UINT mode_lf_delta0:8; 1352 UINT mode_lf_delta1:8; 1353 UINT mode_lf_delta2:8; 1354 UINT mode_lf_delta3:8; 1355 }; 1356 struct 1357 { 1358 UINT dw35_val; 1359 }; 1360 } dw35; 1361 1362 // dw36 1363 union 1364 { 1365 struct 1366 { 1367 1368 UINT lf_level0:8; 1369 UINT lf_level1:8; 1370 UINT lf_level2:8; 1371 UINT lf_level3:8; 1372 }; 1373 struct 1374 { 1375 UINT dw36_val; 1376 }; 1377 } dw36; 1378 1379 // dw37 1380 union 1381 { 1382 struct 1383 { 1384 UINT dw37_val; 1385 }; 1386 } dw37; 1387 1388 // dw38 1389 union 1390 { 1391 struct 1392 { 1393 UINT dw38_val; 1394 }; 1395 } dw38; 1396 1397 // dw39 1398 union 1399 { 1400 struct 1401 { 1402 UINT dw39_val; 1403 }; 1404 } dw39; 1405 1406 // dw40 1407 union 1408 { 1409 struct 1410 { 1411 UINT pak_per_mb_out_data_surf_bti:32; 1412 }; 1413 struct 1414 { 1415 UINT dw40_val; 1416 }; 1417 } dw40; 1418 1419 // dw41 1420 union 1421 { 1422 struct 1423 { 1424 UINT mb_enc_curr_y_bti:32; 1425 }; 1426 struct 1427 { 1428 UINT dw41_val; 1429 }; 1430 } dw41; 1431 1432 // dw42 1433 union 1434 { 1435 struct 1436 { 1437 UINT pak_recon_y_bti:32; 1438 }; 1439 struct 1440 { 1441 UINT dw42_val; 1442 }; 1443 } dw42; 1444 1445 // dw43 1446 union 1447 { 1448 struct 1449 { 1450 UINT pak_row_buffer_y_bti:32; 1451 }; 1452 struct 1453 { 1454 UINT dw43_val; 1455 }; 1456 } dw43; 1457 1458 // dw44 1459 union 1460 { 1461 struct 1462 { 1463 UINT pak_row_buffer_uv_bti:32; 1464 }; 1465 struct 1466 { 1467 UINT dw44_val; 1468 }; 1469 } dw44; 1470 1471 // dw45 1472 union 1473 { 1474 struct 1475 { 1476 UINT pak_col_buffer_y_bti:32; 1477 }; 1478 struct 1479 { 1480 UINT dw45_val; 1481 }; 1482 } dw45; 1483 1484 // dw46 1485 union 1486 { 1487 struct 1488 { 1489 UINT pak_col_buffer_uv_bti:32; 1490 }; 1491 struct 1492 { 1493 UINT dw46_val; 1494 }; 1495 } dw46; 1496 1497 // dw47 1498 union 1499 { 1500 struct 1501 { 1502 UINT pak_kernel_debug_bti:32; 1503 }; 1504 struct 1505 { 1506 UINT dw47_val; 1507 }; 1508 } dw47; 1509 1510 } MEDIA_CURBE_DATA_MBPAK_P2_G75; 1511 1512 // VP8_MBEnc I frame kernel CURBE 1513 typedef struct _media_curbe_data_mbenc_i_g75 1514 { 1515 // dw0 1516 struct 1517 { 1518 UINT frame_width:16; 1519 UINT frame_height:16; 1520 } dw0; 1521 1522 // dw1 1523 struct 1524 { 1525 UINT frame_type:1; 1526 UINT enable_segmentation:1; 1527 UINT enable_hw_intra_prediction:1; 1528 UINT enable_debug_dumps:1; 1529 UINT enable_coeff_clamp:1; 1530 UINT enable_chroma_ip_enhancement:1; 1531 UINT enable_mpu_histogram_update:1; 1532 UINT reserved_mbz:1; 1533 UINT vme_enable_tm_check:1; 1534 UINT vme_distortion_measure:2; 1535 UINT:21; 1536 } dw1; 1537 1538 1539 // dw2 1540 struct 1541 { 1542 UINT lambda_seg_0:16; 1543 UINT lambda_seg_1:16; 1544 } dw2; 1545 1546 // dw3 1547 1548 struct 1549 { 1550 UINT lambda_seg_2:16; 1551 UINT lambda_seg_3:16; 1552 } dw3; 1553 1554 // dw4 1555 struct 1556 { 1557 UINT all_dc_bias_segment_0:16; 1558 UINT all_dc_bias_segment_1:16; 1559 } dw4; 1560 1561 // dw5 1562 struct 1563 { 1564 UINT all_dc_bias_segment_2:16; 1565 UINT all_dc_bias_segment_3:16; 1566 } dw5; 1567 1568 //dw6 1569 struct 1570 { 1571 UINT chroma_dc_de_quant_segment_0:16; 1572 UINT chroma_dc_de_quant_segment_1:16; 1573 } dw6; 1574 1575 1576 // dw7 1577 struct 1578 { 1579 UINT chroma_dc_de_quant_segment_2:16; 1580 UINT chroma_dc_de_quant_segment_3:16; 1581 } dw7; 1582 1583 // dw8 1584 struct 1585 { 1586 UINT chroma_ac_de_quant_segment0:16; 1587 UINT chroma_ac_de_quant_segment1:16; 1588 } dw8; 1589 1590 //dw9 1591 struct 1592 { 1593 UINT chroma_ac_de_quant_segment2:16; 1594 UINT chroma_ac_de_quant_segment3:16; 1595 } dw9; 1596 1597 // 1598 struct 1599 { 1600 UINT chroma_ac0_threshold0_segment0:16; 1601 UINT chroma_ac0_threshold1_segment0:16; 1602 } dw10; 1603 1604 // dw10 1605 1606 struct 1607 { 1608 UINT chroma_ac0_threshold0_segment1:16; 1609 UINT chroma_ac0_threshold1_segment1:16; 1610 } dw11; 1611 1612 1613 // dw12 1614 struct 1615 { 1616 UINT chroma_ac0_threshold0_segment2:16; 1617 UINT chroma_ac0_threshold1_segment2:16; 1618 1619 } dw12; 1620 1621 //dw13 1622 struct 1623 { 1624 UINT chroma_ac0_threshold0_segment3:16; 1625 UINT chroma_ac0_threshold1_segment3:16; 1626 } dw13; 1627 // dw14 1628 struct 1629 { 1630 UINT chroma_dc_threshold0_segment0:16; 1631 UINT chroma_dc_threshold1_segment0:16; 1632 } dw14; 1633 1634 // dw15 1635 struct 1636 { 1637 UINT chroma_dc_threshold2_segment0:16; 1638 UINT chroma_dc_threshold3_segment0:16; 1639 } dw15; 1640 1641 // dw16 1642 struct 1643 { 1644 UINT chroma_dc_threshold0_segment1:16; 1645 UINT chroma_dc_threshold1_segment1:16; 1646 } dw16; 1647 1648 // dw17 1649 struct 1650 { 1651 UINT chroma_dc_threshold2_segment1:16; 1652 UINT chroma_dc_threshold3_segment1:16; 1653 } dw17; 1654 1655 // dw18 1656 struct 1657 { 1658 UINT chroma_dc_threshold0_segment2:16; 1659 UINT chroma_dc_threshold1_segment2:16; 1660 } dw18; 1661 1662 // dw19 1663 struct 1664 { 1665 UINT chroma_dc_threshold2_segment2:16; 1666 UINT chroma_dc_threshold3_segment2:16; 1667 } dw19; 1668 1669 // dw20 1670 struct 1671 { 1672 UINT chroma_dc_threshold0_segment3:16; 1673 UINT chroma_dc_threshold1_segment3:16; 1674 } dw20; 1675 1676 // dw21 1677 struct 1678 { 1679 UINT chroma_dc_threshold2_segment3:16; 1680 UINT chroma_dc_threshold3_segment3:16; 1681 } dw21; 1682 1683 1684 // dw22 1685 struct 1686 { 1687 UINT chroma_ac1_threshold_segment0:16; 1688 UINT chroma_ac1_threshold_segment1:16; 1689 } dw22; 1690 1691 // dw23 1692 struct 1693 { 1694 UINT chroma_ac1_threshold_segment2:16; 1695 UINT chroma_ac1_threshold_segment3:16; 1696 } dw23; 1697 1698 1699 // dw24 1700 struct 1701 { 1702 UINT vme_16x16_cost_segment0:8; 1703 UINT vme_16x16_cost_segment1:8; 1704 UINT vme_16x16_cost_segment2:8; 1705 UINT vme_16x16_cost_segment3:8; 1706 } dw24; 1707 1708 //dw25 1709 1710 struct 1711 { 1712 UINT vme_4x4_cost_segment0:8; 1713 UINT vme_4x4_cost_segment1:8; 1714 UINT vme_4x4_cost_segment2:8; 1715 UINT vme_4x4_cost_segment3:8; 1716 } dw25; 1717 1718 // dw26 1719 struct 1720 { 1721 UINT vme_16x16_non_dc_penalty_segment0:8; 1722 UINT vme_16x16_non_dc_penalty_segment1:8; 1723 UINT vme_16x16_non_dc_penalty_segment2:8; 1724 UINT vme_16x16_non_dc_penalty_segment3:8; 1725 } dw26; 1726 1727 // dw27 1728 struct 1729 { 1730 UINT vme_4x4_non_dc_penalty_segment0:8; 1731 UINT vme_4x4_non_dc_penalty_segment1:8; 1732 UINT vme_4x4_non_dc_penalty_segment2:8; 1733 UINT vme_4x4_non_dc_penalty_segment3:8; 1734 } dw27; 1735 1736 // dw28 1737 struct 1738 { 1739 UINT reserved:32; 1740 } dw28; 1741 1742 // dw29 1743 struct 1744 { 1745 UINT reserved:32; 1746 } dw29; 1747 1748 1749 // dw30 1750 struct 1751 { 1752 UINT reserved:32; 1753 } dw30; 1754 // dw31 1755 struct 1756 { 1757 UINT reserved:32; 1758 } dw31; 1759 1760 // dw32 1761 struct 1762 { 1763 UINT mb_enc_per_mb_out_data_surf_bti:32; 1764 } dw32; 1765 // dw33 1766 struct 1767 { 1768 UINT mb_enc_curr_y_bti:32; 1769 } dw33; 1770 // dw34 1771 struct 1772 { 1773 UINT mb_enc_curr_uv_bti:32; 1774 } dw34; 1775 1776 // dw35 1777 struct 1778 { 1779 UINT mb_mode_cost_luma_bti:32; 1780 } dw35; 1781 // dw36 1782 struct 1783 { 1784 UINT mb_enc_block_mode_cost_bti:32; 1785 } dw36; 1786 1787 // dw37 1788 struct 1789 { 1790 UINT chroma_recon_surf_bti:32; 1791 } dw37; 1792 1793 // dw38 1794 struct 1795 { 1796 UINT segmentation_map_bti:32; 1797 } dw38; 1798 // dw39 1799 struct 1800 { 1801 UINT histogram_bti:32; 1802 } dw39; 1803 // dw40 1804 struct 1805 { 1806 UINT mb_enc_vme_debug_stream_out_bti:32; 1807 } dw40; 1808 1809 // dw41 1810 struct 1811 { 1812 UINT vme_bti:32; 1813 } dw41; 1814 1815 // dw42 1816 struct 1817 { 1818 UINT idist_surface:32; 1819 } dw42; 1820 // dw43 1821 struct 1822 { 1823 UINT curr_y_surface4x_downscaled:32; 1824 } dw43; 1825 // dw44 1826 struct 1827 { 1828 UINT vme_coarse_intra_surface:32; 1829 } dw44; 1830 1831 } MEDIA_CURBE_DATA_MBENC_I_G75; 1832 1833 1834 typedef struct _media_curbe_data_hme_kernel 1835 { 1836 1837 struct 1838 { 1839 UINT skip_mode_en:1; 1840 UINT adaptive_en:1; 1841 UINT Bi_dir_mix_dis:1; 1842 UINT:2; 1843 UINT early_ime_success_en:1; 1844 UINT:1; 1845 UINT t_8x8_flag_for_inter_en:1; 1846 UINT:16; 1847 UINT early_ime_stop:8; 1848 } dw0; 1849 1850 1851 1852 struct 1853 { 1854 UINT max_num_mvs:6; 1855 UINT:10; 1856 UINT bi_weight:6; 1857 UINT:6; 1858 UINT uni_mix_disable:1; 1859 UINT:3; 1860 } dw1; 1861 1862 1863 struct 1864 { 1865 UINT max_len_sp:8; 1866 UINT max_num_su:8; 1867 UINT:16; 1868 } dw2; 1869 1870 1871 1872 struct 1873 { 1874 UINT src_size:2; 1875 UINT:2; 1876 UINT mb_type_remap:2; 1877 UINT src_access:1; 1878 UINT ref_access:1; 1879 UINT search_ctrl:3; 1880 UINT dual_search_path_option:1; 1881 UINT sub_pel_mode:2; 1882 UINT skip_type:1; 1883 UINT disable_field_cache_alloc:1; 1884 UINT inter_chroma_mode:1; 1885 UINT fte_enable:1; 1886 UINT bme_disable_fbr:1; 1887 UINT block_based_skip_enable:1; 1888 UINT inter_sad:2; 1889 UINT intra_sad:2; 1890 UINT sub_mb_part_mask:7; 1891 UINT:1; 1892 } dw3; 1893 1894 1895 struct 1896 { 1897 UINT:8; 1898 UINT picture_height_minus1:8; 1899 UINT picture_width:8; 1900 UINT b_file_idr:1; 1901 UINT:7; 1902 } dw4; 1903 1904 struct 1905 { 1906 UINT:8; 1907 UINT qp_prime_y:8; 1908 UINT ref_width:8; 1909 UINT ref_height:8; 1910 1911 } dw5; 1912 1913 1914 struct 1915 { 1916 UINT:3; 1917 UINT me_modes:2; 1918 UINT:3; 1919 UINT super_combine_dist:8; 1920 UINT max_vmv_range:16; 1921 } dw6; 1922 1923 struct 1924 { 1925 UINT:16; 1926 UINT mv_cost_scale_factor:2; 1927 UINT bilinear_enable:1; 1928 UINT src_field_polarity:1; 1929 UINT en_weighted_sad_haar:1; 1930 UINT ac_only_haar:1; 1931 UINT ref_id_cost_mode:1; 1932 UINT:1; 1933 UINT skip_center_mask:8; 1934 } dw7; 1935 1936 1937 struct 1938 { 1939 UINT mode_0_cost:8; 1940 UINT mode_1_cost:8; 1941 UINT mode_2_cost:8; 1942 UINT mode_3_Cost:8; 1943 } dw8; 1944 1945 1946 struct 1947 { 1948 UINT mode_4_cost:8; 1949 UINT mode_5_cost:8; 1950 UINT mode_6_cost:8; 1951 UINT mode_7_cost:8; 1952 } dw9; 1953 1954 1955 struct 1956 { 1957 UINT mode_8_cost:8; 1958 UINT mode_9_cost:8; 1959 UINT ref_id_cost:8; 1960 UINT chroma_intra_mode_cost:8; 1961 } dw10; 1962 1963 struct 1964 { 1965 UINT mv_0_cost:8; 1966 UINT mv_1_cost:8; 1967 UINT mv_2_cost:8; 1968 UINT mv_3_cost:8; 1969 } dw11; 1970 1971 struct 1972 { 1973 UINT mv_4_cost:8; 1974 UINT mv_5_cost:8; 1975 UINT mv_6_cost:8; 1976 UINT mv_7_cost:8; 1977 } dw12; 1978 1979 1980 struct 1981 { 1982 UINT num_ref_idx_l0_minus_one:8; 1983 UINT num_ref_idx_l1_minus_one:8; 1984 UINT:16; 1985 } dw13; 1986 1987 struct 1988 { 1989 UINT reserved:32; 1990 } dw14; 1991 1992 struct 1993 { 1994 UINT reserved:32; 1995 1996 } dw15; 1997 1998 struct 1999 { 2000 SEARCH_PATH_DELTA sp_delta_0; 2001 SEARCH_PATH_DELTA sp_delta_1; 2002 SEARCH_PATH_DELTA sp_delta_2; 2003 SEARCH_PATH_DELTA sp_delta_3; 2004 } dw16; 2005 2006 struct 2007 { 2008 SEARCH_PATH_DELTA sp_delta_4; 2009 SEARCH_PATH_DELTA sp_delta_5; 2010 SEARCH_PATH_DELTA sp_delta_6; 2011 SEARCH_PATH_DELTA sp_delta_7; 2012 } dw17; 2013 2014 struct 2015 { 2016 SEARCH_PATH_DELTA SPDelta_8; 2017 SEARCH_PATH_DELTA SPDelta_9; 2018 SEARCH_PATH_DELTA SPDelta_10; 2019 SEARCH_PATH_DELTA SPDelta_11; 2020 } dw18; 2021 2022 struct 2023 { 2024 SEARCH_PATH_DELTA sp_delta_12; 2025 SEARCH_PATH_DELTA sp_delta_13; 2026 SEARCH_PATH_DELTA sp_delta_14; 2027 SEARCH_PATH_DELTA sp_delta_15; 2028 } dw19; 2029 2030 struct 2031 { 2032 SEARCH_PATH_DELTA sp_delta_16; 2033 SEARCH_PATH_DELTA sp_delta_17; 2034 SEARCH_PATH_DELTA sp_delta_18; 2035 SEARCH_PATH_DELTA sp_delta_19; 2036 } dw20; 2037 2038 struct 2039 { 2040 SEARCH_PATH_DELTA sp_delta_20; 2041 SEARCH_PATH_DELTA sp_delta_21; 2042 SEARCH_PATH_DELTA sp_delta_22; 2043 SEARCH_PATH_DELTA sp_delta_23; 2044 } dw21; 2045 2046 struct 2047 { 2048 SEARCH_PATH_DELTA sp_delta_24; 2049 SEARCH_PATH_DELTA sp_delta_25; 2050 SEARCH_PATH_DELTA sp_delta_26; 2051 SEARCH_PATH_DELTA sp_delta_27; 2052 } dw22; 2053 2054 struct 2055 { 2056 SEARCH_PATH_DELTA sp_delta_28; 2057 SEARCH_PATH_DELTA sp_delta_29; 2058 SEARCH_PATH_DELTA sp_delta_30; 2059 SEARCH_PATH_DELTA sp_delta_31; 2060 } dw23; 2061 2062 struct 2063 { 2064 SEARCH_PATH_DELTA sp_delta_32; 2065 SEARCH_PATH_DELTA sp_delta_33; 2066 SEARCH_PATH_DELTA sp_delta_34; 2067 SEARCH_PATH_DELTA sp_delta_35; 2068 } dw24; 2069 2070 struct 2071 { 2072 SEARCH_PATH_DELTA sp_delta_36; 2073 SEARCH_PATH_DELTA sp_delta_37; 2074 SEARCH_PATH_DELTA sp_delta_38; 2075 SEARCH_PATH_DELTA sp_delta_39; 2076 } dw25; 2077 struct 2078 { 2079 SEARCH_PATH_DELTA sp_delta_40; 2080 SEARCH_PATH_DELTA sp_delta_41; 2081 SEARCH_PATH_DELTA sp_delta_42; 2082 SEARCH_PATH_DELTA sp_delta_43; 2083 } dw26; 2084 2085 struct 2086 { 2087 SEARCH_PATH_DELTA sp_delta_44; 2088 SEARCH_PATH_DELTA sp_delta_45; 2089 SEARCH_PATH_DELTA sp_delta_46; 2090 SEARCH_PATH_DELTA sp_delta_47; 2091 } dw27; 2092 2093 struct 2094 { 2095 SEARCH_PATH_DELTA sp_delta_48; 2096 SEARCH_PATH_DELTA sp_delta_49; 2097 SEARCH_PATH_DELTA sp_delta_50; 2098 SEARCH_PATH_DELTA sp_delta_51; 2099 } dw28; 2100 2101 struct 2102 { 2103 SEARCH_PATH_DELTA sp_delta_52; 2104 SEARCH_PATH_DELTA sp_delta_53; 2105 SEARCH_PATH_DELTA sp_delta_54; 2106 SEARCH_PATH_DELTA sp_delta_55; 2107 } dw29; 2108 struct 2109 { 2110 UINT reserved; 2111 2112 } dw30; 2113 2114 struct 2115 { 2116 UINT reserved; 2117 2118 } dw31; 2119 2120 struct 2121 { 2122 UINT mv_data_surf:32; 2123 } dw32; 2124 struct 2125 { 2126 UINT mv_data_inp_surf:32; 2127 } dw33; 2128 2129 struct 2130 { 2131 UINT dist_surf:32; 2132 } dw34; 2133 2134 struct 2135 { 2136 UINT min_dist_brc_surf:32; 2137 } dw35; 2138 2139 struct 2140 { 2141 UINT mb_enc_vme_interpred:32; 2142 } dw36; 2143 2144 struct 2145 { 2146 UINT backward_ref_pic:32; 2147 } dw37; 2148 struct 2149 { 2150 UINT reserved:32; 2151 2152 } dw38; 2153 } MEDIA_CURBE_DATA_ME; 2154 #endif 2155 typedef struct _media_curbe_data_mbenc_p_g75 2156 { 2157 // dw0 2158 struct 2159 { 2160 UINT frame_width:16; 2161 UINT frame_height:16; 2162 } dw0; 2163 2164 // dw1 2165 struct 2166 { 2167 UINT frame_type:1; 2168 UINT motion_compensation_filter_type:2; 2169 UINT hme_enable:1; 2170 UINT hme_combine_overlap:2; 2171 UINT all_fractional:1; 2172 UINT multiple_pred_enable:1; 2173 UINT hme_combined_extra_su:8; 2174 UINT ref_ctrl:4; 2175 UINT enable_segmentation:1; 2176 UINT enable_segmentation_info_update:1; 2177 UINT enable_coeff_clamp:1; 2178 UINT multi_reference_qp_check:1; 2179 UINT mode_cost_enable_flag:1; 2180 UINT hme_coarse_shape:2; 2181 UINT reserved_mbz:4; 2182 UINT enable_debug_dumps:1; 2183 } dw1; 2184 // dw2 2185 struct 2186 { 2187 UINT lambda_intra_segment0:16; 2188 UINT lambda_inter_segment0:16; 2189 } dw2; 2190 2191 // dw3 2192 struct 2193 { 2194 UINT lambda_intra_segment1:16; 2195 UINT lambda_inter_segment1:16; 2196 } dw3; 2197 2198 //dw4 2199 struct 2200 { 2201 UINT lambda_intra_segment2:16; 2202 UINT lambda_inter_segment2:16; 2203 } dw4; 2204 2205 // dw5 2206 struct 2207 { 2208 UINT lambda_intra_segment3:16; 2209 UINT lambda_inter_segment3:16; 2210 } dw5; 2211 // dw6 2212 struct 2213 { 2214 UINT reference_frame_sign_bias_0:8; 2215 UINT reference_frame_sign_bias_1:8; 2216 UINT reference_frame_sign_bias_2:8; 2217 UINT reference_frame_sign_bias_3:8; 2218 } dw6; 2219 // dw7 2220 struct 2221 { 2222 UINT raw_dist_threshold:16; 2223 UINT reserved_mbz:16; 2224 } dw7; 2225 // dw8 2226 struct 2227 { 2228 UINT skip_mode_enable:1; 2229 UINT adaptive_search_enable:1; 2230 UINT bidirectional_mix_disbale:1; 2231 UINT reserved_mbz1:2; 2232 UINT early_ime_success_enable:1; 2233 UINT reserved_mbz2:1; 2234 UINT transform8x8_flag_for_inter_enable:1; 2235 UINT reserved_mbz3:16; 2236 UINT early_ime_successful_stop_threshold:8; 2237 } dw8; 2238 2239 //dw9 2240 struct 2241 { 2242 UINT max_num_of_motion_vectors:6; 2243 UINT reserved_mbz1:2; 2244 UINT ref_id_polarity_bits:8; 2245 UINT bidirectional_weight:6; 2246 UINT reserved_mbz2:6; 2247 UINT unidirection_mix_enable:1; 2248 UINT ref_pixel_bias_enable:1; 2249 UINT reserved_mbz3:2; 2250 } dw9; 2251 2252 2253 //dw10 2254 struct 2255 { 2256 UINT max_fixed_search_path_length:8; 2257 UINT maximum_search_path_length:8; 2258 UINT reserved_mbz:16; 2259 } dw10; 2260 2261 struct 2262 { 2263 UINT source_block_size:2; 2264 UINT reserved_mbz1:2; 2265 UINT inter_mb_type_road_map:2; 2266 UINT source_access:1; 2267 UINT reference_access:1; 2268 UINT search_control:3; 2269 UINT dual_search_path_option:1; 2270 UINT sub_pel_mode:2; 2271 UINT skip_mode_type:1; 2272 UINT disable_field_cache_allocation:1; 2273 UINT process_inter_chroma_pixels_mode:1; 2274 UINT forward_trans_form_skip_check_enable:1; 2275 UINT bme_disable_for_fbr_message:1; 2276 UINT block_based_skip_enable:1; 2277 UINT inter_sad_measure_adjustment:2; 2278 UINT intra_sad_measure_adjustment:2; 2279 UINT submacro_block_subPartition_mask:6; 2280 UINT reserved_mbz2:1; 2281 } dw11; 2282 2283 //dw12 2284 struct 2285 { 2286 UINT reserved_mbz:16; 2287 UINT reference_search_windows_width:8; 2288 UINT reference_search_windows_height:8; 2289 } dw12; 2290 2291 // dw13 2292 union 2293 { 2294 struct 2295 { 2296 UINT mode_0_cost_seg_0:8; 2297 UINT mode_1_cost_seg_0:8; 2298 UINT mode_2_cost_seg_0:8; 2299 UINT mode_3_cost_seg_0:8; 2300 }; 2301 struct 2302 { 2303 UINT mode_0_3_cost_seg0; 2304 }; 2305 } dw13; 2306 2307 // dw14 2308 union 2309 { 2310 struct 2311 { 2312 UINT mode_4_cost_seg_0:8; 2313 UINT mode_5_cost_seg_0:8; 2314 UINT mode_6_cost_seg_0:8; 2315 UINT mode_7_cost_seg_0:8; 2316 }; 2317 struct 2318 { 2319 UINT mode_4_7_cost_seg0; 2320 2321 }; 2322 2323 } dw14; 2324 2325 2326 //dw15 2327 union 2328 { 2329 struct 2330 { 2331 UINT mode_8_cost_seg_0:8; 2332 UINT mode_9_cost_seg_0:8; 2333 UINT ref_id_cost_seg_0:8; 2334 UINT chroma_cost_seg_0:8; 2335 }; 2336 struct 2337 { 2338 UINT val; 2339 2340 }; 2341 2342 } dw15; 2343 2344 //dw16 2345 struct 2346 { 2347 SEARCH_PATH_DELTA sp_delta_0; 2348 SEARCH_PATH_DELTA sp_delta_1; 2349 SEARCH_PATH_DELTA sp_delta_2; 2350 SEARCH_PATH_DELTA sp_delta_3; 2351 } dw16; 2352 2353 // dw17 2354 struct 2355 { 2356 SEARCH_PATH_DELTA sp_delta_4; 2357 SEARCH_PATH_DELTA sp_delta_5; 2358 SEARCH_PATH_DELTA sp_delta_6; 2359 SEARCH_PATH_DELTA sp_delta_7; 2360 } dw17; 2361 2362 // dw18 2363 struct 2364 { 2365 SEARCH_PATH_DELTA sp_delta_8; 2366 SEARCH_PATH_DELTA sp_delta_9; 2367 SEARCH_PATH_DELTA sp_delta_10; 2368 SEARCH_PATH_DELTA sp_delta_11; 2369 } dw18; 2370 2371 //dw19 2372 struct 2373 { 2374 SEARCH_PATH_DELTA sp_delta_12; 2375 SEARCH_PATH_DELTA sp_delta_13; 2376 SEARCH_PATH_DELTA sp_delta_14; 2377 SEARCH_PATH_DELTA sp_delta_15; 2378 } dw19; 2379 2380 // dw20 2381 struct 2382 { 2383 SEARCH_PATH_DELTA sp_delta_16; 2384 SEARCH_PATH_DELTA sp_delta_17; 2385 SEARCH_PATH_DELTA sp_delta_18; 2386 SEARCH_PATH_DELTA sp_delta_19; 2387 } dw20; 2388 2389 // dw21 2390 struct 2391 { 2392 SEARCH_PATH_DELTA sp_delta_20; 2393 SEARCH_PATH_DELTA sp_delta_21; 2394 SEARCH_PATH_DELTA sp_delta_22; 2395 SEARCH_PATH_DELTA sp_delta_23; 2396 } dw21; 2397 2398 // dw22 2399 struct 2400 { 2401 SEARCH_PATH_DELTA sp_delta_24; 2402 SEARCH_PATH_DELTA sp_delta_25; 2403 SEARCH_PATH_DELTA sp_delta_26; 2404 SEARCH_PATH_DELTA sp_delta_27; 2405 } dw22; 2406 2407 // dw23 2408 struct 2409 { 2410 SEARCH_PATH_DELTA sp_delta_28; 2411 SEARCH_PATH_DELTA sp_delta_29; 2412 SEARCH_PATH_DELTA sp_delta_30; 2413 SEARCH_PATH_DELTA sp_delta_31; 2414 } dw23; 2415 2416 2417 //dw24 2418 struct 2419 { 2420 SEARCH_PATH_DELTA sp_delta_32; 2421 SEARCH_PATH_DELTA sp_delta_33; 2422 SEARCH_PATH_DELTA sp_delta_34; 2423 SEARCH_PATH_DELTA sp_delta_35; 2424 } dw24; 2425 2426 //dw25 2427 struct 2428 { 2429 SEARCH_PATH_DELTA sp_delta_36; 2430 SEARCH_PATH_DELTA sp_delta_37; 2431 SEARCH_PATH_DELTA sp_delta_38; 2432 SEARCH_PATH_DELTA sp_delta_39; 2433 } dw25; 2434 2435 // dw26 2436 struct 2437 { 2438 SEARCH_PATH_DELTA sp_delta_40; 2439 SEARCH_PATH_DELTA sp_delta_41; 2440 SEARCH_PATH_DELTA sp_delta_42; 2441 SEARCH_PATH_DELTA sp_delta_43; 2442 }; 2443 2444 // dw27 2445 struct 2446 { 2447 SEARCH_PATH_DELTA sp_delta_44; 2448 SEARCH_PATH_DELTA sp_delta_45; 2449 SEARCH_PATH_DELTA sp_delta_46; 2450 SEARCH_PATH_DELTA sp_delta_47; 2451 } dw27; 2452 2453 2454 // dw28 2455 struct 2456 { 2457 SEARCH_PATH_DELTA sp_delta_48; 2458 SEARCH_PATH_DELTA sp_delta_49; 2459 SEARCH_PATH_DELTA sp_delta_50; 2460 SEARCH_PATH_DELTA sp_delta_51; 2461 } dw28; 2462 2463 // dw29 2464 struct 2465 { 2466 SEARCH_PATH_DELTA sp_delta_52; 2467 SEARCH_PATH_DELTA sp_delta_53; 2468 SEARCH_PATH_DELTA sp_delta_54; 2469 SEARCH_PATH_DELTA sp_delta_55; 2470 } dw29; 2471 2472 // dw30 2473 union 2474 { 2475 struct 2476 { 2477 UINT mv_0_cost_seg_0:8; 2478 UINT mv_1_cost_seg_0:8; 2479 UINT mv_2_cost_seg_0:8; 2480 UINT mv_3_cost_seg_0:8; 2481 2482 }; 2483 struct 2484 { 2485 UINT mv_cost_seg_val; 2486 }; 2487 2488 } dw30; 2489 2490 // dw31 2491 union 2492 { 2493 struct 2494 { 2495 UINT mv_4_cost_seg_0:8; 2496 UINT mv_5_cost_seg_0:8; 2497 UINT mv_6_cost_seg_0:8; 2498 UINT mv_7_cost_seg_0:8; 2499 } dw31; 2500 struct 2501 { 2502 UINT mv_cost_seg_val; 2503 }; 2504 2505 } dw31; 2506 // dw32 2507 2508 struct 2509 { 2510 UINT intra_16x16_no_dc_penalty_segment0:8; 2511 UINT intra_16x16_no_dc_penalty_segment1:8; 2512 UINT reserved_mbz1:7; 2513 UINT bilinear_enable:1; 2514 UINT reserved_mbz2:8; 2515 } dw32; 2516 2517 // dw33 2518 struct 2519 { 2520 UINT hme_combine_len:16; 2521 UINT intra_16x16_no_dc_penalty_segment2:8; 2522 UINT intra_16x16_no_dc_penalty_segment3:8; 2523 } dw33; 2524 2525 // dw34 2526 struct 2527 { 2528 UINT mv_ref_cost_context_0_0_0:16; 2529 UINT mv_ref_cost_context_0_0_1:16; 2530 } dw34; 2531 2532 2533 // dw35 2534 struct 2535 { 2536 UINT mv_ref_cost_context_0_1_0:16; 2537 UINT mv_ref_cost_context_0_1_1:16; 2538 } dw35; 2539 2540 2541 // dw36 2542 struct 2543 { 2544 UINT mv_ref_cost_context_0_2_0:16; 2545 UINT mv_ref_cost_context_0_2_1:16; 2546 } dw36; 2547 2548 // dw37 2549 struct 2550 { 2551 UINT mv_ref_cost_context_0_3_0:16; 2552 UINT mv_ref_cost_context_0_3_1:16; 2553 } dw37; 2554 2555 2556 // dw38 2557 struct 2558 { 2559 UINT mv_ref_cost_context_1_0_0:16; 2560 UINT mv_ref_cost_context_1_0_1:16; 2561 } dw38; 2562 2563 // dw39 2564 struct 2565 { 2566 UINT mv_ref_cost_context_1_1_0:16; 2567 UINT mv_ref_cost_context_1_1_1:16; 2568 } dw39; 2569 2570 // dw40 2571 struct 2572 { 2573 UINT mv_ref_cost_context_1_2_0:16; 2574 UINT mv_ref_cost_context_1_2_1:16; 2575 } dw40; 2576 2577 // dw41 2578 struct 2579 { 2580 UINT mv_ref_cost_context_1_3_0:16; 2581 UINT mv_ref_cost_context_1_3_1:16; 2582 } dw41; 2583 2584 // dw42 2585 struct 2586 { 2587 UINT mv_ref_cost_context_2_0_0:16; 2588 UINT mv_ref_cost_context_2_0_1:16; 2589 }; 2590 // dw43 2591 struct 2592 { 2593 UINT mv_ref_cost_context_2_1_0:16; 2594 UINT mv_ref_cost_context_2_1_1:16; 2595 }; 2596 2597 // dw44 2598 struct 2599 { 2600 UINT mv_ref_cost_context_2_2_0:16; 2601 UINT mv_ref_cost_context_2_2_1:16; 2602 } dw44; 2603 2604 // dw45 2605 struct 2606 { 2607 UINT mv_ref_cost_context_2_3_0:16; 2608 UINT mv_ref_cost_context_2_3_1:16; 2609 } dw45; 2610 2611 // dw46 2612 struct 2613 { 2614 UINT mv_ref_cost_context_3_0_0:16; 2615 UINT mv_ref_cost_context_3_0_1:16; 2616 } dw46; 2617 // dw47 2618 struct 2619 { 2620 UINT mv_ref_cost_context_3_1_0:16; 2621 UINT mv_ref_cost_context_3_1_1:16; 2622 } dw47; 2623 2624 // dw48 2625 struct 2626 { 2627 UINT mv_ref_cost_context_3_2_0:16; 2628 UINT mv_ref_cost_context_3_2_1:16; 2629 } dw48; 2630 2631 // dw49 2632 struct 2633 { 2634 UINT mv_ref_cost_context_3_3_0:16; 2635 UINT mv_ref_cost_context_3_3_1:16; 2636 } dw49; 2637 2638 struct 2639 { 2640 UINT mv_ref_cost_context_4_0_0:16; 2641 UINT mv_ref_cost_context_4_0_1:16; 2642 } dw50; 2643 2644 // dw51 2645 struct 2646 { 2647 UINT mv_ref_cost_context_4_1_0:16; 2648 UINT mv_ref_cost_context_4_1_1:16; 2649 } dw51; 2650 2651 // dw52 2652 struct 2653 { 2654 UINT mv_ref_cost_context_4_2_0:16; 2655 UINT mv_ref_cost_context_4_2_1:16; 2656 }; 2657 2658 // dw53 2659 struct 2660 { 2661 UINT mv_ref_cost_context_4_3_0:16; 2662 UINT mv_ref_cost_context_4_3_1:16; 2663 }; 2664 2665 // dw54 2666 struct 2667 { 2668 UINT mv_ref_cost_context_5_0_0:16; 2669 UINT mv_ref_cost_context_5_0_1:16; 2670 }; 2671 2672 // dw55 2673 struct 2674 { 2675 UINT mv_ref_cost_context_5_1_0:16; 2676 UINT mv_ref_cost_context_5_1_1:16; 2677 } dw55; 2678 2679 // dw56 2680 struct 2681 { 2682 UINT mv_ref_cost_context_5_2_0:16; 2683 UINT mv_ref_cost_context_5_2_1:16; 2684 } dw56; 2685 2686 // dw57 2687 struct 2688 { 2689 UINT mv_ref_cost_context_5_3_0:16; 2690 UINT mv_ref_cost_context_5_3_1:16; 2691 } dw57; 2692 2693 // dw58 2694 struct 2695 { 2696 UINT enc_cost_16x16:16; 2697 UINT enc_cost_16x8:16; 2698 } dw58; 2699 2700 // dw59 2701 struct 2702 { 2703 UINT enc_cost_8x8:16; 2704 UINT enc_cost_4x4:16; 2705 } dw59; 2706 2707 // dw60 2708 struct 2709 { 2710 UINT frame_count_probability_ref_frame_cost_0:16; 2711 UINT frame_count_probability_ref_frame_cost_1:16; 2712 } dw60; 2713 2714 // dw61 2715 struct 2716 { 2717 UINT frame_count_probability_ref_frame_cost_2:16; 2718 UINT frame_count_probability_ref_frame_cost_3:16; 2719 } dw61; 2720 2721 // dw62 2722 struct 2723 { 2724 UINT average_qp_of_last_ref_frame:8; 2725 UINT average_qp_of_gold_ref_frame:8; 2726 UINT average_qp_of_alt_ref_frame:8; 2727 UINT reserved_mbz:8; 2728 } dw62; 2729 2730 // dw63 2731 struct 2732 { 2733 UINT intra_4x4_no_dc_penalty_segment0:8; 2734 UINT intra_4x4_no_dc_penalty_segment1:8; 2735 UINT intra_4x4_no_dc_penalty_segment2:8; 2736 UINT intra_4x4_no_dc_penalty_segment3:8; 2737 } dw63; 2738 2739 // dw64 2740 union 2741 { 2742 struct 2743 { 2744 UINT mode_0_cost_segment1:8; 2745 UINT mode_1_cost_segment1:8; 2746 UINT mode_2_cost_segment1:8; 2747 UINT mode_3_cost_segment1:8; 2748 }; 2749 struct 2750 { 2751 UINT mode_cost_seg_1_val; 2752 2753 }; 2754 } dw64; 2755 2756 //dw65 2757 union 2758 { 2759 struct 2760 { 2761 UINT mode_4_cost_segment1:8; 2762 UINT mode_5_cost_segment1:8; 2763 UINT mode_6_cost_segment1:8; 2764 UINT mode_7_cost_segment1:8; 2765 }; 2766 struct 2767 { 2768 UINT mode_cost_seg_1_val; 2769 2770 }; 2771 } dw65; 2772 2773 // dw66 2774 union 2775 { 2776 struct 2777 { 2778 UINT mode_8_cost_segment1:8; 2779 UINT mode_9_cost_segment1:8; 2780 UINT ref_id_cost_segment1:8; 2781 UINT chroma_cost_sSegment1:8; 2782 }; 2783 2784 struct 2785 { 2786 UINT mode_cost_seg_1_val; 2787 2788 }; 2789 } dw66; 2790 2791 2792 // dw67 2793 union 2794 { 2795 struct 2796 { 2797 UINT mv_0_cost_segment1:8; 2798 UINT mv_1_cost_segment1:8; 2799 UINT mv_2_cost_segment1:8; 2800 UINT mv_3_cost_segment1:8; 2801 }; 2802 struct 2803 { 2804 UINT mv_cost_seg1_val; 2805 }; 2806 2807 } dw67; 2808 2809 // dw68 2810 union 2811 { 2812 struct 2813 { 2814 UINT mv_4_cost_segment1:8; 2815 UINT mv_5_cost_segment1:8; 2816 UINT mv_6_cost_segment1:8; 2817 UINT mv_7_cost_segment1:8; 2818 }; 2819 2820 struct 2821 { 2822 UINT mv_cost_seg1_val; 2823 }; 2824 } dw68; 2825 2826 // dw69 2827 union 2828 { 2829 struct 2830 { 2831 UINT mode_0_cost_segment2:8; 2832 UINT mode_1_cost_segment2:8; 2833 UINT mode_2_cost_segment2:8; 2834 UINT mode_3_cost_segment2:8; 2835 }; 2836 struct 2837 { 2838 UINT mv_cost_seg2_val; 2839 }; 2840 2841 } dw69; 2842 2843 // dw70 2844 union 2845 { 2846 struct 2847 { 2848 UINT mode_4_cost_segment2:8; 2849 UINT mode_5_cost_segment2:8; 2850 UINT mode_6_cost_segment2:8; 2851 UINT mode_7_cost_segment2:8; 2852 }; 2853 2854 struct 2855 { 2856 UINT mv_cost_seg2_val; 2857 2858 }; 2859 } dw70; 2860 2861 // dw71 2862 union 2863 { 2864 struct 2865 { 2866 UINT mode_8_cost_segment2:8; 2867 UINT mode_9_cost_segment2:8; 2868 UINT ref_id_cost_segment2:8; 2869 UINT chroma_cost_segment2:8; 2870 }; 2871 struct 2872 { 2873 UINT mv_cost_seg2_val; 2874 }; 2875 } dw71; 2876 2877 // dw72 2878 union 2879 { 2880 struct 2881 { 2882 UINT mv_0_cost_segment2:8; 2883 UINT mv_1_cost_segment2:8; 2884 UINT mv_2_cost_segment2:8; 2885 UINT mv_3_cost_segment2:8; 2886 }; 2887 struct 2888 { 2889 UINT mv_cost_seg2; 2890 }; 2891 } dw72; 2892 2893 // dw73 2894 union 2895 { 2896 struct 2897 { 2898 UINT mv_4_cost_segment2:8; 2899 UINT mv_5_cost_segment2:8; 2900 UINT mv_6_cost_segment2:8; 2901 UINT mv_7_cost_segment2:8; 2902 }; 2903 struct 2904 { 2905 UINT mv_cost_seg2; 2906 }; 2907 } dw73; 2908 // dw74 2909 union 2910 { 2911 struct 2912 { 2913 UINT mode_0_cost_segment3:8; 2914 UINT mode_1_cost_segment3:8; 2915 UINT mode_2_cost_segment3:8; 2916 UINT mode_3_cost_segment3:8; 2917 }; 2918 struct 2919 { 2920 UINT mode_cost_seg3; 2921 2922 }; 2923 } dw74; 2924 // dw75 2925 union 2926 { 2927 struct 2928 { 2929 UINT mode_4_costSegment3:8; 2930 UINT mode_5_costSegment3:8; 2931 UINT mode_6_costSegment3:8; 2932 UINT mode_7_costSegment3:8; 2933 }; 2934 struct 2935 { 2936 UINT mode_cost_seg3; 2937 }; 2938 } dw75; 2939 2940 2941 // dw76 2942 union 2943 { 2944 struct 2945 { 2946 UINT mode_8_cost_segment3:8; 2947 UINT mode_9_cost_segment3:8; 2948 UINT ref_id_cost_segment3:8; 2949 UINT chroma_cost_segment3:8; 2950 2951 }; 2952 struct 2953 { 2954 UINT mode_cost_seg3; 2955 }; 2956 } dw76; 2957 2958 // dw77 2959 union 2960 { 2961 struct 2962 { 2963 UINT mv_0_cost_segment3:8; 2964 UINT mv_1_cost_segment3:8; 2965 UINT mv_2_cost_segment3:8; 2966 UINT mv_3_cost_segment3:8; 2967 }; 2968 struct 2969 { 2970 UINT mv_cost_seg3; 2971 }; 2972 } dw77; 2973 2974 2975 // dw78 2976 union 2977 { 2978 struct 2979 { 2980 UINT mv_4_cost_segment3:8; 2981 UINT mv_5_cost_segment3:8; 2982 UINT mv_6_cost_segment3:8; 2983 UINT mv_7_cost_segmant3:8; 2984 }; 2985 struct 2986 { 2987 UINT mv_cost_seg3; 2988 }; 2989 } dw78; 2990 // dw79 2991 struct 2992 { 2993 UINT new_mv_skip_threshold_segment0:16; 2994 UINT new_mv_skip_threshold_segment1:16; 2995 } dw79; 2996 2997 // dw80 2998 struct 2999 { 3000 UINT new_mv_skip_threshold_segment2:16; 3001 UINT new_mv_skip_threshold_segment3:16; 3002 } dw80; 3003 3004 // dw81 3005 struct 3006 { 3007 UINT per_mb_output_data_surface_bti:32; 3008 } dw81; 3009 3010 // dw82 3011 struct 3012 { 3013 UINT current_picture_y_surface_bti:32; 3014 } dw82; 3015 3016 // dw83 3017 struct 3018 { 3019 UINT current_picture_interleaved_uv_surface_bti:32; 3020 } dw83; 3021 3022 // dw84 3023 struct 3024 { 3025 UINT hme_mv_data_surface_bti:32; 3026 } dw84; 3027 3028 // dw85 3029 struct 3030 { 3031 UINT mv_data_surface_bti:32; 3032 } dw85; 3033 3034 // dw86 3035 struct 3036 { 3037 UINT mb_count_per_reference_frame_bti:32; 3038 } dw86; 3039 3040 // dw87 3041 struct 3042 { 3043 UINT vme_inter_prediction_bti:32; 3044 } dw87; 3045 3046 // dw88 3047 struct 3048 { 3049 UINT last_picture_bti:32; 3050 } dw88; 3051 // dw89 3052 struct 3053 { 3054 UINT gold_picture_bti:32; 3055 } dw89; 3056 3057 // dw90 3058 struct 3059 { 3060 UINT alternate_picture_bti:32; 3061 } dw90; 3062 3063 // dw91 3064 struct 3065 { 3066 UINT per_mb_quant_data_bti:32; 3067 } dw91; 3068 3069 // dw92 3070 struct 3071 { 3072 UINT segment_map_bti:32; 3073 } dw92; 3074 3075 // dw93 3076 struct 3077 { 3078 UINT inter_prediction_distortion_bti:32; 3079 } dw93; 3080 // dw94 3081 struct 3082 { 3083 UINT histogram_bti:32; 3084 } dw94; 3085 3086 // dw95 3087 struct 3088 { 3089 UINT pred_mv_data_bti:32; 3090 } dw95; 3091 3092 // dw96 3093 struct 3094 { 3095 UINT mode_cost_update_bti:32; 3096 } dw96; 3097 // dw97 3098 struct 3099 { 3100 UINT kernel_debug_dump_bti:32; 3101 } dw97; 3102 } MEDIA_CURBE_DATA_MBENC_P_G75; 3103 typedef struct surface_state_g7 3104 { 3105 /*union { */ 3106 struct 3107 { 3108 unsigned int cube_pos_z:1; 3109 unsigned int cube_neg_z:1; 3110 unsigned int cube_pos_y:1; 3111 unsigned int cube_neg_y:1; 3112 unsigned int cube_pos_x:1; 3113 unsigned int cube_neg_x:1; 3114 unsigned int media_boundry_pix_mode:2; 3115 unsigned int render_cache_read_write:1; 3116 unsigned int reserved0:1; 3117 unsigned int surface_array_spacing:1; 3118 unsigned int vert_line_stride_offset:1; 3119 unsigned int vert_line_stride:1; 3120 unsigned int tile_walk:1; 3121 unsigned int tiled_surface:1; 3122 unsigned int horizontal_alignment:1; 3123 unsigned int vertical_alignment:2; 3124 unsigned int surface_format:9; /**< BRW_SURFACEFORMAT_x */ 3125 unsigned int min_mag_state_not_eq:1; 3126 unsigned int surface_array:1; 3127 unsigned int surface_type:3; /**< BRW_SURFACE_1D/2D/3D/CUBE */ 3128 /*}; 3129 struct { 3130 unsigned int val; 3131 }; */ 3132 } dw0; 3133 /*union {*/ 3134 struct 3135 { 3136 unsigned int base_addr; 3137 /* }; 3138 struct { 3139 unsigned int val; 3140 };*/ 3141 } dw1; 3142 3143 /*union {*/ 3144 struct 3145 { 3146 unsigned int width:14; 3147 unsigned int:2; 3148 unsigned int height:14; 3149 unsigned int:2; 3150 /*}; 3151 struct { 3152 unsigned int val; 3153 };*/ 3154 } dw2; 3155 3156 /* union {*/ 3157 struct 3158 { 3159 unsigned int surface_pitch:18; 3160 unsigned int:3; 3161 unsigned int depth:11; 3162 /* }; 3163 struct { 3164 unsigned int val; 3165 }; 3166 */ 3167 } dw3; 3168 /*union {*/ 3169 struct 3170 { 3171 unsigned int multisample_position_palette_index:3; 3172 unsigned int num_multisamples:3; 3173 unsigned int multisampled_surface_storage_format:1; 3174 unsigned int render_target_view_extent:11; 3175 unsigned int min_array_elt:11; 3176 unsigned int rotation:2; 3177 unsigned int:1; 3178 /*}; 3179 struct { 3180 unsigned int val; 3181 }; 3182 */ 3183 } dw4; 3184 3185 /*union {*/ 3186 struct 3187 { 3188 unsigned int mip_count:4; 3189 unsigned int min_lod:4; 3190 unsigned int reserved0:8; 3191 unsigned int obj_ctrl_state:4; 3192 unsigned int y_offset:4; 3193 unsigned int pad0:1; 3194 unsigned int x_offset:7; 3195 /* }; 3196 struct { 3197 unsigned int val; 3198 };*/ 3199 } dw5; 3200 3201 /*union {*/ 3202 struct 3203 { 3204 /* Multisample ontrol surface stuff */ 3205 unsigned int mcs_enable:1; 3206 unsigned int:2; 3207 unsigned int mcs_surface_picth:9; 3208 unsigned int mcs_base_addr:20; 3209 /*}; 3210 struct 3211 { 3212 unsigned int val; 3213 };*/ 3214 } dw6; 3215 /*union {*/ 3216 struct 3217 { 3218 unsigned int resource_min_lod:12; 3219 unsigned int pad0:4; 3220 unsigned int shader_chanel_select_a:3; 3221 unsigned int shader_chanel_select_b:3; 3222 unsigned int shader_chanel_select_g:3; 3223 unsigned int shader_chanel_select_r:3; 3224 unsigned int alpha_clear_color:1; 3225 unsigned int blue_clear_color:1; 3226 unsigned int green_clear_color:1; 3227 unsigned int red_clear_color:1; 3228 /*}; 3229 struct 3230 { 3231 unsigned int val; 3232 };*/ 3233 } dw7; 3234 } SURFACE_STATE_G7; 3235 3236 3237 typedef struct _binding_table_state 3238 { 3239 //dw0 3240 struct 3241 { 3242 unsigned int enable:1; 3243 unsigned int copy:1; 3244 unsigned int binding_table_state_type:1; 3245 unsigned int:2; 3246 unsigned int surface_state_pointer:27; 3247 } dw0; 3248 3249 } BINDING_TABLE_STATE; 3250 3251 VOID media_add_binding_table (MEDIA_GPE_CTX * gpe_ctx); 3252 VOID media_interface_setup_mbenc (MEDIA_ENCODER_CTX * encoder_context); 3253 3254 typedef struct _media_curbe_data_brc_init_reset_g75 3255 { 3256 struct { 3257 UINT profile_level_max_frame; /* in bytes */ 3258 } dw0; 3259 3260 struct { 3261 UINT init_buf_full_in_bits; 3262 } dw1; 3263 3264 struct { 3265 UINT buf_size_in_bits; 3266 } dw2; 3267 3268 struct { 3269 UINT average_bit_rate; 3270 } dw3; 3271 3272 struct { 3273 UINT max_bit_rate; 3274 } dw4; 3275 3276 struct { 3277 UINT min_bit_rate; 3278 } dw5; 3279 3280 struct { 3281 UINT frame_rate_m; 3282 } dw6; 3283 3284 struct { 3285 UINT frame_rate_d; 3286 } dw7; 3287 3288 struct { 3289 UINT brc_flag:16; 3290 UINT number_pframes_in_gop:16; 3291 } dw8; 3292 3293 struct { 3294 UINT constant_0:16; 3295 UINT frame_width:16; /* in bytes */ 3296 } dw9; 3297 3298 struct { 3299 UINT frame_height:16; /* in bytes */ 3300 UINT avbr_accuracy:16; 3301 } dw10; 3302 3303 struct { 3304 UINT avbr_convergence:16; 3305 UINT min_qp:16; 3306 } dw11; 3307 3308 struct { 3309 UINT max_qp:16; 3310 UINT level_qp:16; 3311 } dw12; 3312 3313 struct { 3314 UINT max_section_pct:16; 3315 UINT under_shoot_cbr_pct:16; 3316 } dw13; 3317 3318 struct { 3319 UINT vbr_bias_pct:16; 3320 UINT min_section_pct:16; 3321 } dw14; 3322 3323 struct { 3324 UINT instant_rate_threshold0_pframe:8; 3325 UINT instant_rate_threshold1_pframe:8; 3326 UINT instant_rate_threshold2_pframe:8; 3327 UINT instant_rate_threshold3_pframe:8; 3328 } dw15; 3329 3330 struct { 3331 UINT constant_0:8; 3332 UINT constant_1:8; 3333 UINT constant_2:8; 3334 UINT constant_3:8; 3335 } dw16; 3336 3337 struct { 3338 UINT instant_rate_threshold0_iframe:8; 3339 UINT instant_rate_threshold1_iframe:8; 3340 UINT instant_rate_threshold2_iframe:8; 3341 UINT instant_rate_threshold3_iframe:8; 3342 } dw17; 3343 3344 struct { 3345 UINT deviation_threshold0_pframe:8; // signed byte 3346 UINT deviation_threshold1_pframe:8; // signed byte 3347 UINT deviation_threshold2_pframe:8; // signed byte 3348 UINT deviation_threshold3_pframe:8; // signed byte 3349 } dw18; 3350 3351 struct { 3352 UINT deviation_threshold4_pframe:8; // signed byte 3353 UINT deviation_threshold5_pframe:8; // signed byte 3354 UINT deviation_threshold6_pframe:8; // signed byte 3355 UINT deviation_threshold7_pframe:8; // signed byte 3356 } dw19; 3357 3358 struct { 3359 UINT deviation_threshold0_vbr:8; // signed byte 3360 UINT deviation_threshold1_vbr:8; // signed byte 3361 UINT deviation_threshold2_vbr:8; // signed byte 3362 UINT deviation_threshold3_vbr:8; // signed byte 3363 } dw20; 3364 3365 struct { 3366 UINT deviation_threshold4_vbr:8; // signed byte 3367 UINT deviation_threshold5_vbr:8; // signed byte 3368 UINT deviation_threshold6_vbr:8; // signed byte 3369 UINT deviation_threshold7_vbr:8; // signed byte 3370 } dw21; 3371 3372 struct { 3373 UINT deviation_threshold0_iframe:8; // signed byte 3374 UINT deviation_threshold1_iframe:8; // signed byte 3375 UINT deviation_threshold2_iframe:8; // signed byte 3376 UINT deviation_threshold3_iframe:8; // signed byte 3377 } dw22; 3378 3379 struct { 3380 UINT deviation_threshold4_iframe:8; // signed byte 3381 UINT deviation_threshold5_iframe:8; // signed byte 3382 UINT deviation_threshold6_iframe:8; // signed byte 3383 UINT deviation_threshold7_iframe:8; // signed byte 3384 } dw23; 3385 3386 struct { 3387 UINT initial_qp_iframe:8; 3388 UINT initial_qp_pframe:8; 3389 UINT pad0:8; 3390 UINT pad1:8; 3391 } dw24; 3392 3393 struct { 3394 UINT history_buffer_bti; 3395 } dw25; 3396 3397 struct { 3398 UINT distortion_buffer_bti; 3399 } dw26; 3400 } MEDIA_CURBE_DATA_BRC_INIT_RESET_G75; 3401 3402 typedef struct _media_curbe_data_brc_update_g75 3403 { 3404 struct { 3405 UINT target_size; 3406 } dw0; 3407 3408 struct { 3409 UINT frame_number; 3410 } dw1; 3411 3412 struct { 3413 UINT picture_header_size:32; 3414 } dw2; 3415 3416 struct { 3417 UINT start_global_adjust_frame0:16; 3418 UINT start_global_adjust_frame1:16; 3419 } dw3; 3420 3421 struct { 3422 UINT start_global_adjust_frame2:16; 3423 UINT start_global_adjust_frame3:16; 3424 } dw4; 3425 3426 struct { 3427 UINT target_size_flag:8; 3428 UINT brc_flag:8; 3429 UINT max_num_paks:8; 3430 UINT curr_frame_type:8; 3431 } dw5; 3432 3433 struct { 3434 UINT reserved0:32; 3435 } dw6; 3436 3437 struct { 3438 UINT reserved0:32; 3439 } dw7; 3440 3441 struct { 3442 UINT start_global_adjust_mult0:8; 3443 UINT start_global_adjust_mult1:8; 3444 UINT start_global_adjust_mult2:8; 3445 UINT start_global_adjust_mult3:8; 3446 } dw8; 3447 3448 struct { 3449 UINT start_global_adjust_mult4:8; 3450 UINT start_global_adjust_div0:8; 3451 UINT start_global_adjust_div1:8; 3452 UINT start_global_adjust_div2:8; 3453 } dw9; 3454 3455 struct { 3456 UINT start_global_adjust_div3:8; 3457 UINT start_global_adjust_div4:8; 3458 UINT qp_threshold0:8; 3459 UINT qp_threshold1:8; 3460 } dw10; 3461 3462 struct { 3463 UINT qp_threshold2:8; 3464 UINT qp_threshold3:8; 3465 UINT rate_ratio_threshold0:8; 3466 UINT rate_ratio_threshold1:8; 3467 } dw11; 3468 3469 struct { 3470 UINT rate_ratio_threshold2:8; 3471 UINT rate_ratio_threshold3:8; 3472 UINT rate_ratio_threshold4:8; 3473 UINT rate_ratio_threshold5:8; 3474 } dw12; 3475 3476 struct { 3477 UINT rate_ratio_threshold_qp0:8; 3478 UINT rate_ratio_threshold_qp1:8; 3479 UINT rate_ratio_threshold_qp2:8; 3480 UINT rate_ratio_threshold_qp3:8; 3481 } dw13; 3482 3483 struct { 3484 UINT rate_ratio_threshold_qp4:8; 3485 UINT rate_ratio_threshold_qp5:8; 3486 UINT rate_ratio_threshold_qp6:8; 3487 UINT index_of_previous_qp:8; 3488 } dw14; 3489 3490 struct { 3491 UINT frame_width_in_mb:8; 3492 UINT frame_height_in_mb:8; 3493 UINT prev_flag:8; 3494 UINT reserved:8; 3495 } dw15; 3496 3497 struct { 3498 UINT frame_byte_count:32; 3499 } dw16; 3500 3501 struct { 3502 UINT key_frame_qp_seg0:8; 3503 UINT key_frame_qp_seg1:8; 3504 UINT key_frame_qp_seg2:8; 3505 UINT key_frame_qp_seg3:8; 3506 } dw17; 3507 3508 struct { 3509 UINT qp_delta_plane0:8; 3510 UINT qp_delta_plane1:8; 3511 UINT qp_delta_plane2:8; 3512 UINT qp_delta_plane3:8; 3513 } dw18; 3514 3515 struct { 3516 UINT qp_delta_plane4:8; 3517 UINT qp:8; 3518 UINT reserved:16; 3519 } dw19; 3520 3521 struct { 3522 UINT segmentation_enabled:8; 3523 UINT mb_rc:8; 3524 UINT brc_method:8; 3525 UINT vme_intraprediction:8; 3526 } dw20; 3527 3528 struct { 3529 UINT history_buffer_index; 3530 } dw21; 3531 3532 struct { 3533 UINT pak_surface_index; 3534 } dw22; 3535 3536 struct { 3537 UINT mbpak_curbe1_index; 3538 } dw23; 3539 3540 struct { 3541 UINT mbpak_curbe2_index; 3542 } dw24; 3543 3544 struct { 3545 UINT mbenc_curbe_input_index; 3546 } dw25; 3547 3548 struct { 3549 UINT mbenc_curbe_output_index; 3550 } dw26; 3551 3552 struct { 3553 UINT distortion_input_index; 3554 } dw27; 3555 3556 struct { 3557 UINT constant_data_input_index; 3558 } dw28; 3559 3560 struct { 3561 UINT pak_table_surface_index; 3562 } dw29; 3563 3564 struct { 3565 UINT reserved; 3566 } dw30; 3567 3568 struct { 3569 UINT reserved; 3570 } dw31; 3571 3572 struct { 3573 UINT reserved; 3574 } dw32; 3575 3576 struct { 3577 UINT reserved; 3578 } dw33; 3579 } MEDIA_CURBE_DATA_BRC_UPDATE_G75; 3580 3581 void media_interface_setup_mbpak (MEDIA_GPE_CTX *mbpak_gpe_ctx); 3582 void 3583 media_surface_state_vp8_mbpak (MEDIA_ENCODER_CTX * encoder_context, 3584 struct encode_state *encode_state, 3585 MBPAK_SURFACE_PARAMS_VP8 * 3586 mbpak_sutface_params); 3587 void 3588 media_surface_state_vp8_mbenc (MEDIA_ENCODER_CTX * encoder_context, 3589 struct encode_state *encode_state, 3590 MBENC_SURFACE_PARAMS_VP8 * 3591 mbenc_sutface_params); 3592 void 3593 media_set_curbe_i_vp8_mbenc (struct encode_state *encode_state, 3594 MEDIA_MBENC_CURBE_PARAMS_VP8 * params); 3595 void media_set_curbe_p_vp8_mbenc (struct encode_state *encode_state, 3596 MEDIA_MBENC_CURBE_PARAMS_VP8 * params); 3597 void media_set_curbe_vp8_me (VP8_ME_CURBE_PARAMS * params); 3598 void 3599 media_surface_state_vp8_me (MEDIA_ENCODER_CTX * encoder_context, 3600 struct encode_state *encode_state, 3601 ME_SURFACE_PARAMS_VP8 * me_sutface_params); 3602 void media_set_curbe_vp8_mbpak (struct encode_state *encode_state, 3603 MEDIA_MBPAK_CURBE_PARAMS_VP8 * params); 3604 void media_surface_state_scaling (MEDIA_ENCODER_CTX * encoder_context, 3605 SCALING_SURFACE_PARAMS * 3606 scaling_sutface_params); 3607 void 3608 media_encode_init_mbenc_constant_buffer_vp8_g75 3609 (MBENC_CONSTANT_BUFFER_PARAMS_VP8 * params); 3610 3611 void 3612 media_set_curbe_vp8_brc_init_reset(struct encode_state *encode_state, 3613 MEDIA_BRC_INIT_RESET_PARAMS_VP8 * params); 3614 VOID 3615 media_interface_setup_brc_init_reset (MEDIA_ENCODER_CTX * encoder_context); 3616 3617 VOID 3618 media_surface_state_vp8_brc_init_reset (MEDIA_ENCODER_CTX * encoder_context, 3619 struct encode_state *encode_state, 3620 BRC_INIT_RESET_SURFACE_PARAMS_VP8 *surface_params); 3621 3622 VOID 3623 media_interface_setup_brc_update (MEDIA_ENCODER_CTX * encoder_context); 3624 3625 VOID 3626 media_surface_state_vp8_brc_update (MEDIA_ENCODER_CTX * encoder_context, 3627 struct encode_state *encode_state, 3628 BRC_UPDATE_SURFACE_PARAMS_VP8 *surface_params); 3629 3630 VOID 3631 media_set_curbe_vp8_brc_update(struct encode_state *encode_state, 3632 MEDIA_BRC_UPDATE_PARAMS_VP8 * params); 3633 3634 VOID 3635 media_encode_init_brc_update_constant_data_vp8_g75(BRC_UPDATE_CONSTANT_DATA_PARAMS_VP8 *params); 3636 3637 VOID 3638 media_add_surface_state (SURFACE_SET_PARAMS * params); 3639 3640 VOID 3641 media_interface_setup_scaling (MEDIA_ENCODER_CTX * encoder_context); 3642 3643 VOID 3644 media_interface_setup_me (MEDIA_ENCODER_CTX * encoder_context); 3645 3646 VOID 3647 media_hw_context_init_g75(VADriverContextP ctx, MEDIA_HW_CONTEXT *hw_ctx); 3648 3649 VOID 3650 media_init_brc_distortion_buffer_g75 (MEDIA_ENCODER_CTX * encoder_context); 3651 3652 #endif 3653