1 /*-
2 * Copyright (c) 1992 Terrence R. Lambert.
3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
4 * Copyright (c) 1997 KATO Takenori.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to Berkeley by
8 * William Jolitz.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by the University of
21 * California, Berkeley and its contributors.
22 * 4. Neither the name of the University nor the names of its contributors
23 * may be used to endorse or promote products derived from this software
24 * without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * SUCH DAMAGE.
37 *
38 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
39 */
40
41 #include <sys/cdefs.h>
42 #include "opt_cpu.h"
43
44 #include <sys/param.h>
45 #include <sys/bus.h>
46 #include <sys/cpu.h>
47 #include <sys/eventhandler.h>
48 #include <sys/limits.h>
49 #include <sys/systm.h>
50 #include <sys/kernel.h>
51 #include <sys/sysctl.h>
52 #include <sys/power.h>
53
54 #include <vm/vm.h>
55 #include <vm/pmap.h>
56
57 #include <machine/asmacros.h>
58 #include <machine/clock.h>
59 #include <machine/cputypes.h>
60 #include <machine/frame.h>
61 #include <machine/intr_machdep.h>
62 #include <machine/md_var.h>
63 #include <machine/segments.h>
64 #include <machine/specialreg.h>
65
66 #include <amd64/vmm/intel/vmx_controls.h>
67 #include <x86/isa/icu.h>
68 #include <x86/vmware.h>
69
70 #ifdef XENHVM
71 #include <xen/xen-os.h>
72 #endif
73
74 #ifdef __i386__
75 #define IDENTBLUE_CYRIX486 0
76 #define IDENTBLUE_IBMCPU 1
77 #define IDENTBLUE_CYRIXM2 2
78
79 static void identifycyrix(void);
80 static void print_transmeta_info(void);
81 #endif
82 static u_int find_cpu_vendor_id(void);
83 static void print_AMD_info(void);
84 static void print_INTEL_info(void);
85 static void print_INTEL_TLB(u_int data);
86 static void print_hypervisor_info(void);
87 static void print_svm_info(void);
88 static void print_via_padlock_info(void);
89 static void print_vmx_info(void);
90
91 #ifdef __i386__
92 int cpu; /* Are we 386, 386sx, 486, etc? */
93 int cpu_class;
94 #endif
95 u_int cpu_feature; /* Feature flags */
96 u_int cpu_feature2; /* Feature flags */
97 u_int amd_feature; /* AMD feature flags */
98 u_int amd_feature2; /* AMD feature flags */
99 u_int amd_rascap; /* AMD RAS capabilities */
100 u_int amd_pminfo; /* AMD advanced power management info */
101 u_int amd_extended_feature_extensions;
102 u_int via_feature_rng; /* VIA RNG features */
103 u_int via_feature_xcrypt; /* VIA ACE features */
104 u_int cpu_high; /* Highest arg to CPUID */
105 u_int cpu_exthigh; /* Highest arg to extended CPUID */
106 u_int cpu_id; /* Stepping ID */
107 u_int cpu_procinfo; /* HyperThreading Info / Brand Index / CLFUSH */
108 u_int cpu_procinfo2; /* Multicore info */
109 u_int cpu_procinfo3;
110 char cpu_vendor[20]; /* CPU Origin code */
111 u_int cpu_vendor_id; /* CPU vendor ID */
112 u_int cpu_mxcsr_mask; /* Valid bits in mxcsr */
113 u_int cpu_clflush_line_size = 32;
114 u_int cpu_stdext_feature; /* %ebx */
115 u_int cpu_stdext_feature2; /* %ecx */
116 u_int cpu_stdext_feature3; /* %edx */
117 uint64_t cpu_ia32_arch_caps;
118 u_int cpu_max_ext_state_size;
119 u_int cpu_mon_mwait_flags; /* MONITOR/MWAIT flags (CPUID.05H.ECX) */
120 u_int cpu_mon_min_size; /* MONITOR minimum range size, bytes */
121 u_int cpu_mon_max_size; /* MONITOR minimum range size, bytes */
122 u_int cpu_maxphyaddr; /* Max phys addr width in bits */
123 u_int cpu_power_eax; /* 06H: Power management leaf, %eax */
124 u_int cpu_power_ebx; /* 06H: Power management leaf, %ebx */
125 u_int cpu_power_ecx; /* 06H: Power management leaf, %ecx */
126 u_int cpu_power_edx; /* 06H: Power management leaf, %edx */
127 const char machine[] = MACHINE;
128
129 SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD,
130 &via_feature_rng, 0,
131 "VIA RNG feature available in CPU");
132 SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD,
133 &via_feature_xcrypt, 0,
134 "VIA xcrypt feature available in CPU");
135
136 #ifdef __amd64__
137 #ifdef SCTL_MASK32
138 extern int adaptive_machine_arch;
139 #endif
140
141 static int
sysctl_hw_machine(SYSCTL_HANDLER_ARGS)142 sysctl_hw_machine(SYSCTL_HANDLER_ARGS)
143 {
144 #ifdef SCTL_MASK32
145 static const char machine32[] = "i386";
146 #endif
147 int error;
148
149 #ifdef SCTL_MASK32
150 if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch)
151 error = SYSCTL_OUT(req, machine32, sizeof(machine32));
152 else
153 #endif
154 error = SYSCTL_OUT(req, machine, sizeof(machine));
155 return (error);
156
157 }
158 SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD |
159 CTLFLAG_CAPRD | CTLFLAG_MPSAFE, NULL, 0, sysctl_hw_machine, "A", "Machine class");
160 #else
161 SYSCTL_CONST_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD | CTLFLAG_CAPRD,
162 machine, "Machine class");
163 #endif
164
165 char cpu_model[128];
166 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD | CTLFLAG_CAPRD,
167 cpu_model, 0, "Machine model");
168
169 static int hw_clockrate;
170 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
171 &hw_clockrate, 0, "CPU instruction clock rate");
172
173 u_int hv_base;
174 u_int hv_high;
175 char hv_vendor[16];
176 SYSCTL_STRING(_hw, OID_AUTO, hv_vendor, CTLFLAG_RD, hv_vendor,
177 0, "Hypervisor vendor");
178
179 static eventhandler_tag tsc_post_tag;
180
181 static char cpu_brand[48];
182
183 #ifdef __i386__
184 #define MAX_BRAND_INDEX 8
185
186 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
187 NULL, /* No brand */
188 "Intel Celeron",
189 "Intel Pentium III",
190 "Intel Pentium III Xeon",
191 NULL,
192 NULL,
193 NULL,
194 NULL,
195 "Intel Pentium 4"
196 };
197
198 static struct {
199 char *cpu_name;
200 int cpu_class;
201 } cpus[] = {
202 { "Intel 80286", CPUCLASS_286 }, /* CPU_286 */
203 { "i386SX", CPUCLASS_386 }, /* CPU_386SX */
204 { "i386DX", CPUCLASS_386 }, /* CPU_386 */
205 { "i486SX", CPUCLASS_486 }, /* CPU_486SX */
206 { "i486DX", CPUCLASS_486 }, /* CPU_486 */
207 { "Pentium", CPUCLASS_586 }, /* CPU_586 */
208 { "Cyrix 486", CPUCLASS_486 }, /* CPU_486DLC */
209 { "Pentium Pro", CPUCLASS_686 }, /* CPU_686 */
210 { "Cyrix 5x86", CPUCLASS_486 }, /* CPU_M1SC */
211 { "Cyrix 6x86", CPUCLASS_486 }, /* CPU_M1 */
212 { "Blue Lightning", CPUCLASS_486 }, /* CPU_BLUE */
213 { "Cyrix 6x86MX", CPUCLASS_686 }, /* CPU_M2 */
214 { "NexGen 586", CPUCLASS_386 }, /* CPU_NX586 (XXX) */
215 { "Cyrix 486S/DX", CPUCLASS_486 }, /* CPU_CY486DX */
216 { "Pentium II", CPUCLASS_686 }, /* CPU_PII */
217 { "Pentium III", CPUCLASS_686 }, /* CPU_PIII */
218 { "Pentium 4", CPUCLASS_686 }, /* CPU_P4 */
219 };
220 #endif
221
222 static struct {
223 char *vendor;
224 u_int vendor_id;
225 } cpu_vendors[] = {
226 { INTEL_VENDOR_ID, CPU_VENDOR_INTEL }, /* GenuineIntel */
227 { AMD_VENDOR_ID, CPU_VENDOR_AMD }, /* AuthenticAMD */
228 { HYGON_VENDOR_ID, CPU_VENDOR_HYGON }, /* HygonGenuine */
229 { CENTAUR_VENDOR_ID, CPU_VENDOR_CENTAUR }, /* CentaurHauls */
230 #ifdef __i386__
231 { NSC_VENDOR_ID, CPU_VENDOR_NSC }, /* Geode by NSC */
232 { CYRIX_VENDOR_ID, CPU_VENDOR_CYRIX }, /* CyrixInstead */
233 { TRANSMETA_VENDOR_ID, CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */
234 { SIS_VENDOR_ID, CPU_VENDOR_SIS }, /* SiS SiS SiS */
235 { UMC_VENDOR_ID, CPU_VENDOR_UMC }, /* UMC UMC UMC */
236 { NEXGEN_VENDOR_ID, CPU_VENDOR_NEXGEN }, /* NexGenDriven */
237 { RISE_VENDOR_ID, CPU_VENDOR_RISE }, /* RiseRiseRise */
238 #if 0
239 /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */
240 { "TransmetaCPU", CPU_VENDOR_TRANSMETA },
241 #endif
242 #endif
243 };
244
245 void
printcpuinfo(void)246 printcpuinfo(void)
247 {
248 u_int regs[4], i;
249 char *brand;
250
251 printf("CPU: ");
252 #ifdef __i386__
253 cpu_class = cpus[cpu].cpu_class;
254 strncpy(cpu_model, cpus[cpu].cpu_name, sizeof (cpu_model));
255 #else
256 strncpy(cpu_model, "Hammer", sizeof (cpu_model));
257 #endif
258
259 /* Check for extended CPUID information and a processor name. */
260 if (cpu_exthigh >= 0x80000004) {
261 brand = cpu_brand;
262 for (i = 0x80000002; i < 0x80000005; i++) {
263 do_cpuid(i, regs);
264 memcpy(brand, regs, sizeof(regs));
265 brand += sizeof(regs);
266 }
267 }
268
269 switch (cpu_vendor_id) {
270 case CPU_VENDOR_INTEL:
271 #ifdef __i386__
272 if ((cpu_id & 0xf00) > 0x300) {
273 u_int brand_index;
274
275 cpu_model[0] = '\0';
276
277 switch (cpu_id & 0x3000) {
278 case 0x1000:
279 strcpy(cpu_model, "Overdrive ");
280 break;
281 case 0x2000:
282 strcpy(cpu_model, "Dual ");
283 break;
284 }
285
286 switch (cpu_id & 0xf00) {
287 case 0x400:
288 strcat(cpu_model, "i486 ");
289 /* Check the particular flavor of 486 */
290 switch (cpu_id & 0xf0) {
291 case 0x00:
292 case 0x10:
293 strcat(cpu_model, "DX");
294 break;
295 case 0x20:
296 strcat(cpu_model, "SX");
297 break;
298 case 0x30:
299 strcat(cpu_model, "DX2");
300 break;
301 case 0x40:
302 strcat(cpu_model, "SL");
303 break;
304 case 0x50:
305 strcat(cpu_model, "SX2");
306 break;
307 case 0x70:
308 strcat(cpu_model,
309 "DX2 Write-Back Enhanced");
310 break;
311 case 0x80:
312 strcat(cpu_model, "DX4");
313 break;
314 }
315 break;
316 case 0x500:
317 /* Check the particular flavor of 586 */
318 strcat(cpu_model, "Pentium");
319 switch (cpu_id & 0xf0) {
320 case 0x00:
321 strcat(cpu_model, " A-step");
322 break;
323 case 0x10:
324 strcat(cpu_model, "/P5");
325 break;
326 case 0x20:
327 strcat(cpu_model, "/P54C");
328 break;
329 case 0x30:
330 strcat(cpu_model, "/P24T");
331 break;
332 case 0x40:
333 strcat(cpu_model, "/P55C");
334 break;
335 case 0x70:
336 strcat(cpu_model, "/P54C");
337 break;
338 case 0x80:
339 strcat(cpu_model, "/P55C (quarter-micron)");
340 break;
341 default:
342 /* nothing */
343 break;
344 }
345 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
346 /*
347 * XXX - If/when Intel fixes the bug, this
348 * should also check the version of the
349 * CPU, not just that it's a Pentium.
350 */
351 has_f00f_bug = 1;
352 #endif
353 break;
354 case 0x600:
355 /* Check the particular flavor of 686 */
356 switch (cpu_id & 0xf0) {
357 case 0x00:
358 strcat(cpu_model, "Pentium Pro A-step");
359 break;
360 case 0x10:
361 strcat(cpu_model, "Pentium Pro");
362 break;
363 case 0x30:
364 case 0x50:
365 case 0x60:
366 strcat(cpu_model,
367 "Pentium II/Pentium II Xeon/Celeron");
368 cpu = CPU_PII;
369 break;
370 case 0x70:
371 case 0x80:
372 case 0xa0:
373 case 0xb0:
374 strcat(cpu_model,
375 "Pentium III/Pentium III Xeon/Celeron");
376 cpu = CPU_PIII;
377 break;
378 default:
379 strcat(cpu_model, "Unknown 80686");
380 break;
381 }
382 break;
383 case 0xf00:
384 strcat(cpu_model, "Pentium 4");
385 cpu = CPU_P4;
386 break;
387 default:
388 strcat(cpu_model, "unknown");
389 break;
390 }
391
392 /*
393 * If we didn't get a brand name from the extended
394 * CPUID, try to look it up in the brand table.
395 */
396 if (cpu_high > 0 && *cpu_brand == '\0') {
397 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
398 if (brand_index <= MAX_BRAND_INDEX &&
399 cpu_brandtable[brand_index] != NULL)
400 strcpy(cpu_brand,
401 cpu_brandtable[brand_index]);
402 }
403 }
404 #else
405 /* Please make up your mind folks! */
406 strcat(cpu_model, "EM64T");
407 #endif
408 break;
409 case CPU_VENDOR_AMD:
410 /*
411 * Values taken from AMD Processor Recognition
412 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
413 * (also describes ``Features'' encodings.
414 */
415 strcpy(cpu_model, "AMD ");
416 #ifdef __i386__
417 switch (cpu_id & 0xFF0) {
418 case 0x410:
419 strcat(cpu_model, "Standard Am486DX");
420 break;
421 case 0x430:
422 strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
423 break;
424 case 0x470:
425 strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
426 break;
427 case 0x480:
428 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
429 break;
430 case 0x490:
431 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
432 break;
433 case 0x4E0:
434 strcat(cpu_model, "Am5x86 Write-Through");
435 break;
436 case 0x4F0:
437 strcat(cpu_model, "Am5x86 Write-Back");
438 break;
439 case 0x500:
440 strcat(cpu_model, "K5 model 0");
441 break;
442 case 0x510:
443 strcat(cpu_model, "K5 model 1");
444 break;
445 case 0x520:
446 strcat(cpu_model, "K5 PR166 (model 2)");
447 break;
448 case 0x530:
449 strcat(cpu_model, "K5 PR200 (model 3)");
450 break;
451 case 0x560:
452 strcat(cpu_model, "K6");
453 break;
454 case 0x570:
455 strcat(cpu_model, "K6 266 (model 1)");
456 break;
457 case 0x580:
458 strcat(cpu_model, "K6-2");
459 break;
460 case 0x590:
461 strcat(cpu_model, "K6-III");
462 break;
463 case 0x5a0:
464 strcat(cpu_model, "Geode LX");
465 break;
466 default:
467 strcat(cpu_model, "Unknown");
468 break;
469 }
470 #else
471 if ((cpu_id & 0xf00) == 0xf00)
472 strcat(cpu_model, "AMD64 Processor");
473 else
474 strcat(cpu_model, "Unknown");
475 #endif
476 break;
477 #ifdef __i386__
478 case CPU_VENDOR_CYRIX:
479 strcpy(cpu_model, "Cyrix ");
480 switch (cpu_id & 0xff0) {
481 case 0x440:
482 strcat(cpu_model, "MediaGX");
483 break;
484 case 0x520:
485 strcat(cpu_model, "6x86");
486 break;
487 case 0x540:
488 cpu_class = CPUCLASS_586;
489 strcat(cpu_model, "GXm");
490 break;
491 case 0x600:
492 strcat(cpu_model, "6x86MX");
493 break;
494 default:
495 /*
496 * Even though CPU supports the cpuid
497 * instruction, it can be disabled.
498 * Therefore, this routine supports all Cyrix
499 * CPUs.
500 */
501 switch (cyrix_did & 0xf0) {
502 case 0x00:
503 switch (cyrix_did & 0x0f) {
504 case 0x00:
505 strcat(cpu_model, "486SLC");
506 break;
507 case 0x01:
508 strcat(cpu_model, "486DLC");
509 break;
510 case 0x02:
511 strcat(cpu_model, "486SLC2");
512 break;
513 case 0x03:
514 strcat(cpu_model, "486DLC2");
515 break;
516 case 0x04:
517 strcat(cpu_model, "486SRx");
518 break;
519 case 0x05:
520 strcat(cpu_model, "486DRx");
521 break;
522 case 0x06:
523 strcat(cpu_model, "486SRx2");
524 break;
525 case 0x07:
526 strcat(cpu_model, "486DRx2");
527 break;
528 case 0x08:
529 strcat(cpu_model, "486SRu");
530 break;
531 case 0x09:
532 strcat(cpu_model, "486DRu");
533 break;
534 case 0x0a:
535 strcat(cpu_model, "486SRu2");
536 break;
537 case 0x0b:
538 strcat(cpu_model, "486DRu2");
539 break;
540 default:
541 strcat(cpu_model, "Unknown");
542 break;
543 }
544 break;
545 case 0x10:
546 switch (cyrix_did & 0x0f) {
547 case 0x00:
548 strcat(cpu_model, "486S");
549 break;
550 case 0x01:
551 strcat(cpu_model, "486S2");
552 break;
553 case 0x02:
554 strcat(cpu_model, "486Se");
555 break;
556 case 0x03:
557 strcat(cpu_model, "486S2e");
558 break;
559 case 0x0a:
560 strcat(cpu_model, "486DX");
561 break;
562 case 0x0b:
563 strcat(cpu_model, "486DX2");
564 break;
565 case 0x0f:
566 strcat(cpu_model, "486DX4");
567 break;
568 default:
569 strcat(cpu_model, "Unknown");
570 break;
571 }
572 break;
573 case 0x20:
574 if ((cyrix_did & 0x0f) < 8)
575 strcat(cpu_model, "6x86"); /* Where did you get it? */
576 else
577 strcat(cpu_model, "5x86");
578 break;
579 case 0x30:
580 strcat(cpu_model, "6x86");
581 break;
582 case 0x40:
583 if ((cyrix_did & 0xf000) == 0x3000) {
584 cpu_class = CPUCLASS_586;
585 strcat(cpu_model, "GXm");
586 } else
587 strcat(cpu_model, "MediaGX");
588 break;
589 case 0x50:
590 strcat(cpu_model, "6x86MX");
591 break;
592 case 0xf0:
593 switch (cyrix_did & 0x0f) {
594 case 0x0d:
595 strcat(cpu_model, "Overdrive CPU");
596 break;
597 case 0x0e:
598 strcpy(cpu_model, "Texas Instruments 486SXL");
599 break;
600 case 0x0f:
601 strcat(cpu_model, "486SLC/DLC");
602 break;
603 default:
604 strcat(cpu_model, "Unknown");
605 break;
606 }
607 break;
608 default:
609 strcat(cpu_model, "Unknown");
610 break;
611 }
612 break;
613 }
614 break;
615 case CPU_VENDOR_RISE:
616 strcpy(cpu_model, "Rise ");
617 switch (cpu_id & 0xff0) {
618 case 0x500: /* 6401 and 6441 (Kirin) */
619 case 0x520: /* 6510 (Lynx) */
620 strcat(cpu_model, "mP6");
621 break;
622 default:
623 strcat(cpu_model, "Unknown");
624 }
625 break;
626 #endif
627 case CPU_VENDOR_CENTAUR:
628 #ifdef __i386__
629 switch (cpu_id & 0xff0) {
630 case 0x540:
631 strcpy(cpu_model, "IDT WinChip C6");
632 break;
633 case 0x580:
634 strcpy(cpu_model, "IDT WinChip 2");
635 break;
636 case 0x590:
637 strcpy(cpu_model, "IDT WinChip 3");
638 break;
639 case 0x660:
640 strcpy(cpu_model, "VIA C3 Samuel");
641 break;
642 case 0x670:
643 if (cpu_id & 0x8)
644 strcpy(cpu_model, "VIA C3 Ezra");
645 else
646 strcpy(cpu_model, "VIA C3 Samuel 2");
647 break;
648 case 0x680:
649 strcpy(cpu_model, "VIA C3 Ezra-T");
650 break;
651 case 0x690:
652 strcpy(cpu_model, "VIA C3 Nehemiah");
653 break;
654 case 0x6a0:
655 case 0x6d0:
656 strcpy(cpu_model, "VIA C7 Esther");
657 break;
658 case 0x6f0:
659 strcpy(cpu_model, "VIA Nano");
660 break;
661 default:
662 strcpy(cpu_model, "VIA/IDT Unknown");
663 }
664 #else
665 strcpy(cpu_model, "VIA ");
666 if ((cpu_id & 0xff0) == 0x6f0)
667 strcat(cpu_model, "Nano Processor");
668 else
669 strcat(cpu_model, "Unknown");
670 #endif
671 break;
672 #ifdef __i386__
673 case CPU_VENDOR_IBM:
674 strcpy(cpu_model, "Blue Lightning CPU");
675 break;
676 case CPU_VENDOR_NSC:
677 switch (cpu_id & 0xff0) {
678 case 0x540:
679 strcpy(cpu_model, "Geode SC1100");
680 cpu = CPU_GEODE1100;
681 break;
682 default:
683 strcpy(cpu_model, "Geode/NSC unknown");
684 break;
685 }
686 break;
687 #endif
688 case CPU_VENDOR_HYGON:
689 strcpy(cpu_model, "Hygon ");
690 #ifdef __i386__
691 strcat(cpu_model, "Unknown");
692 #else
693 if ((cpu_id & 0xf00) == 0xf00)
694 strcat(cpu_model, "AMD64 Processor");
695 else
696 strcat(cpu_model, "Unknown");
697 #endif
698 break;
699
700 default:
701 strcat(cpu_model, "Unknown");
702 break;
703 }
704
705 /*
706 * Replace cpu_model with cpu_brand minus leading spaces if
707 * we have one.
708 */
709 brand = cpu_brand;
710 while (*brand == ' ')
711 ++brand;
712 if (*brand != '\0')
713 strcpy(cpu_model, brand);
714
715 printf("%s (", cpu_model);
716 if (tsc_freq != 0) {
717 hw_clockrate = (tsc_freq + 5000) / 1000000;
718 printf("%jd.%02d-MHz ",
719 (intmax_t)(tsc_freq + 4999) / 1000000,
720 (u_int)((tsc_freq + 4999) / 10000) % 100);
721 }
722 #ifdef __i386__
723 switch(cpu_class) {
724 case CPUCLASS_286:
725 printf("286");
726 break;
727 case CPUCLASS_386:
728 printf("386");
729 break;
730 #if defined(I486_CPU)
731 case CPUCLASS_486:
732 printf("486");
733 break;
734 #endif
735 #if defined(I586_CPU)
736 case CPUCLASS_586:
737 printf("586");
738 break;
739 #endif
740 #if defined(I686_CPU)
741 case CPUCLASS_686:
742 printf("686");
743 break;
744 #endif
745 default:
746 printf("Unknown"); /* will panic below... */
747 }
748 #else
749 printf("K8");
750 #endif
751 printf("-class CPU)\n");
752 if (*cpu_vendor)
753 printf(" Origin=\"%s\"", cpu_vendor);
754 if (cpu_id)
755 printf(" Id=0x%x", cpu_id);
756
757 if (cpu_vendor_id == CPU_VENDOR_INTEL ||
758 cpu_vendor_id == CPU_VENDOR_AMD ||
759 cpu_vendor_id == CPU_VENDOR_HYGON ||
760 cpu_vendor_id == CPU_VENDOR_CENTAUR ||
761 #ifdef __i386__
762 cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
763 cpu_vendor_id == CPU_VENDOR_RISE ||
764 cpu_vendor_id == CPU_VENDOR_NSC ||
765 (cpu_vendor_id == CPU_VENDOR_CYRIX && ((cpu_id & 0xf00) > 0x500)) ||
766 #endif
767 0) {
768 printf(" Family=0x%x", CPUID_TO_FAMILY(cpu_id));
769 printf(" Model=0x%x", CPUID_TO_MODEL(cpu_id));
770 printf(" Stepping=%u", cpu_id & CPUID_STEPPING);
771 #ifdef __i386__
772 if (cpu_vendor_id == CPU_VENDOR_CYRIX)
773 printf("\n DIR=0x%04x", cyrix_did);
774 #endif
775
776 /*
777 * AMD CPUID Specification
778 * http://support.amd.com/us/Embedded_TechDocs/25481.pdf
779 *
780 * Intel Processor Identification and CPUID Instruction
781 * http://www.intel.com/assets/pdf/appnote/241618.pdf
782 */
783 if (cpu_high > 0) {
784 /*
785 * Here we should probably set up flags indicating
786 * whether or not various features are available.
787 * The interesting ones are probably VME, PSE, PAE,
788 * and PGE. The code already assumes without bothering
789 * to check that all CPUs >= Pentium have a TSC and
790 * MSRs.
791 */
792 printf("\n Features=0x%b", cpu_feature,
793 "\020"
794 "\001FPU" /* Integral FPU */
795 "\002VME" /* Extended VM86 mode support */
796 "\003DE" /* Debugging Extensions (CR4.DE) */
797 "\004PSE" /* 4MByte page tables */
798 "\005TSC" /* Timestamp counter */
799 "\006MSR" /* Machine specific registers */
800 "\007PAE" /* Physical address extension */
801 "\010MCE" /* Machine Check support */
802 "\011CX8" /* CMPEXCH8 instruction */
803 "\012APIC" /* SMP local APIC */
804 "\013oldMTRR" /* Previous implementation of MTRR */
805 "\014SEP" /* Fast System Call */
806 "\015MTRR" /* Memory Type Range Registers */
807 "\016PGE" /* PG_G (global bit) support */
808 "\017MCA" /* Machine Check Architecture */
809 "\020CMOV" /* CMOV instruction */
810 "\021PAT" /* Page attributes table */
811 "\022PSE36" /* 36 bit address space support */
812 "\023PN" /* Processor Serial number */
813 "\024CLFLUSH" /* Has the CLFLUSH instruction */
814 "\025<b20>"
815 "\026DTS" /* Debug Trace Store */
816 "\027ACPI" /* ACPI support */
817 "\030MMX" /* MMX instructions */
818 "\031FXSR" /* FXSAVE/FXRSTOR */
819 "\032SSE" /* Streaming SIMD Extensions */
820 "\033SSE2" /* Streaming SIMD Extensions #2 */
821 "\034SS" /* Self snoop */
822 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */
823 "\036TM" /* Thermal Monitor clock slowdown */
824 "\037IA64" /* CPU can execute IA64 instructions */
825 "\040PBE" /* Pending Break Enable */
826 );
827
828 if (cpu_feature2 != 0) {
829 printf("\n Features2=0x%b", cpu_feature2,
830 "\020"
831 "\001SSE3" /* SSE3 */
832 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */
833 "\003DTES64" /* 64-bit Debug Trace */
834 "\004MON" /* MONITOR/MWAIT Instructions */
835 "\005DS_CPL" /* CPL Qualified Debug Store */
836 "\006VMX" /* Virtual Machine Extensions */
837 "\007SMX" /* Safer Mode Extensions */
838 "\010EST" /* Enhanced SpeedStep */
839 "\011TM2" /* Thermal Monitor 2 */
840 "\012SSSE3" /* SSSE3 */
841 "\013CNXT-ID" /* L1 context ID available */
842 "\014SDBG" /* IA32 silicon debug */
843 "\015FMA" /* Fused Multiply Add */
844 "\016CX16" /* CMPXCHG16B Instruction */
845 "\017xTPR" /* Send Task Priority Messages*/
846 "\020PDCM" /* Perf/Debug Capability MSR */
847 "\021<b16>"
848 "\022PCID" /* Process-context Identifiers*/
849 "\023DCA" /* Direct Cache Access */
850 "\024SSE4.1" /* SSE 4.1 */
851 "\025SSE4.2" /* SSE 4.2 */
852 "\026x2APIC" /* xAPIC Extensions */
853 "\027MOVBE" /* MOVBE Instruction */
854 "\030POPCNT" /* POPCNT Instruction */
855 "\031TSCDLT" /* TSC-Deadline Timer */
856 "\032AESNI" /* AES Crypto */
857 "\033XSAVE" /* XSAVE/XRSTOR States */
858 "\034OSXSAVE" /* OS-Enabled State Management*/
859 "\035AVX" /* Advanced Vector Extensions */
860 "\036F16C" /* Half-precision conversions */
861 "\037RDRAND" /* RDRAND Instruction */
862 "\040HV" /* Hypervisor */
863 );
864 }
865
866 if (amd_feature != 0) {
867 printf("\n AMD Features=0x%b", amd_feature,
868 "\020" /* in hex */
869 "\001<s0>" /* Same */
870 "\002<s1>" /* Same */
871 "\003<s2>" /* Same */
872 "\004<s3>" /* Same */
873 "\005<s4>" /* Same */
874 "\006<s5>" /* Same */
875 "\007<s6>" /* Same */
876 "\010<s7>" /* Same */
877 "\011<s8>" /* Same */
878 "\012<s9>" /* Same */
879 "\013<b10>" /* Undefined */
880 "\014SYSCALL" /* Have SYSCALL/SYSRET */
881 "\015<s12>" /* Same */
882 "\016<s13>" /* Same */
883 "\017<s14>" /* Same */
884 "\020<s15>" /* Same */
885 "\021<s16>" /* Same */
886 "\022<s17>" /* Same */
887 "\023<b18>" /* Reserved, unknown */
888 "\024MP" /* Multiprocessor Capable */
889 "\025NX" /* Has EFER.NXE, NX */
890 "\026<b21>" /* Undefined */
891 "\027MMX+" /* AMD MMX Extensions */
892 "\030<s23>" /* Same */
893 "\031<s24>" /* Same */
894 "\032FFXSR" /* Fast FXSAVE/FXRSTOR */
895 "\033Page1GB" /* 1-GB large page support */
896 "\034RDTSCP" /* RDTSCP */
897 "\035<b28>" /* Undefined */
898 "\036LM" /* 64 bit long mode */
899 "\0373DNow!+" /* AMD 3DNow! Extensions */
900 "\0403DNow!" /* AMD 3DNow! */
901 );
902 }
903
904 if (amd_feature2 != 0) {
905 printf("\n AMD Features2=0x%b", amd_feature2,
906 "\020"
907 "\001LAHF" /* LAHF/SAHF in long mode */
908 "\002CMP" /* CMP legacy */
909 "\003SVM" /* Secure Virtual Mode */
910 "\004ExtAPIC" /* Extended APIC register */
911 "\005CR8" /* CR8 in legacy mode */
912 "\006ABM" /* LZCNT instruction */
913 "\007SSE4A" /* SSE4A */
914 "\010MAS" /* Misaligned SSE mode */
915 "\011Prefetch" /* 3DNow! Prefetch/PrefetchW */
916 "\012OSVW" /* OS visible workaround */
917 "\013IBS" /* Instruction based sampling */
918 "\014XOP" /* XOP extended instructions */
919 "\015SKINIT" /* SKINIT/STGI */
920 "\016WDT" /* Watchdog timer */
921 "\017<b14>"
922 "\020LWP" /* Lightweight Profiling */
923 "\021FMA4" /* 4-operand FMA instructions */
924 "\022TCE" /* Translation Cache Extension */
925 "\023<b18>"
926 "\024NodeId" /* NodeId MSR support */
927 "\025<b20>"
928 "\026TBM" /* Trailing Bit Manipulation */
929 "\027Topology" /* Topology Extensions */
930 "\030PCXC" /* Core perf count */
931 "\031PNXC" /* NB perf count */
932 "\032<b25>"
933 "\033DBE" /* Data Breakpoint extension */
934 "\034PTSC" /* Performance TSC */
935 "\035PL2I" /* L2I perf count */
936 "\036MWAITX" /* MONITORX/MWAITX instructions */
937 "\037ADMSKX" /* Address mask extension */
938 "\040<b31>"
939 );
940 }
941
942 if (cpu_stdext_feature != 0) {
943 printf("\n Structured Extended Features=0x%b",
944 cpu_stdext_feature,
945 "\020"
946 /* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
947 "\001FSGSBASE"
948 "\002TSCADJ"
949 "\003SGX"
950 /* Bit Manipulation Instructions */
951 "\004BMI1"
952 /* Hardware Lock Elision */
953 "\005HLE"
954 /* Advanced Vector Instructions 2 */
955 "\006AVX2"
956 /* FDP_EXCPTN_ONLY */
957 "\007FDPEXC"
958 /* Supervisor Mode Execution Prot. */
959 "\010SMEP"
960 /* Bit Manipulation Instructions */
961 "\011BMI2"
962 "\012ERMS"
963 /* Invalidate Processor Context ID */
964 "\013INVPCID"
965 /* Restricted Transactional Memory */
966 "\014RTM"
967 "\015PQM"
968 "\016NFPUSG"
969 /* Intel Memory Protection Extensions */
970 "\017MPX"
971 "\020PQE"
972 /* AVX512 Foundation */
973 "\021AVX512F"
974 "\022AVX512DQ"
975 /* Enhanced NRBG */
976 "\023RDSEED"
977 /* ADCX + ADOX */
978 "\024ADX"
979 /* Supervisor Mode Access Prevention */
980 "\025SMAP"
981 "\026AVX512IFMA"
982 /* Formerly PCOMMIT */
983 "\027<b22>"
984 "\030CLFLUSHOPT"
985 "\031CLWB"
986 "\032PROCTRACE"
987 "\033AVX512PF"
988 "\034AVX512ER"
989 "\035AVX512CD"
990 "\036SHA"
991 "\037AVX512BW"
992 "\040AVX512VL"
993 );
994 }
995
996 if (cpu_stdext_feature2 != 0) {
997 printf("\n Structured Extended Features2=0x%b",
998 cpu_stdext_feature2,
999 "\020"
1000 "\001PREFETCHWT1"
1001 "\002AVX512VBMI"
1002 "\003UMIP"
1003 "\004PKU"
1004 "\005OSPKE"
1005 "\006WAITPKG"
1006 "\007AVX512VBMI2"
1007 "\011GFNI"
1008 "\012VAES"
1009 "\013VPCLMULQDQ"
1010 "\014AVX512VNNI"
1011 "\015AVX512BITALG"
1012 "\016TME"
1013 "\017AVX512VPOPCNTDQ"
1014 "\021LA57"
1015 "\027RDPID"
1016 "\032CLDEMOTE"
1017 "\034MOVDIRI"
1018 "\035MOVDIR64B"
1019 "\036ENQCMD"
1020 "\037SGXLC"
1021 );
1022 }
1023
1024 if (cpu_stdext_feature3 != 0) {
1025 printf("\n Structured Extended Features3=0x%b",
1026 cpu_stdext_feature3,
1027 "\020"
1028 "\003AVX512_4VNNIW"
1029 "\004AVX512_4FMAPS"
1030 "\005FSRM"
1031 "\011AVX512VP2INTERSECT"
1032 "\012MCUOPT"
1033 "\013MD_CLEAR"
1034 "\016TSXFA"
1035 "\023PCONFIG"
1036 "\025IBT"
1037 "\033IBPB"
1038 "\034STIBP"
1039 "\035L1DFL"
1040 "\036ARCH_CAP"
1041 "\037CORE_CAP"
1042 "\040SSBD"
1043 );
1044 }
1045
1046 if ((cpu_feature2 & CPUID2_XSAVE) != 0) {
1047 cpuid_count(0xd, 0x1, regs);
1048 if (regs[0] != 0) {
1049 printf("\n XSAVE Features=0x%b",
1050 regs[0],
1051 "\020"
1052 "\001XSAVEOPT"
1053 "\002XSAVEC"
1054 "\003XINUSE"
1055 "\004XSAVES");
1056 }
1057 }
1058
1059 if (cpu_ia32_arch_caps != 0) {
1060 printf("\n IA32_ARCH_CAPS=0x%b",
1061 (u_int)cpu_ia32_arch_caps,
1062 "\020"
1063 "\001RDCL_NO"
1064 "\002IBRS_ALL"
1065 "\003RSBA"
1066 "\004SKIP_L1DFL_VME"
1067 "\005SSB_NO"
1068 "\006MDS_NO"
1069 "\010TSX_CTRL"
1070 "\011TAA_NO"
1071 );
1072 }
1073
1074 if (amd_extended_feature_extensions != 0) {
1075 u_int amd_fe_masked;
1076
1077 amd_fe_masked = amd_extended_feature_extensions;
1078 if ((amd_fe_masked & AMDFEID_IBRS) == 0)
1079 amd_fe_masked &=
1080 ~(AMDFEID_IBRS_ALWAYSON |
1081 AMDFEID_PREFER_IBRS);
1082 if ((amd_fe_masked & AMDFEID_STIBP) == 0)
1083 amd_fe_masked &=
1084 ~AMDFEID_STIBP_ALWAYSON;
1085
1086 printf("\n "
1087 "AMD Extended Feature Extensions ID EBX="
1088 "0x%b", amd_fe_masked,
1089 "\020"
1090 "\001CLZERO"
1091 "\002IRPerf"
1092 "\003XSaveErPtr"
1093 "\004INVLPGB"
1094 "\005RDPRU"
1095 "\007BE"
1096 "\011MCOMMIT"
1097 "\012WBNOINVD"
1098 "\015IBPB"
1099 "\016INT_WBINVD"
1100 "\017IBRS"
1101 "\020STIBP"
1102 "\021IBRS_ALWAYSON"
1103 "\022STIBP_ALWAYSON"
1104 "\023PREFER_IBRS"
1105 "\024SAMEMODE_IBRS"
1106 "\025NOLMSLE"
1107 "\026INVLPGBNEST"
1108 "\030PPIN"
1109 "\031SSBD"
1110 "\032VIRT_SSBD"
1111 "\033SSB_NO"
1112 "\034CPPC"
1113 "\035PSFD"
1114 "\036BTC_NO"
1115 "\037IBPB_RET"
1116 );
1117 }
1118
1119 if (via_feature_rng != 0 || via_feature_xcrypt != 0)
1120 print_via_padlock_info();
1121
1122 if (cpu_feature2 & CPUID2_VMX)
1123 print_vmx_info();
1124
1125 if (amd_feature2 & AMDID2_SVM)
1126 print_svm_info();
1127
1128 if ((cpu_feature & CPUID_HTT) &&
1129 (cpu_vendor_id == CPU_VENDOR_AMD ||
1130 cpu_vendor_id == CPU_VENDOR_HYGON))
1131 cpu_feature &= ~CPUID_HTT;
1132
1133 /*
1134 * If this CPU supports P-state invariant TSC then
1135 * mention the capability.
1136 */
1137 if (tsc_is_invariant) {
1138 printf("\n TSC: P-state invariant");
1139 if (tsc_perf_stat)
1140 printf(", performance statistics");
1141 }
1142 }
1143 #ifdef __i386__
1144 } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1145 printf(" DIR=0x%04x", cyrix_did);
1146 printf(" Stepping=%u", (cyrix_did & 0xf000) >> 12);
1147 printf(" Revision=%u", (cyrix_did & 0x0f00) >> 8);
1148 #ifndef CYRIX_CACHE_REALLY_WORKS
1149 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
1150 printf("\n CPU cache: write-through mode");
1151 #endif
1152 #endif
1153 }
1154
1155 /* Avoid ugly blank lines: only print newline when we have to. */
1156 if (*cpu_vendor || cpu_id)
1157 printf("\n");
1158
1159 if (bootverbose) {
1160 if (cpu_vendor_id == CPU_VENDOR_AMD ||
1161 cpu_vendor_id == CPU_VENDOR_HYGON)
1162 print_AMD_info();
1163 else if (cpu_vendor_id == CPU_VENDOR_INTEL)
1164 print_INTEL_info();
1165 #ifdef __i386__
1166 else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA)
1167 print_transmeta_info();
1168 #endif
1169 }
1170
1171 print_hypervisor_info();
1172 }
1173
1174 #ifdef __i386__
1175 void
panicifcpuunsupported(void)1176 panicifcpuunsupported(void)
1177 {
1178
1179 #if !defined(lint)
1180 #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
1181 #error This kernel is not configured for one of the supported CPUs
1182 #endif
1183 #else /* lint */
1184 #endif /* lint */
1185 /*
1186 * Now that we have told the user what they have,
1187 * let them know if that machine type isn't configured.
1188 */
1189 switch (cpu_class) {
1190 case CPUCLASS_286: /* a 286 should not make it this far, anyway */
1191 case CPUCLASS_386:
1192 #if !defined(I486_CPU)
1193 case CPUCLASS_486:
1194 #endif
1195 #if !defined(I586_CPU)
1196 case CPUCLASS_586:
1197 #endif
1198 #if !defined(I686_CPU)
1199 case CPUCLASS_686:
1200 #endif
1201 panic("CPU class not configured");
1202 default:
1203 break;
1204 }
1205 }
1206
1207 static volatile u_int trap_by_rdmsr;
1208
1209 /*
1210 * Special exception 6 handler.
1211 * The rdmsr instruction generates invalid opcodes fault on 486-class
1212 * Cyrix CPU. Stacked eip register points the rdmsr instruction in the
1213 * function identblue() when this handler is called. Stacked eip should
1214 * be advanced.
1215 */
1216 inthand_t bluetrap6;
1217 __asm
1218 (" \n\
1219 .text \n\
1220 .p2align 2,0x90 \n\
1221 .type " __XSTRING(CNAME(bluetrap6)) ",@function \n\
1222 " __XSTRING(CNAME(bluetrap6)) ": \n\
1223 ss \n\
1224 movl $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) " \n\
1225 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\
1226 iret \n\
1227 ");
1228
1229 /*
1230 * Special exception 13 handler.
1231 * Accessing non-existent MSR generates general protection fault.
1232 */
1233 inthand_t bluetrap13;
1234 __asm
1235 (" \n\
1236 .text \n\
1237 .p2align 2,0x90 \n\
1238 .type " __XSTRING(CNAME(bluetrap13)) ",@function \n\
1239 " __XSTRING(CNAME(bluetrap13)) ": \n\
1240 ss \n\
1241 movl $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) " \n\
1242 popl %eax /* discard error code */ \n\
1243 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\
1244 iret \n\
1245 ");
1246
1247 /*
1248 * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
1249 * support cpuid instruction. This function should be called after
1250 * loading interrupt descriptor table register.
1251 *
1252 * I don't like this method that handles fault, but I couldn't get
1253 * information for any other methods. Does blue giant know?
1254 */
1255 static int
identblue(void)1256 identblue(void)
1257 {
1258
1259 trap_by_rdmsr = 0;
1260
1261 /*
1262 * Cyrix 486-class CPU does not support rdmsr instruction.
1263 * The rdmsr instruction generates invalid opcode fault, and exception
1264 * will be trapped by bluetrap6() on Cyrix 486-class CPU. The
1265 * bluetrap6() set the magic number to trap_by_rdmsr.
1266 */
1267 setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL,
1268 GSEL(GCODE_SEL, SEL_KPL));
1269
1270 /*
1271 * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
1272 * In this case, rdmsr generates general protection fault, and
1273 * exception will be trapped by bluetrap13().
1274 */
1275 setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL,
1276 GSEL(GCODE_SEL, SEL_KPL));
1277
1278 rdmsr(0x1002); /* Cyrix CPU generates fault. */
1279
1280 if (trap_by_rdmsr == 0xa8c1d)
1281 return IDENTBLUE_CYRIX486;
1282 else if (trap_by_rdmsr == 0xa89c4)
1283 return IDENTBLUE_CYRIXM2;
1284 return IDENTBLUE_IBMCPU;
1285 }
1286
1287 /*
1288 * identifycyrix() set lower 16 bits of cyrix_did as follows:
1289 *
1290 * F E D C B A 9 8 7 6 5 4 3 2 1 0
1291 * +-------+-------+---------------+
1292 * | SID | RID | Device ID |
1293 * | (DIR 1) | (DIR 0) |
1294 * +-------+-------+---------------+
1295 */
1296 static void
identifycyrix(void)1297 identifycyrix(void)
1298 {
1299 register_t saveintr;
1300 int ccr2_test = 0, dir_test = 0;
1301 u_char ccr2, ccr3;
1302
1303 saveintr = intr_disable();
1304
1305 ccr2 = read_cyrix_reg(CCR2);
1306 write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
1307 read_cyrix_reg(CCR2);
1308 if (read_cyrix_reg(CCR2) != ccr2)
1309 ccr2_test = 1;
1310 write_cyrix_reg(CCR2, ccr2);
1311
1312 ccr3 = read_cyrix_reg(CCR3);
1313 write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
1314 read_cyrix_reg(CCR3);
1315 if (read_cyrix_reg(CCR3) != ccr3)
1316 dir_test = 1; /* CPU supports DIRs. */
1317 write_cyrix_reg(CCR3, ccr3);
1318
1319 if (dir_test) {
1320 /* Device ID registers are available. */
1321 cyrix_did = read_cyrix_reg(DIR1) << 8;
1322 cyrix_did += read_cyrix_reg(DIR0);
1323 } else if (ccr2_test)
1324 cyrix_did = 0x0010; /* 486S A-step */
1325 else
1326 cyrix_did = 0x00ff; /* Old 486SLC/DLC and TI486SXLC/SXL */
1327
1328 intr_restore(saveintr);
1329 }
1330 #endif
1331
1332 /* Update TSC freq with the value indicated by the caller. */
1333 static void
tsc_freq_changed(void * arg __unused,const struct cf_level * level,int status)1334 tsc_freq_changed(void *arg __unused, const struct cf_level *level, int status)
1335 {
1336
1337 /* If there was an error during the transition, don't do anything. */
1338 if (status != 0)
1339 return;
1340
1341 /* Total setting for this level gives the new frequency in MHz. */
1342 hw_clockrate = level->total_set.freq;
1343 }
1344
1345 static void
hook_tsc_freq(void * arg __unused)1346 hook_tsc_freq(void *arg __unused)
1347 {
1348
1349 if (tsc_is_invariant)
1350 return;
1351
1352 tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change,
1353 tsc_freq_changed, NULL, EVENTHANDLER_PRI_ANY);
1354 }
1355
1356 SYSINIT(hook_tsc_freq, SI_SUB_CONFIGURE, SI_ORDER_ANY, hook_tsc_freq, NULL);
1357
1358 static struct {
1359 const char *vm_cpuid;
1360 int vm_guest;
1361 void (*init)(void);
1362 } vm_cpuids[] = {
1363 { "XenVMMXenVMM", VM_GUEST_XEN,
1364 #ifdef XENHVM
1365 &xen_early_init,
1366 #endif
1367 }, /* XEN */
1368 { "Microsoft Hv", VM_GUEST_HV }, /* Microsoft Hyper-V */
1369 { "VMwareVMware", VM_GUEST_VMWARE }, /* VMware VM */
1370 { "KVMKVMKVM", VM_GUEST_KVM }, /* KVM */
1371 { "bhyve bhyve ", VM_GUEST_BHYVE }, /* bhyve */
1372 { "VBoxVBoxVBox", VM_GUEST_VBOX }, /* VirtualBox */
1373 { "___ NVMM ___", VM_GUEST_NVMM }, /* NVMM */
1374 };
1375
1376 static void
identify_hypervisor_cpuid_base(void)1377 identify_hypervisor_cpuid_base(void)
1378 {
1379 void (*init_fn)(void) = NULL;
1380 u_int leaf, regs[4];
1381 int i;
1382
1383 /*
1384 * [RFC] CPUID usage for interaction between Hypervisors and Linux.
1385 * http://lkml.org/lkml/2008/10/1/246
1386 *
1387 * KB1009458: Mechanisms to determine if software is running in
1388 * a VMware virtual machine
1389 * http://kb.vmware.com/kb/1009458
1390 *
1391 * Search for a hypervisor that we recognize. If we cannot find
1392 * a specific hypervisor, return the first information about the
1393 * hypervisor that we found, as others may be able to use.
1394 */
1395 for (leaf = 0x40000000; leaf < 0x40010000; leaf += 0x100) {
1396 do_cpuid(leaf, regs);
1397
1398 /*
1399 * KVM from Linux kernels prior to commit
1400 * 57c22e5f35aa4b9b2fe11f73f3e62bbf9ef36190 set %eax
1401 * to 0 rather than a valid hv_high value. Check for
1402 * the KVM signature bytes and fixup %eax to the
1403 * highest supported leaf in that case.
1404 */
1405 if (regs[0] == 0 && regs[1] == 0x4b4d564b &&
1406 regs[2] == 0x564b4d56 && regs[3] == 0x0000004d)
1407 regs[0] = leaf + 1;
1408
1409 if (regs[0] >= leaf) {
1410 enum VM_GUEST prev_vm_guest = vm_guest;
1411
1412 for (i = 0; i < nitems(vm_cpuids); i++)
1413 if (strncmp((const char *)®s[1],
1414 vm_cpuids[i].vm_cpuid, 12) == 0) {
1415 vm_guest = vm_cpuids[i].vm_guest;
1416 init_fn = vm_cpuids[i].init;
1417 break;
1418 }
1419
1420 /*
1421 * If this is the first entry or we found a
1422 * specific hypervisor, record the base, high value,
1423 * and vendor identifier.
1424 */
1425 if (vm_guest != prev_vm_guest || leaf == 0x40000000) {
1426 hv_base = leaf;
1427 hv_high = regs[0];
1428 ((u_int *)&hv_vendor)[0] = regs[1];
1429 ((u_int *)&hv_vendor)[1] = regs[2];
1430 ((u_int *)&hv_vendor)[2] = regs[3];
1431 hv_vendor[12] = '\0';
1432
1433 /*
1434 * If we found a specific hypervisor, then
1435 * we are finished.
1436 */
1437 if (vm_guest != VM_GUEST_VM &&
1438 /*
1439 * Xen and other hypervisors can expose the
1440 * HyperV signature in addition to the
1441 * native one in order to support Viridian
1442 * extensions for Windows guests.
1443 *
1444 * Do the full cpuid scan if HyperV is
1445 * detected, as the native hypervisor is
1446 * preferred.
1447 */
1448 vm_guest != VM_GUEST_HV)
1449 break;
1450 }
1451 }
1452 }
1453
1454 if (init_fn != NULL)
1455 init_fn();
1456 }
1457
1458 void
identify_hypervisor(void)1459 identify_hypervisor(void)
1460 {
1461 u_int regs[4];
1462 char *p;
1463
1464 TSENTER();
1465 /*
1466 * If CPUID2_HV is set, we are running in a hypervisor environment.
1467 */
1468 if (cpu_feature2 & CPUID2_HV) {
1469 vm_guest = VM_GUEST_VM;
1470 identify_hypervisor_cpuid_base();
1471
1472 /* If we have a definitive vendor, we can return now. */
1473 if (*hv_vendor != '\0') {
1474 TSEXIT();
1475 return;
1476 }
1477 }
1478
1479 /*
1480 * Examine SMBIOS strings for older hypervisors.
1481 */
1482 p = kern_getenv("smbios.system.serial");
1483 if (p != NULL) {
1484 if (strncmp(p, "VMware-", 7) == 0 || strncmp(p, "VMW", 3) == 0) {
1485 vmware_hvcall(0, VMW_HVCMD_GETVERSION,
1486 VMW_HVCMD_DEFAULT_PARAM, regs);
1487 if (regs[1] == VMW_HVMAGIC) {
1488 vm_guest = VM_GUEST_VMWARE;
1489 freeenv(p);
1490 TSEXIT();
1491 return;
1492 }
1493 }
1494 freeenv(p);
1495 }
1496 TSEXIT();
1497 }
1498
1499 bool
fix_cpuid(void)1500 fix_cpuid(void)
1501 {
1502 uint64_t msr;
1503
1504 /*
1505 * Clear "Limit CPUID Maxval" bit and return true if the caller should
1506 * get the largest standard CPUID function number again if it is set
1507 * from BIOS. It is necessary for probing correct CPU topology later
1508 * and for the correct operation of the AVX-aware userspace.
1509 */
1510 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
1511 ((CPUID_TO_FAMILY(cpu_id) == 0xf &&
1512 CPUID_TO_MODEL(cpu_id) >= 0x3) ||
1513 (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
1514 CPUID_TO_MODEL(cpu_id) >= 0xe))) {
1515 msr = rdmsr(MSR_IA32_MISC_ENABLE);
1516 if ((msr & IA32_MISC_EN_LIMCPUID) != 0) {
1517 msr &= ~IA32_MISC_EN_LIMCPUID;
1518 wrmsr(MSR_IA32_MISC_ENABLE, msr);
1519 return (true);
1520 }
1521 }
1522
1523 /*
1524 * Re-enable AMD Topology Extension that could be disabled by BIOS
1525 * on some notebook processors. Without the extension it's really
1526 * hard to determine the correct CPU cache topology.
1527 * See BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 15h
1528 * Models 60h-6Fh Processors, Publication # 50742.
1529 */
1530 if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_AMD &&
1531 CPUID_TO_FAMILY(cpu_id) == 0x15) {
1532 msr = rdmsr(MSR_EXTFEATURES);
1533 if ((msr & ((uint64_t)1 << 54)) == 0) {
1534 msr |= (uint64_t)1 << 54;
1535 wrmsr(MSR_EXTFEATURES, msr);
1536 return (true);
1537 }
1538 }
1539 return (false);
1540 }
1541
1542 void
identify_cpu1(void)1543 identify_cpu1(void)
1544 {
1545 u_int regs[4];
1546
1547 do_cpuid(0, regs);
1548 cpu_high = regs[0];
1549 ((u_int *)&cpu_vendor)[0] = regs[1];
1550 ((u_int *)&cpu_vendor)[1] = regs[3];
1551 ((u_int *)&cpu_vendor)[2] = regs[2];
1552 cpu_vendor[12] = '\0';
1553
1554 do_cpuid(1, regs);
1555 cpu_id = regs[0];
1556 cpu_procinfo = regs[1];
1557 cpu_feature = regs[3];
1558 cpu_feature2 = regs[2];
1559 }
1560
1561 void
identify_cpu2(void)1562 identify_cpu2(void)
1563 {
1564 u_int regs[4], cpu_stdext_disable;
1565
1566 if (cpu_high >= 6) {
1567 cpuid_count(6, 0, regs);
1568 cpu_power_eax = regs[0];
1569 cpu_power_ebx = regs[1];
1570 cpu_power_ecx = regs[2];
1571 cpu_power_edx = regs[3];
1572 }
1573
1574 if (cpu_high >= 7) {
1575 cpuid_count(7, 0, regs);
1576 cpu_stdext_feature = regs[1];
1577
1578 /*
1579 * Some hypervisors failed to filter out unsupported
1580 * extended features. Allow to disable the
1581 * extensions, activation of which requires setting a
1582 * bit in CR4, and which VM monitors do not support.
1583 */
1584 cpu_stdext_disable = 0;
1585 TUNABLE_INT_FETCH("hw.cpu_stdext_disable", &cpu_stdext_disable);
1586 cpu_stdext_feature &= ~cpu_stdext_disable;
1587
1588 cpu_stdext_feature2 = regs[2];
1589 cpu_stdext_feature3 = regs[3];
1590
1591 if ((cpu_stdext_feature3 & CPUID_STDEXT3_ARCH_CAP) != 0)
1592 cpu_ia32_arch_caps = rdmsr(MSR_IA32_ARCH_CAP);
1593 }
1594 }
1595
1596 void
identify_cpu_ext_features(void)1597 identify_cpu_ext_features(void)
1598 {
1599 u_int regs[4];
1600
1601 if (cpu_high >= 7) {
1602 cpuid_count(7, 0, regs);
1603 cpu_stdext_feature2 = regs[2];
1604 cpu_stdext_feature3 = regs[3];
1605 }
1606 }
1607
1608 void
identify_cpu_fixup_bsp(void)1609 identify_cpu_fixup_bsp(void)
1610 {
1611 u_int regs[4];
1612
1613 cpu_vendor_id = find_cpu_vendor_id();
1614
1615 if (fix_cpuid()) {
1616 do_cpuid(0, regs);
1617 cpu_high = regs[0];
1618 }
1619 }
1620
1621 /*
1622 * Final stage of CPU identification.
1623 */
1624 void
finishidentcpu(void)1625 finishidentcpu(void)
1626 {
1627 u_int regs[4];
1628 #ifdef __i386__
1629 u_char ccr3;
1630 #endif
1631
1632 identify_cpu_fixup_bsp();
1633
1634 if (cpu_high >= 5 && (cpu_feature2 & CPUID2_MON) != 0) {
1635 do_cpuid(5, regs);
1636 cpu_mon_mwait_flags = regs[2];
1637 cpu_mon_min_size = regs[0] & CPUID5_MON_MIN_SIZE;
1638 cpu_mon_max_size = regs[1] & CPUID5_MON_MAX_SIZE;
1639 }
1640
1641 identify_cpu2();
1642
1643 #ifdef __i386__
1644 if (cpu_high > 0 &&
1645 (cpu_vendor_id == CPU_VENDOR_INTEL ||
1646 cpu_vendor_id == CPU_VENDOR_AMD ||
1647 cpu_vendor_id == CPU_VENDOR_HYGON ||
1648 cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
1649 cpu_vendor_id == CPU_VENDOR_CENTAUR ||
1650 cpu_vendor_id == CPU_VENDOR_NSC)) {
1651 do_cpuid(0x80000000, regs);
1652 if (regs[0] >= 0x80000000)
1653 cpu_exthigh = regs[0];
1654 }
1655 #else
1656 if (cpu_vendor_id == CPU_VENDOR_INTEL ||
1657 cpu_vendor_id == CPU_VENDOR_AMD ||
1658 cpu_vendor_id == CPU_VENDOR_HYGON ||
1659 cpu_vendor_id == CPU_VENDOR_CENTAUR) {
1660 do_cpuid(0x80000000, regs);
1661 cpu_exthigh = regs[0];
1662 }
1663 #endif
1664 if (cpu_exthigh >= 0x80000001) {
1665 do_cpuid(0x80000001, regs);
1666 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
1667 amd_feature2 = regs[2];
1668 }
1669 if (cpu_exthigh >= 0x80000007) {
1670 do_cpuid(0x80000007, regs);
1671 amd_rascap = regs[1];
1672 amd_pminfo = regs[3];
1673 }
1674 if (cpu_exthigh >= 0x80000008) {
1675 do_cpuid(0x80000008, regs);
1676 cpu_maxphyaddr = regs[0] & 0xff;
1677 amd_extended_feature_extensions = regs[1];
1678 cpu_procinfo2 = regs[2];
1679 cpu_procinfo3 = regs[3];
1680 } else {
1681 cpu_maxphyaddr = (cpu_feature & CPUID_PAE) != 0 ? 36 : 32;
1682 }
1683
1684 #ifdef __i386__
1685 if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1686 if (cpu == CPU_486) {
1687 /*
1688 * These conditions are equivalent to:
1689 * - CPU does not support cpuid instruction.
1690 * - Cyrix/IBM CPU is detected.
1691 */
1692 if (identblue() == IDENTBLUE_IBMCPU) {
1693 strcpy(cpu_vendor, "IBM");
1694 cpu_vendor_id = CPU_VENDOR_IBM;
1695 cpu = CPU_BLUE;
1696 return;
1697 }
1698 }
1699 switch (cpu_id & 0xf00) {
1700 case 0x600:
1701 /*
1702 * Cyrix's datasheet does not describe DIRs.
1703 * Therefor, I assume it does not have them
1704 * and use the result of the cpuid instruction.
1705 * XXX they seem to have it for now at least. -Peter
1706 */
1707 identifycyrix();
1708 cpu = CPU_M2;
1709 break;
1710 default:
1711 identifycyrix();
1712 /*
1713 * This routine contains a trick.
1714 * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
1715 */
1716 switch (cyrix_did & 0x00f0) {
1717 case 0x00:
1718 case 0xf0:
1719 cpu = CPU_486DLC;
1720 break;
1721 case 0x10:
1722 cpu = CPU_CY486DX;
1723 break;
1724 case 0x20:
1725 if ((cyrix_did & 0x000f) < 8)
1726 cpu = CPU_M1;
1727 else
1728 cpu = CPU_M1SC;
1729 break;
1730 case 0x30:
1731 cpu = CPU_M1;
1732 break;
1733 case 0x40:
1734 /* MediaGX CPU */
1735 cpu = CPU_M1SC;
1736 break;
1737 default:
1738 /* M2 and later CPUs are treated as M2. */
1739 cpu = CPU_M2;
1740
1741 /*
1742 * enable cpuid instruction.
1743 */
1744 ccr3 = read_cyrix_reg(CCR3);
1745 write_cyrix_reg(CCR3, CCR3_MAPEN0);
1746 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
1747 write_cyrix_reg(CCR3, ccr3);
1748
1749 do_cpuid(0, regs);
1750 cpu_high = regs[0]; /* eax */
1751 do_cpuid(1, regs);
1752 cpu_id = regs[0]; /* eax */
1753 cpu_feature = regs[3]; /* edx */
1754 break;
1755 }
1756 }
1757 } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
1758 /*
1759 * There are BlueLightning CPUs that do not change
1760 * undefined flags by dividing 5 by 2. In this case,
1761 * the CPU identification routine in locore.s leaves
1762 * cpu_vendor null string and puts CPU_486 into the
1763 * cpu.
1764 */
1765 if (identblue() == IDENTBLUE_IBMCPU) {
1766 strcpy(cpu_vendor, "IBM");
1767 cpu_vendor_id = CPU_VENDOR_IBM;
1768 cpu = CPU_BLUE;
1769 return;
1770 }
1771 }
1772 #endif
1773 }
1774
1775 int
pti_get_default(void)1776 pti_get_default(void)
1777 {
1778
1779 if (strcmp(cpu_vendor, AMD_VENDOR_ID) == 0 ||
1780 strcmp(cpu_vendor, HYGON_VENDOR_ID) == 0)
1781 return (0);
1782 if ((cpu_ia32_arch_caps & IA32_ARCH_CAP_RDCL_NO) != 0)
1783 return (0);
1784 return (1);
1785 }
1786
1787 static u_int
find_cpu_vendor_id(void)1788 find_cpu_vendor_id(void)
1789 {
1790 int i;
1791
1792 for (i = 0; i < nitems(cpu_vendors); i++)
1793 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0)
1794 return (cpu_vendors[i].vendor_id);
1795 return (0);
1796 }
1797
1798 static void
print_AMD_assoc(int i)1799 print_AMD_assoc(int i)
1800 {
1801 if (i == 255)
1802 printf(", fully associative\n");
1803 else
1804 printf(", %d-way associative\n", i);
1805 }
1806
1807 static void
print_AMD_l2_assoc(int i)1808 print_AMD_l2_assoc(int i)
1809 {
1810 switch (i & 0x0f) {
1811 case 0: printf(", disabled/not present\n"); break;
1812 case 1: printf(", direct mapped\n"); break;
1813 case 2: printf(", 2-way associative\n"); break;
1814 case 4: printf(", 4-way associative\n"); break;
1815 case 6: printf(", 8-way associative\n"); break;
1816 case 8: printf(", 16-way associative\n"); break;
1817 case 15: printf(", fully associative\n"); break;
1818 default: printf(", reserved configuration\n"); break;
1819 }
1820 }
1821
1822 static void
print_AMD_info(void)1823 print_AMD_info(void)
1824 {
1825 #ifdef __i386__
1826 uint64_t amd_whcr;
1827 #endif
1828 u_int regs[4];
1829
1830 if (cpu_exthigh >= 0x80000005) {
1831 do_cpuid(0x80000005, regs);
1832 printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff);
1833 print_AMD_assoc(regs[0] >> 24);
1834
1835 printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff);
1836 print_AMD_assoc((regs[0] >> 8) & 0xff);
1837
1838 printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff);
1839 print_AMD_assoc(regs[1] >> 24);
1840
1841 printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff);
1842 print_AMD_assoc((regs[1] >> 8) & 0xff);
1843
1844 printf("L1 data cache: %d kbytes", regs[2] >> 24);
1845 printf(", %d bytes/line", regs[2] & 0xff);
1846 printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
1847 print_AMD_assoc((regs[2] >> 16) & 0xff);
1848
1849 printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
1850 printf(", %d bytes/line", regs[3] & 0xff);
1851 printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
1852 print_AMD_assoc((regs[3] >> 16) & 0xff);
1853 }
1854
1855 if (cpu_exthigh >= 0x80000006) {
1856 do_cpuid(0x80000006, regs);
1857 if ((regs[0] >> 16) != 0) {
1858 printf("L2 2MB data TLB: %d entries",
1859 (regs[0] >> 16) & 0xfff);
1860 print_AMD_l2_assoc(regs[0] >> 28);
1861 printf("L2 2MB instruction TLB: %d entries",
1862 regs[0] & 0xfff);
1863 print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1864 } else {
1865 printf("L2 2MB unified TLB: %d entries",
1866 regs[0] & 0xfff);
1867 print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1868 }
1869 if ((regs[1] >> 16) != 0) {
1870 printf("L2 4KB data TLB: %d entries",
1871 (regs[1] >> 16) & 0xfff);
1872 print_AMD_l2_assoc(regs[1] >> 28);
1873
1874 printf("L2 4KB instruction TLB: %d entries",
1875 (regs[1] >> 16) & 0xfff);
1876 print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1877 } else {
1878 printf("L2 4KB unified TLB: %d entries",
1879 (regs[1] >> 16) & 0xfff);
1880 print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1881 }
1882 printf("L2 unified cache: %d kbytes", regs[2] >> 16);
1883 printf(", %d bytes/line", regs[2] & 0xff);
1884 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
1885 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f);
1886 }
1887
1888 #ifdef __i386__
1889 if (((cpu_id & 0xf00) == 0x500)
1890 && (((cpu_id & 0x0f0) > 0x80)
1891 || (((cpu_id & 0x0f0) == 0x80)
1892 && (cpu_id & 0x00f) > 0x07))) {
1893 /* K6-2(new core [Stepping 8-F]), K6-III or later */
1894 amd_whcr = rdmsr(0xc0000082);
1895 if (!(amd_whcr & (0x3ff << 22))) {
1896 printf("Write Allocate Disable\n");
1897 } else {
1898 printf("Write Allocate Enable Limit: %dM bytes\n",
1899 (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
1900 printf("Write Allocate 15-16M bytes: %s\n",
1901 (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
1902 }
1903 } else if (((cpu_id & 0xf00) == 0x500)
1904 && ((cpu_id & 0x0f0) > 0x50)) {
1905 /* K6, K6-2(old core) */
1906 amd_whcr = rdmsr(0xc0000082);
1907 if (!(amd_whcr & (0x7f << 1))) {
1908 printf("Write Allocate Disable\n");
1909 } else {
1910 printf("Write Allocate Enable Limit: %dM bytes\n",
1911 (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
1912 printf("Write Allocate 15-16M bytes: %s\n",
1913 (amd_whcr & 0x0001) ? "Enable" : "Disable");
1914 printf("Hardware Write Allocate Control: %s\n",
1915 (amd_whcr & 0x0100) ? "Enable" : "Disable");
1916 }
1917 }
1918 #endif
1919 /*
1920 * Opteron Rev E shows a bug as in very rare occasions a read memory
1921 * barrier is not performed as expected if it is followed by a
1922 * non-atomic read-modify-write instruction.
1923 * As long as that bug pops up very rarely (intensive machine usage
1924 * on other operating systems generally generates one unexplainable
1925 * crash any 2 months) and as long as a model specific fix would be
1926 * impractical at this stage, print out a warning string if the broken
1927 * model and family are identified.
1928 */
1929 if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 &&
1930 CPUID_TO_MODEL(cpu_id) <= 0x3f)
1931 printf("WARNING: This architecture revision has known SMP "
1932 "hardware bugs which may cause random instability\n");
1933 }
1934
1935 static void
print_INTEL_info(void)1936 print_INTEL_info(void)
1937 {
1938 u_int regs[4];
1939 u_int rounds, regnum;
1940 u_int nwaycode, nway;
1941
1942 if (cpu_high >= 2) {
1943 rounds = 0;
1944 do {
1945 do_cpuid(0x2, regs);
1946 if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0)
1947 break; /* we have a buggy CPU */
1948
1949 for (regnum = 0; regnum <= 3; ++regnum) {
1950 if (regs[regnum] & (1<<31))
1951 continue;
1952 if (regnum != 0)
1953 print_INTEL_TLB(regs[regnum] & 0xff);
1954 print_INTEL_TLB((regs[regnum] >> 8) & 0xff);
1955 print_INTEL_TLB((regs[regnum] >> 16) & 0xff);
1956 print_INTEL_TLB((regs[regnum] >> 24) & 0xff);
1957 }
1958 } while (--rounds > 0);
1959 }
1960
1961 if (cpu_exthigh >= 0x80000006) {
1962 do_cpuid(0x80000006, regs);
1963 nwaycode = (regs[2] >> 12) & 0x0f;
1964 if (nwaycode >= 0x02 && nwaycode <= 0x08)
1965 nway = 1 << (nwaycode / 2);
1966 else
1967 nway = 0;
1968 printf("L2 cache: %u kbytes, %u-way associative, %u bytes/line\n",
1969 (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff);
1970 }
1971 }
1972
1973 static void
print_INTEL_TLB(u_int data)1974 print_INTEL_TLB(u_int data)
1975 {
1976 switch (data) {
1977 case 0x0:
1978 case 0x40:
1979 default:
1980 break;
1981 case 0x1:
1982 printf("Instruction TLB: 4 KB pages, 4-way set associative, 32 entries\n");
1983 break;
1984 case 0x2:
1985 printf("Instruction TLB: 4 MB pages, fully associative, 2 entries\n");
1986 break;
1987 case 0x3:
1988 printf("Data TLB: 4 KB pages, 4-way set associative, 64 entries\n");
1989 break;
1990 case 0x4:
1991 printf("Data TLB: 4 MB Pages, 4-way set associative, 8 entries\n");
1992 break;
1993 case 0x6:
1994 printf("1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size\n");
1995 break;
1996 case 0x8:
1997 printf("1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size\n");
1998 break;
1999 case 0x9:
2000 printf("1st-level instruction cache: 32 KB, 4-way set associative, 64 byte line size\n");
2001 break;
2002 case 0xa:
2003 printf("1st-level data cache: 8 KB, 2-way set associative, 32 byte line size\n");
2004 break;
2005 case 0xb:
2006 printf("Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries\n");
2007 break;
2008 case 0xc:
2009 printf("1st-level data cache: 16 KB, 4-way set associative, 32 byte line size\n");
2010 break;
2011 case 0xd:
2012 printf("1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size");
2013 break;
2014 case 0xe:
2015 printf("1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size\n");
2016 break;
2017 case 0x1d:
2018 printf("2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size\n");
2019 break;
2020 case 0x21:
2021 printf("2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size\n");
2022 break;
2023 case 0x22:
2024 printf("3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2025 break;
2026 case 0x23:
2027 printf("3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2028 break;
2029 case 0x24:
2030 printf("2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size\n");
2031 break;
2032 case 0x25:
2033 printf("3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2034 break;
2035 case 0x29:
2036 printf("3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2037 break;
2038 case 0x2c:
2039 printf("1st-level data cache: 32 KB, 8-way set associative, 64 byte line size\n");
2040 break;
2041 case 0x30:
2042 printf("1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size\n");
2043 break;
2044 case 0x39: /* De-listed in SDM rev. 54 */
2045 printf("2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2046 break;
2047 case 0x3b: /* De-listed in SDM rev. 54 */
2048 printf("2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size\n");
2049 break;
2050 case 0x3c: /* De-listed in SDM rev. 54 */
2051 printf("2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2052 break;
2053 case 0x41:
2054 printf("2nd-level cache: 128 KB, 4-way set associative, 32 byte line size\n");
2055 break;
2056 case 0x42:
2057 printf("2nd-level cache: 256 KB, 4-way set associative, 32 byte line size\n");
2058 break;
2059 case 0x43:
2060 printf("2nd-level cache: 512 KB, 4-way set associative, 32 byte line size\n");
2061 break;
2062 case 0x44:
2063 printf("2nd-level cache: 1 MB, 4-way set associative, 32 byte line size\n");
2064 break;
2065 case 0x45:
2066 printf("2nd-level cache: 2 MB, 4-way set associative, 32 byte line size\n");
2067 break;
2068 case 0x46:
2069 printf("3rd-level cache: 4 MB, 4-way set associative, 64 byte line size\n");
2070 break;
2071 case 0x47:
2072 printf("3rd-level cache: 8 MB, 8-way set associative, 64 byte line size\n");
2073 break;
2074 case 0x48:
2075 printf("2nd-level cache: 3MByte, 12-way set associative, 64 byte line size\n");
2076 break;
2077 case 0x49:
2078 if (CPUID_TO_FAMILY(cpu_id) == 0xf &&
2079 CPUID_TO_MODEL(cpu_id) == 0x6)
2080 printf("3rd-level cache: 4MB, 16-way set associative, 64-byte line size\n");
2081 else
2082 printf("2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size");
2083 break;
2084 case 0x4a:
2085 printf("3rd-level cache: 6MByte, 12-way set associative, 64 byte line size\n");
2086 break;
2087 case 0x4b:
2088 printf("3rd-level cache: 8MByte, 16-way set associative, 64 byte line size\n");
2089 break;
2090 case 0x4c:
2091 printf("3rd-level cache: 12MByte, 12-way set associative, 64 byte line size\n");
2092 break;
2093 case 0x4d:
2094 printf("3rd-level cache: 16MByte, 16-way set associative, 64 byte line size\n");
2095 break;
2096 case 0x4e:
2097 printf("2nd-level cache: 6MByte, 24-way set associative, 64 byte line size\n");
2098 break;
2099 case 0x4f:
2100 printf("Instruction TLB: 4 KByte pages, 32 entries\n");
2101 break;
2102 case 0x50:
2103 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries\n");
2104 break;
2105 case 0x51:
2106 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries\n");
2107 break;
2108 case 0x52:
2109 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries\n");
2110 break;
2111 case 0x55:
2112 printf("Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries\n");
2113 break;
2114 case 0x56:
2115 printf("Data TLB0: 4 MByte pages, 4-way set associative, 16 entries\n");
2116 break;
2117 case 0x57:
2118 printf("Data TLB0: 4 KByte pages, 4-way associative, 16 entries\n");
2119 break;
2120 case 0x59:
2121 printf("Data TLB0: 4 KByte pages, fully associative, 16 entries\n");
2122 break;
2123 case 0x5a:
2124 printf("Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries\n");
2125 break;
2126 case 0x5b:
2127 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 64 entries\n");
2128 break;
2129 case 0x5c:
2130 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 128 entries\n");
2131 break;
2132 case 0x5d:
2133 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 256 entries\n");
2134 break;
2135 case 0x60:
2136 printf("1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2137 break;
2138 case 0x61:
2139 printf("Instruction TLB: 4 KByte pages, fully associative, 48 entries\n");
2140 break;
2141 case 0x63:
2142 printf("Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries\n");
2143 break;
2144 case 0x64:
2145 printf("Data TLB: 4 KBytes pages, 4-way set associative, 512 entries\n");
2146 break;
2147 case 0x66:
2148 printf("1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2149 break;
2150 case 0x67:
2151 printf("1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2152 break;
2153 case 0x68:
2154 printf("1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size\n");
2155 break;
2156 case 0x6a:
2157 printf("uTLB: 4KByte pages, 8-way set associative, 64 entries\n");
2158 break;
2159 case 0x6b:
2160 printf("DTLB: 4KByte pages, 8-way set associative, 256 entries\n");
2161 break;
2162 case 0x6c:
2163 printf("DTLB: 2M/4M pages, 8-way set associative, 128 entries\n");
2164 break;
2165 case 0x6d:
2166 printf("DTLB: 1 GByte pages, fully associative, 16 entries\n");
2167 break;
2168 case 0x70:
2169 printf("Trace cache: 12K-uops, 8-way set associative\n");
2170 break;
2171 case 0x71:
2172 printf("Trace cache: 16K-uops, 8-way set associative\n");
2173 break;
2174 case 0x72:
2175 printf("Trace cache: 32K-uops, 8-way set associative\n");
2176 break;
2177 case 0x76:
2178 printf("Instruction TLB: 2M/4M pages, fully associative, 8 entries\n");
2179 break;
2180 case 0x78:
2181 printf("2nd-level cache: 1 MB, 4-way set associative, 64-byte line size\n");
2182 break;
2183 case 0x79:
2184 printf("2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2185 break;
2186 case 0x7a:
2187 printf("2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2188 break;
2189 case 0x7b:
2190 printf("2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2191 break;
2192 case 0x7c:
2193 printf("2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2194 break;
2195 case 0x7d:
2196 printf("2nd-level cache: 2-MB, 8-way set associative, 64-byte line size\n");
2197 break;
2198 case 0x7f:
2199 printf("2nd-level cache: 512-KB, 2-way set associative, 64-byte line size\n");
2200 break;
2201 case 0x80:
2202 printf("2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size\n");
2203 break;
2204 case 0x82:
2205 printf("2nd-level cache: 256 KB, 8-way set associative, 32 byte line size\n");
2206 break;
2207 case 0x83:
2208 printf("2nd-level cache: 512 KB, 8-way set associative, 32 byte line size\n");
2209 break;
2210 case 0x84:
2211 printf("2nd-level cache: 1 MB, 8-way set associative, 32 byte line size\n");
2212 break;
2213 case 0x85:
2214 printf("2nd-level cache: 2 MB, 8-way set associative, 32 byte line size\n");
2215 break;
2216 case 0x86:
2217 printf("2nd-level cache: 512 KB, 4-way set associative, 64 byte line size\n");
2218 break;
2219 case 0x87:
2220 printf("2nd-level cache: 1 MB, 8-way set associative, 64 byte line size\n");
2221 break;
2222 case 0xa0:
2223 printf("DTLB: 4k pages, fully associative, 32 entries\n");
2224 break;
2225 case 0xb0:
2226 printf("Instruction TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
2227 break;
2228 case 0xb1:
2229 printf("Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries\n");
2230 break;
2231 case 0xb2:
2232 printf("Instruction TLB: 4KByte pages, 4-way set associative, 64 entries\n");
2233 break;
2234 case 0xb3:
2235 printf("Data TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
2236 break;
2237 case 0xb4:
2238 printf("Data TLB1: 4 KByte pages, 4-way associative, 256 entries\n");
2239 break;
2240 case 0xb5:
2241 printf("Instruction TLB: 4KByte pages, 8-way set associative, 64 entries\n");
2242 break;
2243 case 0xb6:
2244 printf("Instruction TLB: 4KByte pages, 8-way set associative, 128 entries\n");
2245 break;
2246 case 0xba:
2247 printf("Data TLB1: 4 KByte pages, 4-way associative, 64 entries\n");
2248 break;
2249 case 0xc0:
2250 printf("Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries\n");
2251 break;
2252 case 0xc1:
2253 printf("Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries\n");
2254 break;
2255 case 0xc2:
2256 printf("DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries\n");
2257 break;
2258 case 0xc3:
2259 printf("Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries\n");
2260 break;
2261 case 0xc4:
2262 printf("DTLB: 2M/4M Byte pages, 4-way associative, 32 entries\n");
2263 break;
2264 case 0xca:
2265 printf("Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries\n");
2266 break;
2267 case 0xd0:
2268 printf("3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size\n");
2269 break;
2270 case 0xd1:
2271 printf("3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size\n");
2272 break;
2273 case 0xd2:
2274 printf("3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size\n");
2275 break;
2276 case 0xd6:
2277 printf("3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size\n");
2278 break;
2279 case 0xd7:
2280 printf("3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size\n");
2281 break;
2282 case 0xd8:
2283 printf("3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size\n");
2284 break;
2285 case 0xdc:
2286 printf("3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size\n");
2287 break;
2288 case 0xdd:
2289 printf("3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size\n");
2290 break;
2291 case 0xde:
2292 printf("3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size\n");
2293 break;
2294 case 0xe2:
2295 printf("3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size\n");
2296 break;
2297 case 0xe3:
2298 printf("3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size\n");
2299 break;
2300 case 0xe4:
2301 printf("3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size\n");
2302 break;
2303 case 0xea:
2304 printf("3rd-level cache: 12MByte, 24-way set associative, 64 byte line size\n");
2305 break;
2306 case 0xeb:
2307 printf("3rd-level cache: 18MByte, 24-way set associative, 64 byte line size\n");
2308 break;
2309 case 0xec:
2310 printf("3rd-level cache: 24MByte, 24-way set associative, 64 byte line size\n");
2311 break;
2312 case 0xf0:
2313 printf("64-Byte prefetching\n");
2314 break;
2315 case 0xf1:
2316 printf("128-Byte prefetching\n");
2317 break;
2318 }
2319 }
2320
2321 static void
print_svm_info(void)2322 print_svm_info(void)
2323 {
2324 u_int features, regs[4];
2325 uint64_t msr;
2326 int comma;
2327
2328 printf("\n SVM: ");
2329 do_cpuid(0x8000000A, regs);
2330 features = regs[3];
2331
2332 msr = rdmsr(MSR_VM_CR);
2333 if ((msr & VM_CR_SVMDIS) == VM_CR_SVMDIS)
2334 printf("(disabled in BIOS) ");
2335
2336 if (!bootverbose) {
2337 comma = 0;
2338 if (features & (1 << 0)) {
2339 printf("%sNP", comma ? "," : "");
2340 comma = 1;
2341 }
2342 if (features & (1 << 3)) {
2343 printf("%sNRIP", comma ? "," : "");
2344 comma = 1;
2345 }
2346 if (features & (1 << 5)) {
2347 printf("%sVClean", comma ? "," : "");
2348 comma = 1;
2349 }
2350 if (features & (1 << 6)) {
2351 printf("%sAFlush", comma ? "," : "");
2352 comma = 1;
2353 }
2354 if (features & (1 << 7)) {
2355 printf("%sDAssist", comma ? "," : "");
2356 comma = 1;
2357 }
2358 printf("%sNAsids=%d", comma ? "," : "", regs[1]);
2359 return;
2360 }
2361
2362 printf("Features=0x%b", features,
2363 "\020"
2364 "\001NP" /* Nested paging */
2365 "\002LbrVirt" /* LBR virtualization */
2366 "\003SVML" /* SVM lock */
2367 "\004NRIPS" /* NRIP save */
2368 "\005TscRateMsr" /* MSR based TSC rate control */
2369 "\006VmcbClean" /* VMCB clean bits */
2370 "\007FlushByAsid" /* Flush by ASID */
2371 "\010DecodeAssist" /* Decode assist */
2372 "\011<b8>"
2373 "\012<b9>"
2374 "\013PauseFilter" /* PAUSE intercept filter */
2375 "\014EncryptedMcodePatch"
2376 "\015PauseFilterThreshold" /* PAUSE filter threshold */
2377 "\016AVIC" /* virtual interrupt controller */
2378 "\017<b14>"
2379 "\020V_VMSAVE_VMLOAD"
2380 "\021vGIF"
2381 "\022GMET" /* Guest Mode Execute Trap */
2382 "\023<b18>"
2383 "\024<b19>"
2384 "\025GuesSpecCtl" /* Guest Spec_ctl */
2385 "\026<b21>"
2386 "\027<b22>"
2387 "\030<b23>"
2388 "\031<b24>"
2389 "\032<b25>"
2390 "\033<b26>"
2391 "\034<b27>"
2392 "\035<b28>"
2393 "\036<b29>"
2394 "\037<b30>"
2395 "\040<b31>"
2396 );
2397 printf("\nRevision=%d, ASIDs=%d", regs[0] & 0xff, regs[1]);
2398 }
2399
2400 #ifdef __i386__
2401 static void
print_transmeta_info(void)2402 print_transmeta_info(void)
2403 {
2404 u_int regs[4], nreg = 0;
2405
2406 do_cpuid(0x80860000, regs);
2407 nreg = regs[0];
2408 if (nreg >= 0x80860001) {
2409 do_cpuid(0x80860001, regs);
2410 printf(" Processor revision %u.%u.%u.%u\n",
2411 (regs[1] >> 24) & 0xff,
2412 (regs[1] >> 16) & 0xff,
2413 (regs[1] >> 8) & 0xff,
2414 regs[1] & 0xff);
2415 }
2416 if (nreg >= 0x80860002) {
2417 do_cpuid(0x80860002, regs);
2418 printf(" Code Morphing Software revision %u.%u.%u-%u-%u\n",
2419 (regs[1] >> 24) & 0xff,
2420 (regs[1] >> 16) & 0xff,
2421 (regs[1] >> 8) & 0xff,
2422 regs[1] & 0xff,
2423 regs[2]);
2424 }
2425 if (nreg >= 0x80860006) {
2426 char info[65];
2427 do_cpuid(0x80860003, (u_int*) &info[0]);
2428 do_cpuid(0x80860004, (u_int*) &info[16]);
2429 do_cpuid(0x80860005, (u_int*) &info[32]);
2430 do_cpuid(0x80860006, (u_int*) &info[48]);
2431 info[64] = 0;
2432 printf(" %s\n", info);
2433 }
2434 }
2435 #endif
2436
2437 static void
print_via_padlock_info(void)2438 print_via_padlock_info(void)
2439 {
2440 u_int regs[4];
2441
2442 do_cpuid(0xc0000001, regs);
2443 printf("\n VIA Padlock Features=0x%b", regs[3],
2444 "\020"
2445 "\003RNG" /* RNG */
2446 "\007AES" /* ACE */
2447 "\011AES-CTR" /* ACE2 */
2448 "\013SHA1,SHA256" /* PHE */
2449 "\015RSA" /* PMM */
2450 );
2451 }
2452
2453 static uint32_t
vmx_settable(uint64_t basic,int msr,int true_msr)2454 vmx_settable(uint64_t basic, int msr, int true_msr)
2455 {
2456 uint64_t val;
2457
2458 if (basic & (1ULL << 55))
2459 val = rdmsr(true_msr);
2460 else
2461 val = rdmsr(msr);
2462
2463 /* Just report the controls that can be set to 1. */
2464 return (val >> 32);
2465 }
2466
2467 static void
print_vmx_info(void)2468 print_vmx_info(void)
2469 {
2470 uint64_t basic, msr;
2471 uint32_t entry, exit, mask, pin, proc, proc2;
2472 int comma;
2473
2474 printf("\n VT-x: ");
2475 msr = rdmsr(MSR_IA32_FEATURE_CONTROL);
2476 if (!(msr & IA32_FEATURE_CONTROL_VMX_EN))
2477 printf("(disabled in BIOS) ");
2478 basic = rdmsr(MSR_VMX_BASIC);
2479 pin = vmx_settable(basic, MSR_VMX_PINBASED_CTLS,
2480 MSR_VMX_TRUE_PINBASED_CTLS);
2481 proc = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS,
2482 MSR_VMX_TRUE_PROCBASED_CTLS);
2483 if (proc & PROCBASED_SECONDARY_CONTROLS)
2484 proc2 = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS2,
2485 MSR_VMX_PROCBASED_CTLS2);
2486 else
2487 proc2 = 0;
2488 exit = vmx_settable(basic, MSR_VMX_EXIT_CTLS, MSR_VMX_TRUE_EXIT_CTLS);
2489 entry = vmx_settable(basic, MSR_VMX_ENTRY_CTLS, MSR_VMX_TRUE_ENTRY_CTLS);
2490
2491 if (!bootverbose) {
2492 comma = 0;
2493 if (exit & VM_EXIT_SAVE_PAT && exit & VM_EXIT_LOAD_PAT &&
2494 entry & VM_ENTRY_LOAD_PAT) {
2495 printf("%sPAT", comma ? "," : "");
2496 comma = 1;
2497 }
2498 if (proc & PROCBASED_HLT_EXITING) {
2499 printf("%sHLT", comma ? "," : "");
2500 comma = 1;
2501 }
2502 if (proc & PROCBASED_MTF) {
2503 printf("%sMTF", comma ? "," : "");
2504 comma = 1;
2505 }
2506 if (proc & PROCBASED_PAUSE_EXITING) {
2507 printf("%sPAUSE", comma ? "," : "");
2508 comma = 1;
2509 }
2510 if (proc2 & PROCBASED2_ENABLE_EPT) {
2511 printf("%sEPT", comma ? "," : "");
2512 comma = 1;
2513 }
2514 if (proc2 & PROCBASED2_UNRESTRICTED_GUEST) {
2515 printf("%sUG", comma ? "," : "");
2516 comma = 1;
2517 }
2518 if (proc2 & PROCBASED2_ENABLE_VPID) {
2519 printf("%sVPID", comma ? "," : "");
2520 comma = 1;
2521 }
2522 if (proc & PROCBASED_USE_TPR_SHADOW &&
2523 proc2 & PROCBASED2_VIRTUALIZE_APIC_ACCESSES &&
2524 proc2 & PROCBASED2_VIRTUALIZE_X2APIC_MODE &&
2525 proc2 & PROCBASED2_APIC_REGISTER_VIRTUALIZATION &&
2526 proc2 & PROCBASED2_VIRTUAL_INTERRUPT_DELIVERY) {
2527 printf("%sVID", comma ? "," : "");
2528 comma = 1;
2529 if (pin & PINBASED_POSTED_INTERRUPT)
2530 printf(",PostIntr");
2531 }
2532 return;
2533 }
2534
2535 mask = basic >> 32;
2536 printf("Basic Features=0x%b", mask,
2537 "\020"
2538 "\02132PA" /* 32-bit physical addresses */
2539 "\022SMM" /* SMM dual-monitor */
2540 "\027INS/OUTS" /* VM-exit info for INS and OUTS */
2541 "\030TRUE" /* TRUE_CTLS MSRs */
2542 );
2543 printf("\n Pin-Based Controls=0x%b", pin,
2544 "\020"
2545 "\001ExtINT" /* External-interrupt exiting */
2546 "\004NMI" /* NMI exiting */
2547 "\006VNMI" /* Virtual NMIs */
2548 "\007PreTmr" /* Activate VMX-preemption timer */
2549 "\010PostIntr" /* Process posted interrupts */
2550 );
2551 printf("\n Primary Processor Controls=0x%b", proc,
2552 "\020"
2553 "\003INTWIN" /* Interrupt-window exiting */
2554 "\004TSCOff" /* Use TSC offsetting */
2555 "\010HLT" /* HLT exiting */
2556 "\012INVLPG" /* INVLPG exiting */
2557 "\013MWAIT" /* MWAIT exiting */
2558 "\014RDPMC" /* RDPMC exiting */
2559 "\015RDTSC" /* RDTSC exiting */
2560 "\020CR3-LD" /* CR3-load exiting */
2561 "\021CR3-ST" /* CR3-store exiting */
2562 "\024CR8-LD" /* CR8-load exiting */
2563 "\025CR8-ST" /* CR8-store exiting */
2564 "\026TPR" /* Use TPR shadow */
2565 "\027NMIWIN" /* NMI-window exiting */
2566 "\030MOV-DR" /* MOV-DR exiting */
2567 "\031IO" /* Unconditional I/O exiting */
2568 "\032IOmap" /* Use I/O bitmaps */
2569 "\034MTF" /* Monitor trap flag */
2570 "\035MSRmap" /* Use MSR bitmaps */
2571 "\036MONITOR" /* MONITOR exiting */
2572 "\037PAUSE" /* PAUSE exiting */
2573 );
2574 if (proc & PROCBASED_SECONDARY_CONTROLS)
2575 printf("\n Secondary Processor Controls=0x%b", proc2,
2576 "\020"
2577 "\001APIC" /* Virtualize APIC accesses */
2578 "\002EPT" /* Enable EPT */
2579 "\003DT" /* Descriptor-table exiting */
2580 "\004RDTSCP" /* Enable RDTSCP */
2581 "\005x2APIC" /* Virtualize x2APIC mode */
2582 "\006VPID" /* Enable VPID */
2583 "\007WBINVD" /* WBINVD exiting */
2584 "\010UG" /* Unrestricted guest */
2585 "\011APIC-reg" /* APIC-register virtualization */
2586 "\012VID" /* Virtual-interrupt delivery */
2587 "\013PAUSE-loop" /* PAUSE-loop exiting */
2588 "\014RDRAND" /* RDRAND exiting */
2589 "\015INVPCID" /* Enable INVPCID */
2590 "\016VMFUNC" /* Enable VM functions */
2591 "\017VMCS" /* VMCS shadowing */
2592 "\020EPT#VE" /* EPT-violation #VE */
2593 "\021XSAVES" /* Enable XSAVES/XRSTORS */
2594 );
2595 printf("\n Exit Controls=0x%b", mask,
2596 "\020"
2597 "\003DR" /* Save debug controls */
2598 /* Ignore Host address-space size */
2599 "\015PERF" /* Load MSR_PERF_GLOBAL_CTRL */
2600 "\020AckInt" /* Acknowledge interrupt on exit */
2601 "\023PAT-SV" /* Save MSR_PAT */
2602 "\024PAT-LD" /* Load MSR_PAT */
2603 "\025EFER-SV" /* Save MSR_EFER */
2604 "\026EFER-LD" /* Load MSR_EFER */
2605 "\027PTMR-SV" /* Save VMX-preemption timer value */
2606 );
2607 printf("\n Entry Controls=0x%b", mask,
2608 "\020"
2609 "\003DR" /* Save debug controls */
2610 /* Ignore IA-32e mode guest */
2611 /* Ignore Entry to SMM */
2612 /* Ignore Deactivate dual-monitor treatment */
2613 "\016PERF" /* Load MSR_PERF_GLOBAL_CTRL */
2614 "\017PAT" /* Load MSR_PAT */
2615 "\020EFER" /* Load MSR_EFER */
2616 );
2617 if (proc & PROCBASED_SECONDARY_CONTROLS &&
2618 (proc2 & (PROCBASED2_ENABLE_EPT | PROCBASED2_ENABLE_VPID)) != 0) {
2619 msr = rdmsr(MSR_VMX_EPT_VPID_CAP);
2620 mask = msr;
2621 printf("\n EPT Features=0x%b", mask,
2622 "\020"
2623 "\001XO" /* Execute-only translations */
2624 "\007PW4" /* Page-walk length of 4 */
2625 "\011UC" /* EPT paging-structure mem can be UC */
2626 "\017WB" /* EPT paging-structure mem can be WB */
2627 "\0212M" /* EPT PDE can map a 2-Mbyte page */
2628 "\0221G" /* EPT PDPTE can map a 1-Gbyte page */
2629 "\025INVEPT" /* INVEPT is supported */
2630 "\026AD" /* Accessed and dirty flags for EPT */
2631 "\032single" /* INVEPT single-context type */
2632 "\033all" /* INVEPT all-context type */
2633 );
2634 mask = msr >> 32;
2635 printf("\n VPID Features=0x%b", mask,
2636 "\020"
2637 "\001INVVPID" /* INVVPID is supported */
2638 "\011individual" /* INVVPID individual-address type */
2639 "\012single" /* INVVPID single-context type */
2640 "\013all" /* INVVPID all-context type */
2641 /* INVVPID single-context-retaining-globals type */
2642 "\014single-globals"
2643 );
2644 }
2645 }
2646
2647 static void
print_hypervisor_info(void)2648 print_hypervisor_info(void)
2649 {
2650
2651 if (*hv_vendor != '\0')
2652 printf("Hypervisor: Origin = \"%s\"\n", hv_vendor);
2653 }
2654
2655 /*
2656 * Returns the maximum physical address that can be used with the
2657 * current system.
2658 */
2659 vm_paddr_t
cpu_getmaxphyaddr(void)2660 cpu_getmaxphyaddr(void)
2661 {
2662
2663 #if defined(__i386__)
2664 if (!pae_mode)
2665 return (0xffffffff);
2666 #endif
2667 return ((1ULL << cpu_maxphyaddr) - 1);
2668 }
2669