1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (C) 2007-2008 Semihalf, Rafal Jaworowski
5 * Copyright (C) 2006-2007 Semihalf, Piotr Kruszynski
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
22 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
23 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
24 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
25 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
26 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 /*
30 * Freescale integrated Three-Speed Ethernet Controller (TSEC) driver.
31 */
32 #include <sys/cdefs.h>
33 #ifdef HAVE_KERNEL_OPTION_HEADERS
34 #include "opt_device_polling.h"
35 #endif
36
37 #include <sys/param.h>
38 #include <sys/systm.h>
39 #include <sys/bus.h>
40 #include <sys/endian.h>
41 #include <sys/mbuf.h>
42 #include <sys/kernel.h>
43 #include <sys/module.h>
44 #include <sys/socket.h>
45 #include <sys/sockio.h>
46 #include <sys/sysctl.h>
47
48 #include <net/bpf.h>
49 #include <net/ethernet.h>
50 #include <net/if.h>
51 #include <net/if_var.h>
52 #include <net/if_arp.h>
53 #include <net/if_dl.h>
54 #include <net/if_media.h>
55 #include <net/if_types.h>
56 #include <net/if_vlan_var.h>
57
58 #include <netinet/in_systm.h>
59 #include <netinet/in.h>
60 #include <netinet/ip.h>
61
62 #include <machine/bus.h>
63
64 #include <dev/mii/mii.h>
65 #include <dev/mii/miivar.h>
66
67 #include <dev/tsec/if_tsec.h>
68 #include <dev/tsec/if_tsecreg.h>
69
70 static int tsec_alloc_dma_desc(device_t dev, bus_dma_tag_t *dtag,
71 bus_dmamap_t *dmap, bus_size_t dsize, void **vaddr, void *raddr,
72 const char *dname);
73 static void tsec_dma_ctl(struct tsec_softc *sc, int state);
74 static void tsec_encap(if_t ifp, struct tsec_softc *sc,
75 struct mbuf *m0, uint16_t fcb_flags, int *start_tx);
76 static void tsec_free_dma(struct tsec_softc *sc);
77 static void tsec_free_dma_desc(bus_dma_tag_t dtag, bus_dmamap_t dmap, void *vaddr);
78 static int tsec_ifmedia_upd(if_t ifp);
79 static void tsec_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr);
80 static int tsec_new_rxbuf(bus_dma_tag_t tag, bus_dmamap_t map,
81 struct mbuf **mbufp, uint32_t *paddr);
82 static void tsec_map_dma_addr(void *arg, bus_dma_segment_t *segs,
83 int nseg, int error);
84 static void tsec_intrs_ctl(struct tsec_softc *sc, int state);
85 static void tsec_init(void *xsc);
86 static void tsec_init_locked(struct tsec_softc *sc);
87 static int tsec_ioctl(if_t ifp, u_long command, caddr_t data);
88 static void tsec_reset_mac(struct tsec_softc *sc);
89 static void tsec_setfilter(struct tsec_softc *sc);
90 static void tsec_set_mac_address(struct tsec_softc *sc);
91 static void tsec_start(if_t ifp);
92 static void tsec_start_locked(if_t ifp);
93 static void tsec_stop(struct tsec_softc *sc);
94 static void tsec_tick(void *arg);
95 static void tsec_watchdog(struct tsec_softc *sc);
96 static void tsec_add_sysctls(struct tsec_softc *sc);
97 static int tsec_sysctl_ic_time(SYSCTL_HANDLER_ARGS);
98 static int tsec_sysctl_ic_count(SYSCTL_HANDLER_ARGS);
99 static void tsec_set_rxic(struct tsec_softc *sc);
100 static void tsec_set_txic(struct tsec_softc *sc);
101 static int tsec_receive_intr_locked(struct tsec_softc *sc, int count);
102 static void tsec_transmit_intr_locked(struct tsec_softc *sc);
103 static void tsec_error_intr_locked(struct tsec_softc *sc, int count);
104 static void tsec_offload_setup(struct tsec_softc *sc);
105 static void tsec_offload_process_frame(struct tsec_softc *sc,
106 struct mbuf *m);
107 static void tsec_setup_multicast(struct tsec_softc *sc);
108 static int tsec_set_mtu(struct tsec_softc *sc, unsigned int mtu);
109
110 DRIVER_MODULE(miibus, tsec, miibus_driver, 0, 0);
111 MODULE_DEPEND(tsec, ether, 1, 1, 1);
112 MODULE_DEPEND(tsec, miibus, 1, 1, 1);
113
114 struct mtx tsec_phy_mtx;
115
116 int
tsec_attach(struct tsec_softc * sc)117 tsec_attach(struct tsec_softc *sc)
118 {
119 uint8_t hwaddr[ETHER_ADDR_LEN];
120 if_t ifp;
121 int error = 0;
122 int i;
123
124 /* Initialize global (because potentially shared) MII lock */
125 if (!mtx_initialized(&tsec_phy_mtx))
126 mtx_init(&tsec_phy_mtx, "tsec mii", NULL, MTX_DEF);
127
128 /* Reset all TSEC counters */
129 TSEC_TX_RX_COUNTERS_INIT(sc);
130
131 /* Stop DMA engine if enabled by firmware */
132 tsec_dma_ctl(sc, 0);
133
134 /* Reset MAC */
135 tsec_reset_mac(sc);
136
137 /* Disable interrupts for now */
138 tsec_intrs_ctl(sc, 0);
139
140 /* Configure defaults for interrupts coalescing */
141 sc->rx_ic_time = 768;
142 sc->rx_ic_count = 16;
143 sc->tx_ic_time = 768;
144 sc->tx_ic_count = 16;
145 tsec_set_rxic(sc);
146 tsec_set_txic(sc);
147 tsec_add_sysctls(sc);
148
149 /* Allocate a busdma tag and DMA safe memory for TX descriptors. */
150 error = tsec_alloc_dma_desc(sc->dev, &sc->tsec_tx_dtag,
151 &sc->tsec_tx_dmap, sizeof(*sc->tsec_tx_vaddr) * TSEC_TX_NUM_DESC,
152 (void **)&sc->tsec_tx_vaddr, &sc->tsec_tx_raddr, "TX");
153
154 if (error) {
155 tsec_detach(sc);
156 return (ENXIO);
157 }
158
159 /* Allocate a busdma tag and DMA safe memory for RX descriptors. */
160 error = tsec_alloc_dma_desc(sc->dev, &sc->tsec_rx_dtag,
161 &sc->tsec_rx_dmap, sizeof(*sc->tsec_rx_vaddr) * TSEC_RX_NUM_DESC,
162 (void **)&sc->tsec_rx_vaddr, &sc->tsec_rx_raddr, "RX");
163 if (error) {
164 tsec_detach(sc);
165 return (ENXIO);
166 }
167
168 /* Allocate a busdma tag for TX mbufs. */
169 error = bus_dma_tag_create(NULL, /* parent */
170 TSEC_TXBUFFER_ALIGNMENT, 0, /* alignment, boundary */
171 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
172 BUS_SPACE_MAXADDR, /* highaddr */
173 NULL, NULL, /* filtfunc, filtfuncarg */
174 MCLBYTES * (TSEC_TX_NUM_DESC - 1), /* maxsize */
175 TSEC_TX_MAX_DMA_SEGS, /* nsegments */
176 MCLBYTES, 0, /* maxsegsz, flags */
177 NULL, NULL, /* lockfunc, lockfuncarg */
178 &sc->tsec_tx_mtag); /* dmat */
179 if (error) {
180 device_printf(sc->dev, "failed to allocate busdma tag "
181 "(tx mbufs)\n");
182 tsec_detach(sc);
183 return (ENXIO);
184 }
185
186 /* Allocate a busdma tag for RX mbufs. */
187 error = bus_dma_tag_create(NULL, /* parent */
188 TSEC_RXBUFFER_ALIGNMENT, 0, /* alignment, boundary */
189 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
190 BUS_SPACE_MAXADDR, /* highaddr */
191 NULL, NULL, /* filtfunc, filtfuncarg */
192 MCLBYTES, /* maxsize */
193 1, /* nsegments */
194 MCLBYTES, 0, /* maxsegsz, flags */
195 NULL, NULL, /* lockfunc, lockfuncarg */
196 &sc->tsec_rx_mtag); /* dmat */
197 if (error) {
198 device_printf(sc->dev, "failed to allocate busdma tag "
199 "(rx mbufs)\n");
200 tsec_detach(sc);
201 return (ENXIO);
202 }
203
204 /* Create TX busdma maps */
205 for (i = 0; i < TSEC_TX_NUM_DESC; i++) {
206 error = bus_dmamap_create(sc->tsec_tx_mtag, 0,
207 &sc->tx_bufmap[i].map);
208 if (error) {
209 device_printf(sc->dev, "failed to init TX ring\n");
210 tsec_detach(sc);
211 return (ENXIO);
212 }
213 sc->tx_bufmap[i].map_initialized = 1;
214 }
215
216 /* Create RX busdma maps and zero mbuf handlers */
217 for (i = 0; i < TSEC_RX_NUM_DESC; i++) {
218 error = bus_dmamap_create(sc->tsec_rx_mtag, 0,
219 &sc->rx_data[i].map);
220 if (error) {
221 device_printf(sc->dev, "failed to init RX ring\n");
222 tsec_detach(sc);
223 return (ENXIO);
224 }
225 sc->rx_data[i].mbuf = NULL;
226 }
227
228 /* Create mbufs for RX buffers */
229 for (i = 0; i < TSEC_RX_NUM_DESC; i++) {
230 error = tsec_new_rxbuf(sc->tsec_rx_mtag, sc->rx_data[i].map,
231 &sc->rx_data[i].mbuf, &sc->rx_data[i].paddr);
232 if (error) {
233 device_printf(sc->dev, "can't load rx DMA map %d, "
234 "error = %d\n", i, error);
235 tsec_detach(sc);
236 return (error);
237 }
238 }
239
240 /* Create network interface for upper layers */
241 ifp = sc->tsec_ifp = if_alloc(IFT_ETHER);
242 if_setsoftc(ifp, sc);
243 if_initname(ifp, device_get_name(sc->dev), device_get_unit(sc->dev));
244 if_setflags(ifp, IFF_SIMPLEX | IFF_MULTICAST | IFF_BROADCAST);
245 if_setinitfn(ifp, tsec_init);
246 if_setstartfn(ifp, tsec_start);
247 if_setioctlfn(ifp, tsec_ioctl);
248
249 if_setsendqlen(ifp, TSEC_TX_NUM_DESC - 1);
250 if_setsendqready(ifp);
251
252 if_setcapabilities(ifp, IFCAP_VLAN_MTU);
253 if (sc->is_etsec)
254 if_setcapabilitiesbit(ifp, IFCAP_HWCSUM, 0);
255
256 if_setcapenable(ifp, if_getcapabilities(ifp));
257
258 #ifdef DEVICE_POLLING
259 /* Advertise that polling is supported */
260 if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0);
261 #endif
262
263 /* Attach PHY(s) */
264 error = mii_attach(sc->dev, &sc->tsec_miibus, ifp, tsec_ifmedia_upd,
265 tsec_ifmedia_sts, BMSR_DEFCAPMASK, sc->phyaddr, MII_OFFSET_ANY,
266 0);
267 if (error) {
268 device_printf(sc->dev, "attaching PHYs failed\n");
269 if_free(ifp);
270 sc->tsec_ifp = NULL;
271 tsec_detach(sc);
272 return (error);
273 }
274 sc->tsec_mii = device_get_softc(sc->tsec_miibus);
275
276 /* Set MAC address */
277 tsec_get_hwaddr(sc, hwaddr);
278 ether_ifattach(ifp, hwaddr);
279
280 return (0);
281 }
282
283 int
tsec_detach(struct tsec_softc * sc)284 tsec_detach(struct tsec_softc *sc)
285 {
286
287 if (sc->tsec_ifp != NULL) {
288 #ifdef DEVICE_POLLING
289 if (if_getcapenable(sc->tsec_ifp) & IFCAP_POLLING)
290 ether_poll_deregister(sc->tsec_ifp);
291 #endif
292
293 /* Stop TSEC controller and free TX queue */
294 if (sc->sc_rres)
295 tsec_shutdown(sc->dev);
296
297 /* Detach network interface */
298 ether_ifdetach(sc->tsec_ifp);
299 if_free(sc->tsec_ifp);
300 sc->tsec_ifp = NULL;
301 }
302
303 /* Free DMA resources */
304 tsec_free_dma(sc);
305
306 return (0);
307 }
308
309 int
tsec_shutdown(device_t dev)310 tsec_shutdown(device_t dev)
311 {
312 struct tsec_softc *sc;
313
314 sc = device_get_softc(dev);
315
316 TSEC_GLOBAL_LOCK(sc);
317 tsec_stop(sc);
318 TSEC_GLOBAL_UNLOCK(sc);
319 return (0);
320 }
321
322 int
tsec_suspend(device_t dev)323 tsec_suspend(device_t dev)
324 {
325
326 /* TODO not implemented! */
327 return (0);
328 }
329
330 int
tsec_resume(device_t dev)331 tsec_resume(device_t dev)
332 {
333
334 /* TODO not implemented! */
335 return (0);
336 }
337
338 static void
tsec_init(void * xsc)339 tsec_init(void *xsc)
340 {
341 struct tsec_softc *sc = xsc;
342
343 TSEC_GLOBAL_LOCK(sc);
344 tsec_init_locked(sc);
345 TSEC_GLOBAL_UNLOCK(sc);
346 }
347
348 static int
tsec_mii_wait(struct tsec_softc * sc,uint32_t flags)349 tsec_mii_wait(struct tsec_softc *sc, uint32_t flags)
350 {
351 int timeout;
352
353 /*
354 * The status indicators are not set immediately after a command.
355 * Discard the first value.
356 */
357 TSEC_PHY_READ(sc, TSEC_REG_MIIMIND);
358
359 timeout = TSEC_READ_RETRY;
360 while ((TSEC_PHY_READ(sc, TSEC_REG_MIIMIND) & flags) && --timeout)
361 DELAY(TSEC_READ_DELAY);
362
363 return (timeout == 0);
364 }
365
366 static void
tsec_init_locked(struct tsec_softc * sc)367 tsec_init_locked(struct tsec_softc *sc)
368 {
369 struct tsec_desc *tx_desc = sc->tsec_tx_vaddr;
370 struct tsec_desc *rx_desc = sc->tsec_rx_vaddr;
371 if_t ifp = sc->tsec_ifp;
372 uint32_t val, i;
373 int timeout;
374
375 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
376 return;
377
378 TSEC_GLOBAL_LOCK_ASSERT(sc);
379 tsec_stop(sc);
380
381 /*
382 * These steps are according to the MPC8555E PowerQUICCIII RM:
383 * 14.7 Initialization/Application Information
384 */
385
386 /* Step 1: soft reset MAC */
387 tsec_reset_mac(sc);
388
389 /* Step 2: Initialize MACCFG2 */
390 TSEC_WRITE(sc, TSEC_REG_MACCFG2,
391 TSEC_MACCFG2_FULLDUPLEX | /* Full Duplex = 1 */
392 TSEC_MACCFG2_PADCRC | /* PAD/CRC append */
393 TSEC_MACCFG2_GMII | /* I/F Mode bit */
394 TSEC_MACCFG2_PRECNT /* Preamble count = 7 */
395 );
396
397 /* Step 3: Initialize ECNTRL
398 * While the documentation states that R100M is ignored if RPM is
399 * not set, it does seem to be needed to get the orange boxes to
400 * work (which have a Marvell 88E1111 PHY). Go figure.
401 */
402
403 /*
404 * XXX kludge - use circumstancial evidence to program ECNTRL
405 * correctly. Ideally we need some board information to guide
406 * us here.
407 */
408 i = TSEC_READ(sc, TSEC_REG_ID2);
409 val = (i & 0xffff)
410 ? (TSEC_ECNTRL_TBIM | TSEC_ECNTRL_SGMIIM) /* Sumatra */
411 : TSEC_ECNTRL_R100M; /* Orange + CDS */
412 TSEC_WRITE(sc, TSEC_REG_ECNTRL, TSEC_ECNTRL_STEN | val);
413
414 /* Step 4: Initialize MAC station address */
415 tsec_set_mac_address(sc);
416
417 /*
418 * Step 5: Assign a Physical address to the TBI so as to not conflict
419 * with the external PHY physical address
420 */
421 TSEC_WRITE(sc, TSEC_REG_TBIPA, 5);
422
423 TSEC_PHY_LOCK(sc);
424
425 /* Step 6: Reset the management interface */
426 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCFG, TSEC_MIIMCFG_RESETMGMT);
427
428 /* Step 7: Setup the MII Mgmt clock speed */
429 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCFG, TSEC_MIIMCFG_CLKDIV28);
430
431 /* Step 8: Read MII Mgmt indicator register and check for Busy = 0 */
432 timeout = tsec_mii_wait(sc, TSEC_MIIMIND_BUSY);
433
434 TSEC_PHY_UNLOCK(sc);
435 if (timeout) {
436 if_printf(ifp, "tsec_init_locked(): Mgmt busy timeout\n");
437 return;
438 }
439
440 /* Step 9: Setup the MII Mgmt */
441 mii_mediachg(sc->tsec_mii);
442
443 /* Step 10: Clear IEVENT register */
444 TSEC_WRITE(sc, TSEC_REG_IEVENT, 0xffffffff);
445
446 /* Step 11: Enable interrupts */
447 #ifdef DEVICE_POLLING
448 /*
449 * ...only if polling is not turned on. Disable interrupts explicitly
450 * if polling is enabled.
451 */
452 if (if_getcapenable(ifp) & IFCAP_POLLING )
453 tsec_intrs_ctl(sc, 0);
454 else
455 #endif /* DEVICE_POLLING */
456 tsec_intrs_ctl(sc, 1);
457
458 /* Step 12: Initialize IADDRn */
459 TSEC_WRITE(sc, TSEC_REG_IADDR0, 0);
460 TSEC_WRITE(sc, TSEC_REG_IADDR1, 0);
461 TSEC_WRITE(sc, TSEC_REG_IADDR2, 0);
462 TSEC_WRITE(sc, TSEC_REG_IADDR3, 0);
463 TSEC_WRITE(sc, TSEC_REG_IADDR4, 0);
464 TSEC_WRITE(sc, TSEC_REG_IADDR5, 0);
465 TSEC_WRITE(sc, TSEC_REG_IADDR6, 0);
466 TSEC_WRITE(sc, TSEC_REG_IADDR7, 0);
467
468 /* Step 13: Initialize GADDRn */
469 TSEC_WRITE(sc, TSEC_REG_GADDR0, 0);
470 TSEC_WRITE(sc, TSEC_REG_GADDR1, 0);
471 TSEC_WRITE(sc, TSEC_REG_GADDR2, 0);
472 TSEC_WRITE(sc, TSEC_REG_GADDR3, 0);
473 TSEC_WRITE(sc, TSEC_REG_GADDR4, 0);
474 TSEC_WRITE(sc, TSEC_REG_GADDR5, 0);
475 TSEC_WRITE(sc, TSEC_REG_GADDR6, 0);
476 TSEC_WRITE(sc, TSEC_REG_GADDR7, 0);
477
478 /* Step 14: Initialize RCTRL */
479 TSEC_WRITE(sc, TSEC_REG_RCTRL, 0);
480
481 /* Step 15: Initialize DMACTRL */
482 tsec_dma_ctl(sc, 1);
483
484 /* Step 16: Initialize FIFO_PAUSE_CTRL */
485 TSEC_WRITE(sc, TSEC_REG_FIFO_PAUSE_CTRL, TSEC_FIFO_PAUSE_CTRL_EN);
486
487 /*
488 * Step 17: Initialize transmit/receive descriptor rings.
489 * Initialize TBASE and RBASE.
490 */
491 TSEC_WRITE(sc, TSEC_REG_TBASE, sc->tsec_tx_raddr);
492 TSEC_WRITE(sc, TSEC_REG_RBASE, sc->tsec_rx_raddr);
493
494 for (i = 0; i < TSEC_TX_NUM_DESC; i++) {
495 tx_desc[i].bufptr = 0;
496 tx_desc[i].length = 0;
497 tx_desc[i].flags = ((i == TSEC_TX_NUM_DESC - 1) ?
498 TSEC_TXBD_W : 0);
499 }
500 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
501 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
502
503 for (i = 0; i < TSEC_RX_NUM_DESC; i++) {
504 rx_desc[i].bufptr = sc->rx_data[i].paddr;
505 rx_desc[i].length = 0;
506 rx_desc[i].flags = TSEC_RXBD_E | TSEC_RXBD_I |
507 ((i == TSEC_RX_NUM_DESC - 1) ? TSEC_RXBD_W : 0);
508 }
509 bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap,
510 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
511
512 /* Step 18: Initialize the maximum receive buffer length */
513 TSEC_WRITE(sc, TSEC_REG_MRBLR, MCLBYTES);
514
515 /* Step 19: Configure ethernet frame sizes */
516 TSEC_WRITE(sc, TSEC_REG_MINFLR, TSEC_MIN_FRAME_SIZE);
517 tsec_set_mtu(sc, if_getmtu(ifp));
518
519 /* Step 20: Enable Rx and RxBD sdata snooping */
520 TSEC_WRITE(sc, TSEC_REG_ATTR, TSEC_ATTR_RDSEN | TSEC_ATTR_RBDSEN);
521 TSEC_WRITE(sc, TSEC_REG_ATTRELI, 0);
522
523 /* Step 21: Reset collision counters in hardware */
524 TSEC_WRITE(sc, TSEC_REG_MON_TSCL, 0);
525 TSEC_WRITE(sc, TSEC_REG_MON_TMCL, 0);
526 TSEC_WRITE(sc, TSEC_REG_MON_TLCL, 0);
527 TSEC_WRITE(sc, TSEC_REG_MON_TXCL, 0);
528 TSEC_WRITE(sc, TSEC_REG_MON_TNCL, 0);
529
530 /* Step 22: Mask all CAM interrupts */
531 TSEC_WRITE(sc, TSEC_REG_MON_CAM1, 0xffffffff);
532 TSEC_WRITE(sc, TSEC_REG_MON_CAM2, 0xffffffff);
533
534 /* Step 23: Enable Rx and Tx */
535 val = TSEC_READ(sc, TSEC_REG_MACCFG1);
536 val |= (TSEC_MACCFG1_RX_EN | TSEC_MACCFG1_TX_EN);
537 TSEC_WRITE(sc, TSEC_REG_MACCFG1, val);
538
539 /* Step 24: Reset TSEC counters for Tx and Rx rings */
540 TSEC_TX_RX_COUNTERS_INIT(sc);
541
542 /* Step 25: Setup TCP/IP Off-Load engine */
543 if (sc->is_etsec)
544 tsec_offload_setup(sc);
545
546 /* Step 26: Setup multicast filters */
547 tsec_setup_multicast(sc);
548
549 /* Step 27: Activate network interface */
550 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
551 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
552 sc->tsec_if_flags = if_getflags(ifp);
553 sc->tsec_watchdog = 0;
554
555 /* Schedule watchdog timeout */
556 callout_reset(&sc->tsec_callout, hz, tsec_tick, sc);
557 }
558
559 static void
tsec_set_mac_address(struct tsec_softc * sc)560 tsec_set_mac_address(struct tsec_softc *sc)
561 {
562 uint32_t macbuf[2] = { 0, 0 };
563 char *macbufp, *curmac;
564 int i;
565
566 TSEC_GLOBAL_LOCK_ASSERT(sc);
567
568 KASSERT((ETHER_ADDR_LEN <= sizeof(macbuf)),
569 ("tsec_set_mac_address: (%d <= %zd", ETHER_ADDR_LEN,
570 sizeof(macbuf)));
571
572 macbufp = (char *)macbuf;
573 curmac = (char *)if_getlladdr(sc->tsec_ifp);
574
575 /* Correct order of MAC address bytes */
576 for (i = 1; i <= ETHER_ADDR_LEN; i++)
577 macbufp[ETHER_ADDR_LEN-i] = curmac[i-1];
578
579 /* Initialize MAC station address MACSTNADDR2 and MACSTNADDR1 */
580 TSEC_WRITE(sc, TSEC_REG_MACSTNADDR2, macbuf[1]);
581 TSEC_WRITE(sc, TSEC_REG_MACSTNADDR1, macbuf[0]);
582 }
583
584 /*
585 * DMA control function, if argument state is:
586 * 0 - DMA engine will be disabled
587 * 1 - DMA engine will be enabled
588 */
589 static void
tsec_dma_ctl(struct tsec_softc * sc,int state)590 tsec_dma_ctl(struct tsec_softc *sc, int state)
591 {
592 device_t dev;
593 uint32_t dma_flags, timeout;
594
595 dev = sc->dev;
596
597 dma_flags = TSEC_READ(sc, TSEC_REG_DMACTRL);
598
599 switch (state) {
600 case 0:
601 /* Temporarily clear stop graceful stop bits. */
602 tsec_dma_ctl(sc, 1000);
603
604 /* Set it again */
605 dma_flags |= (TSEC_DMACTRL_GRS | TSEC_DMACTRL_GTS);
606 break;
607 case 1000:
608 case 1:
609 /* Set write with response (WWR), wait (WOP) and snoop bits */
610 dma_flags |= (TSEC_DMACTRL_TDSEN | TSEC_DMACTRL_TBDSEN |
611 DMACTRL_WWR | DMACTRL_WOP);
612
613 /* Clear graceful stop bits */
614 dma_flags &= ~(TSEC_DMACTRL_GRS | TSEC_DMACTRL_GTS);
615 break;
616 default:
617 device_printf(dev, "tsec_dma_ctl(): unknown state value: %d\n",
618 state);
619 }
620
621 TSEC_WRITE(sc, TSEC_REG_DMACTRL, dma_flags);
622
623 switch (state) {
624 case 0:
625 /* Wait for DMA stop */
626 timeout = TSEC_READ_RETRY;
627 while (--timeout && (!(TSEC_READ(sc, TSEC_REG_IEVENT) &
628 (TSEC_IEVENT_GRSC | TSEC_IEVENT_GTSC))))
629 DELAY(TSEC_READ_DELAY);
630
631 if (timeout == 0)
632 device_printf(dev, "tsec_dma_ctl(): timeout!\n");
633 break;
634 case 1:
635 /* Restart transmission function */
636 TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT);
637 }
638 }
639
640 /*
641 * Interrupts control function, if argument state is:
642 * 0 - all TSEC interrupts will be masked
643 * 1 - all TSEC interrupts will be unmasked
644 */
645 static void
tsec_intrs_ctl(struct tsec_softc * sc,int state)646 tsec_intrs_ctl(struct tsec_softc *sc, int state)
647 {
648 device_t dev;
649
650 dev = sc->dev;
651
652 switch (state) {
653 case 0:
654 TSEC_WRITE(sc, TSEC_REG_IMASK, 0);
655 break;
656 case 1:
657 TSEC_WRITE(sc, TSEC_REG_IMASK, TSEC_IMASK_BREN |
658 TSEC_IMASK_RXCEN | TSEC_IMASK_BSYEN | TSEC_IMASK_EBERREN |
659 TSEC_IMASK_BTEN | TSEC_IMASK_TXEEN | TSEC_IMASK_TXBEN |
660 TSEC_IMASK_TXFEN | TSEC_IMASK_XFUNEN | TSEC_IMASK_RXFEN);
661 break;
662 default:
663 device_printf(dev, "tsec_intrs_ctl(): unknown state value: %d\n",
664 state);
665 }
666 }
667
668 static void
tsec_reset_mac(struct tsec_softc * sc)669 tsec_reset_mac(struct tsec_softc *sc)
670 {
671 uint32_t maccfg1_flags;
672
673 /* Set soft reset bit */
674 maccfg1_flags = TSEC_READ(sc, TSEC_REG_MACCFG1);
675 maccfg1_flags |= TSEC_MACCFG1_SOFT_RESET;
676 TSEC_WRITE(sc, TSEC_REG_MACCFG1, maccfg1_flags);
677
678 /* Clear soft reset bit */
679 maccfg1_flags = TSEC_READ(sc, TSEC_REG_MACCFG1);
680 maccfg1_flags &= ~TSEC_MACCFG1_SOFT_RESET;
681 TSEC_WRITE(sc, TSEC_REG_MACCFG1, maccfg1_flags);
682 }
683
684 static void
tsec_watchdog(struct tsec_softc * sc)685 tsec_watchdog(struct tsec_softc *sc)
686 {
687 if_t ifp;
688
689 TSEC_GLOBAL_LOCK_ASSERT(sc);
690
691 if (sc->tsec_watchdog == 0 || --sc->tsec_watchdog > 0)
692 return;
693
694 ifp = sc->tsec_ifp;
695 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
696 if_printf(ifp, "watchdog timeout\n");
697
698 tsec_stop(sc);
699 tsec_init_locked(sc);
700 }
701
702 static void
tsec_start(if_t ifp)703 tsec_start(if_t ifp)
704 {
705 struct tsec_softc *sc = if_getsoftc(ifp);
706
707 TSEC_TRANSMIT_LOCK(sc);
708 tsec_start_locked(ifp);
709 TSEC_TRANSMIT_UNLOCK(sc);
710 }
711
712 static void
tsec_start_locked(if_t ifp)713 tsec_start_locked(if_t ifp)
714 {
715 struct tsec_softc *sc;
716 struct mbuf *m0;
717 struct tsec_tx_fcb *tx_fcb;
718 int csum_flags;
719 int start_tx;
720 uint16_t fcb_flags;
721
722 sc = if_getsoftc(ifp);
723 start_tx = 0;
724
725 TSEC_TRANSMIT_LOCK_ASSERT(sc);
726
727 if (sc->tsec_link == 0)
728 return;
729
730 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
731 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
732
733 for (;;) {
734 if (TSEC_FREE_TX_DESC(sc) < TSEC_TX_MAX_DMA_SEGS) {
735 /* No free descriptors */
736 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
737 break;
738 }
739
740 /* Get packet from the queue */
741 m0 = if_dequeue(ifp);
742 if (m0 == NULL)
743 break;
744
745 /* Insert TCP/IP Off-load frame control block */
746 fcb_flags = 0;
747 csum_flags = m0->m_pkthdr.csum_flags;
748 if (csum_flags) {
749 M_PREPEND(m0, sizeof(struct tsec_tx_fcb), M_NOWAIT);
750 if (m0 == NULL)
751 break;
752
753 if (csum_flags & CSUM_IP)
754 fcb_flags |= TSEC_TX_FCB_IP4 |
755 TSEC_TX_FCB_CSUM_IP;
756
757 if (csum_flags & CSUM_TCP)
758 fcb_flags |= TSEC_TX_FCB_TCP |
759 TSEC_TX_FCB_CSUM_TCP_UDP;
760
761 if (csum_flags & CSUM_UDP)
762 fcb_flags |= TSEC_TX_FCB_UDP |
763 TSEC_TX_FCB_CSUM_TCP_UDP;
764
765 tx_fcb = mtod(m0, struct tsec_tx_fcb *);
766 tx_fcb->flags = fcb_flags;
767 tx_fcb->l3_offset = ETHER_HDR_LEN;
768 tx_fcb->l4_offset = sizeof(struct ip);
769 }
770
771 tsec_encap(ifp, sc, m0, fcb_flags, &start_tx);
772 }
773 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
774 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
775
776 if (start_tx) {
777 /* Enable transmitter and watchdog timer */
778 TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT);
779 sc->tsec_watchdog = 5;
780 }
781 }
782
783 static void
tsec_encap(if_t ifp,struct tsec_softc * sc,struct mbuf * m0,uint16_t fcb_flags,int * start_tx)784 tsec_encap(if_t ifp, struct tsec_softc *sc, struct mbuf *m0,
785 uint16_t fcb_flags, int *start_tx)
786 {
787 bus_dma_segment_t segs[TSEC_TX_MAX_DMA_SEGS];
788 int error, i, nsegs;
789 struct tsec_bufmap *tx_bufmap;
790 uint32_t tx_idx;
791 uint16_t flags;
792
793 TSEC_TRANSMIT_LOCK_ASSERT(sc);
794
795 tx_idx = sc->tx_idx_head;
796 tx_bufmap = &sc->tx_bufmap[tx_idx];
797
798 /* Create mapping in DMA memory */
799 error = bus_dmamap_load_mbuf_sg(sc->tsec_tx_mtag, tx_bufmap->map, m0,
800 segs, &nsegs, BUS_DMA_NOWAIT);
801 if (error == EFBIG) {
802 /* Too many segments! Defrag and try again. */
803 struct mbuf *m = m_defrag(m0, M_NOWAIT);
804
805 if (m == NULL) {
806 m_freem(m0);
807 return;
808 }
809 m0 = m;
810 error = bus_dmamap_load_mbuf_sg(sc->tsec_tx_mtag,
811 tx_bufmap->map, m0, segs, &nsegs, BUS_DMA_NOWAIT);
812 }
813 if (error != 0) {
814 /* Give up. */
815 m_freem(m0);
816 return;
817 }
818
819 bus_dmamap_sync(sc->tsec_tx_mtag, tx_bufmap->map,
820 BUS_DMASYNC_PREWRITE);
821 tx_bufmap->mbuf = m0;
822
823 /*
824 * Fill in the TX descriptors back to front so that READY bit in first
825 * descriptor is set last.
826 */
827 tx_idx = (tx_idx + (uint32_t)nsegs) & (TSEC_TX_NUM_DESC - 1);
828 sc->tx_idx_head = tx_idx;
829 flags = TSEC_TXBD_L | TSEC_TXBD_I | TSEC_TXBD_R | TSEC_TXBD_TC;
830 for (i = nsegs - 1; i >= 0; i--) {
831 struct tsec_desc *tx_desc;
832
833 tx_idx = (tx_idx - 1) & (TSEC_TX_NUM_DESC - 1);
834 tx_desc = &sc->tsec_tx_vaddr[tx_idx];
835 tx_desc->length = segs[i].ds_len;
836 tx_desc->bufptr = segs[i].ds_addr;
837
838 if (i == 0) {
839 wmb();
840
841 if (fcb_flags != 0)
842 flags |= TSEC_TXBD_TOE;
843 }
844
845 /*
846 * Set flags:
847 * - wrap
848 * - checksum
849 * - ready to send
850 * - transmit the CRC sequence after the last data byte
851 * - interrupt after the last buffer
852 */
853 tx_desc->flags = (tx_idx == (TSEC_TX_NUM_DESC - 1) ?
854 TSEC_TXBD_W : 0) | flags;
855
856 flags &= ~(TSEC_TXBD_L | TSEC_TXBD_I);
857 }
858
859 BPF_MTAP(ifp, m0);
860 *start_tx = 1;
861 }
862
863 static void
tsec_setfilter(struct tsec_softc * sc)864 tsec_setfilter(struct tsec_softc *sc)
865 {
866 if_t ifp;
867 uint32_t flags;
868
869 ifp = sc->tsec_ifp;
870 flags = TSEC_READ(sc, TSEC_REG_RCTRL);
871
872 /* Promiscuous mode */
873 if (if_getflags(ifp) & IFF_PROMISC)
874 flags |= TSEC_RCTRL_PROM;
875 else
876 flags &= ~TSEC_RCTRL_PROM;
877
878 TSEC_WRITE(sc, TSEC_REG_RCTRL, flags);
879 }
880
881 #ifdef DEVICE_POLLING
882 static poll_handler_t tsec_poll;
883
884 static int
tsec_poll(if_t ifp,enum poll_cmd cmd,int count)885 tsec_poll(if_t ifp, enum poll_cmd cmd, int count)
886 {
887 uint32_t ie;
888 struct tsec_softc *sc = if_getsoftc(ifp);
889 int rx_npkts;
890
891 rx_npkts = 0;
892
893 TSEC_GLOBAL_LOCK(sc);
894 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) {
895 TSEC_GLOBAL_UNLOCK(sc);
896 return (rx_npkts);
897 }
898
899 if (cmd == POLL_AND_CHECK_STATUS) {
900 tsec_error_intr_locked(sc, count);
901
902 /* Clear all events reported */
903 ie = TSEC_READ(sc, TSEC_REG_IEVENT);
904 TSEC_WRITE(sc, TSEC_REG_IEVENT, ie);
905 }
906
907 tsec_transmit_intr_locked(sc);
908
909 TSEC_GLOBAL_TO_RECEIVE_LOCK(sc);
910
911 rx_npkts = tsec_receive_intr_locked(sc, count);
912
913 TSEC_RECEIVE_UNLOCK(sc);
914
915 return (rx_npkts);
916 }
917 #endif /* DEVICE_POLLING */
918
919 static int
tsec_ioctl(if_t ifp,u_long command,caddr_t data)920 tsec_ioctl(if_t ifp, u_long command, caddr_t data)
921 {
922 struct tsec_softc *sc = if_getsoftc(ifp);
923 struct ifreq *ifr = (struct ifreq *)data;
924 int mask, error = 0;
925
926 switch (command) {
927 case SIOCSIFMTU:
928 TSEC_GLOBAL_LOCK(sc);
929 if (tsec_set_mtu(sc, ifr->ifr_mtu))
930 if_setmtu(ifp, ifr->ifr_mtu);
931 else
932 error = EINVAL;
933 TSEC_GLOBAL_UNLOCK(sc);
934 break;
935 case SIOCSIFFLAGS:
936 TSEC_GLOBAL_LOCK(sc);
937 if (if_getflags(ifp) & IFF_UP) {
938 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
939 if ((sc->tsec_if_flags ^ if_getflags(ifp)) &
940 IFF_PROMISC)
941 tsec_setfilter(sc);
942
943 if ((sc->tsec_if_flags ^ if_getflags(ifp)) &
944 IFF_ALLMULTI)
945 tsec_setup_multicast(sc);
946 } else
947 tsec_init_locked(sc);
948 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
949 tsec_stop(sc);
950
951 sc->tsec_if_flags = if_getflags(ifp);
952 TSEC_GLOBAL_UNLOCK(sc);
953 break;
954 case SIOCADDMULTI:
955 case SIOCDELMULTI:
956 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
957 TSEC_GLOBAL_LOCK(sc);
958 tsec_setup_multicast(sc);
959 TSEC_GLOBAL_UNLOCK(sc);
960 }
961 case SIOCGIFMEDIA:
962 case SIOCSIFMEDIA:
963 error = ifmedia_ioctl(ifp, ifr, &sc->tsec_mii->mii_media,
964 command);
965 break;
966 case SIOCSIFCAP:
967 mask = if_getcapenable(ifp) ^ ifr->ifr_reqcap;
968 if ((mask & IFCAP_HWCSUM) && sc->is_etsec) {
969 TSEC_GLOBAL_LOCK(sc);
970 if_setcapenablebit(ifp, 0, IFCAP_HWCSUM);
971 if_setcapenablebit(ifp, IFCAP_HWCSUM & ifr->ifr_reqcap, 0);
972 tsec_offload_setup(sc);
973 TSEC_GLOBAL_UNLOCK(sc);
974 }
975 #ifdef DEVICE_POLLING
976 if (mask & IFCAP_POLLING) {
977 if (ifr->ifr_reqcap & IFCAP_POLLING) {
978 error = ether_poll_register(tsec_poll, ifp);
979 if (error)
980 return (error);
981
982 TSEC_GLOBAL_LOCK(sc);
983 /* Disable interrupts */
984 tsec_intrs_ctl(sc, 0);
985 if_setcapenablebit(ifp, IFCAP_POLLING, 0);
986 TSEC_GLOBAL_UNLOCK(sc);
987 } else {
988 error = ether_poll_deregister(ifp);
989 TSEC_GLOBAL_LOCK(sc);
990 /* Enable interrupts */
991 tsec_intrs_ctl(sc, 1);
992 if_setcapenablebit(ifp, 0, IFCAP_POLLING);
993 TSEC_GLOBAL_UNLOCK(sc);
994 }
995 }
996 #endif
997 break;
998
999 default:
1000 error = ether_ioctl(ifp, command, data);
1001 }
1002
1003 /* Flush buffers if not empty */
1004 if (if_getflags(ifp) & IFF_UP)
1005 tsec_start(ifp);
1006 return (error);
1007 }
1008
1009 static int
tsec_ifmedia_upd(if_t ifp)1010 tsec_ifmedia_upd(if_t ifp)
1011 {
1012 struct tsec_softc *sc = if_getsoftc(ifp);
1013 struct mii_data *mii;
1014
1015 TSEC_TRANSMIT_LOCK(sc);
1016
1017 mii = sc->tsec_mii;
1018 mii_mediachg(mii);
1019
1020 TSEC_TRANSMIT_UNLOCK(sc);
1021 return (0);
1022 }
1023
1024 static void
tsec_ifmedia_sts(if_t ifp,struct ifmediareq * ifmr)1025 tsec_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr)
1026 {
1027 struct tsec_softc *sc = if_getsoftc(ifp);
1028 struct mii_data *mii;
1029
1030 TSEC_TRANSMIT_LOCK(sc);
1031
1032 mii = sc->tsec_mii;
1033 mii_pollstat(mii);
1034
1035 ifmr->ifm_active = mii->mii_media_active;
1036 ifmr->ifm_status = mii->mii_media_status;
1037
1038 TSEC_TRANSMIT_UNLOCK(sc);
1039 }
1040
1041 static int
tsec_new_rxbuf(bus_dma_tag_t tag,bus_dmamap_t map,struct mbuf ** mbufp,uint32_t * paddr)1042 tsec_new_rxbuf(bus_dma_tag_t tag, bus_dmamap_t map, struct mbuf **mbufp,
1043 uint32_t *paddr)
1044 {
1045 struct mbuf *new_mbuf;
1046 bus_dma_segment_t seg[1];
1047 int error, nsegs;
1048
1049 KASSERT(mbufp != NULL, ("NULL mbuf pointer!"));
1050
1051 new_mbuf = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MCLBYTES);
1052 if (new_mbuf == NULL)
1053 return (ENOBUFS);
1054 new_mbuf->m_len = new_mbuf->m_pkthdr.len = new_mbuf->m_ext.ext_size;
1055
1056 if (*mbufp) {
1057 bus_dmamap_sync(tag, map, BUS_DMASYNC_POSTREAD);
1058 bus_dmamap_unload(tag, map);
1059 }
1060
1061 error = bus_dmamap_load_mbuf_sg(tag, map, new_mbuf, seg, &nsegs,
1062 BUS_DMA_NOWAIT);
1063 KASSERT(nsegs == 1, ("Too many segments returned!"));
1064 if (nsegs != 1 || error)
1065 panic("tsec_new_rxbuf(): nsegs(%d), error(%d)", nsegs, error);
1066
1067 #if 0
1068 if (error) {
1069 printf("tsec: bus_dmamap_load_mbuf_sg() returned: %d!\n",
1070 error);
1071 m_freem(new_mbuf);
1072 return (ENOBUFS);
1073 }
1074 #endif
1075
1076 #if 0
1077 KASSERT(((seg->ds_addr) & (TSEC_RXBUFFER_ALIGNMENT-1)) == 0,
1078 ("Wrong alignment of RX buffer!"));
1079 #endif
1080 bus_dmamap_sync(tag, map, BUS_DMASYNC_PREREAD);
1081
1082 (*mbufp) = new_mbuf;
1083 (*paddr) = seg->ds_addr;
1084 return (0);
1085 }
1086
1087 static void
tsec_map_dma_addr(void * arg,bus_dma_segment_t * segs,int nseg,int error)1088 tsec_map_dma_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1089 {
1090 u_int32_t *paddr;
1091
1092 KASSERT(nseg == 1, ("wrong number of segments, should be 1"));
1093 paddr = arg;
1094 *paddr = segs->ds_addr;
1095 }
1096
1097 static int
tsec_alloc_dma_desc(device_t dev,bus_dma_tag_t * dtag,bus_dmamap_t * dmap,bus_size_t dsize,void ** vaddr,void * raddr,const char * dname)1098 tsec_alloc_dma_desc(device_t dev, bus_dma_tag_t *dtag, bus_dmamap_t *dmap,
1099 bus_size_t dsize, void **vaddr, void *raddr, const char *dname)
1100 {
1101 int error;
1102
1103 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */
1104 error = bus_dma_tag_create(NULL, /* parent */
1105 PAGE_SIZE, 0, /* alignment, boundary */
1106 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1107 BUS_SPACE_MAXADDR, /* highaddr */
1108 NULL, NULL, /* filtfunc, filtfuncarg */
1109 dsize, 1, /* maxsize, nsegments */
1110 dsize, 0, /* maxsegsz, flags */
1111 NULL, NULL, /* lockfunc, lockfuncarg */
1112 dtag); /* dmat */
1113
1114 if (error) {
1115 device_printf(dev, "failed to allocate busdma %s tag\n",
1116 dname);
1117 (*vaddr) = NULL;
1118 return (ENXIO);
1119 }
1120
1121 error = bus_dmamem_alloc(*dtag, vaddr, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
1122 dmap);
1123 if (error) {
1124 device_printf(dev, "failed to allocate %s DMA safe memory\n",
1125 dname);
1126 bus_dma_tag_destroy(*dtag);
1127 (*vaddr) = NULL;
1128 return (ENXIO);
1129 }
1130
1131 error = bus_dmamap_load(*dtag, *dmap, *vaddr, dsize,
1132 tsec_map_dma_addr, raddr, BUS_DMA_NOWAIT);
1133 if (error) {
1134 device_printf(dev, "cannot get address of the %s "
1135 "descriptors\n", dname);
1136 bus_dmamem_free(*dtag, *vaddr, *dmap);
1137 bus_dma_tag_destroy(*dtag);
1138 (*vaddr) = NULL;
1139 return (ENXIO);
1140 }
1141
1142 return (0);
1143 }
1144
1145 static void
tsec_free_dma_desc(bus_dma_tag_t dtag,bus_dmamap_t dmap,void * vaddr)1146 tsec_free_dma_desc(bus_dma_tag_t dtag, bus_dmamap_t dmap, void *vaddr)
1147 {
1148
1149 if (vaddr == NULL)
1150 return;
1151
1152 /* Unmap descriptors from DMA memory */
1153 bus_dmamap_sync(dtag, dmap, BUS_DMASYNC_POSTREAD |
1154 BUS_DMASYNC_POSTWRITE);
1155 bus_dmamap_unload(dtag, dmap);
1156
1157 /* Free descriptors memory */
1158 bus_dmamem_free(dtag, vaddr, dmap);
1159
1160 /* Destroy descriptors tag */
1161 bus_dma_tag_destroy(dtag);
1162 }
1163
1164 static void
tsec_free_dma(struct tsec_softc * sc)1165 tsec_free_dma(struct tsec_softc *sc)
1166 {
1167 int i;
1168
1169 /* Free TX maps */
1170 for (i = 0; i < TSEC_TX_NUM_DESC; i++)
1171 if (sc->tx_bufmap[i].map_initialized)
1172 bus_dmamap_destroy(sc->tsec_tx_mtag,
1173 sc->tx_bufmap[i].map);
1174 /* Destroy tag for TX mbufs */
1175 bus_dma_tag_destroy(sc->tsec_tx_mtag);
1176
1177 /* Free RX mbufs and maps */
1178 for (i = 0; i < TSEC_RX_NUM_DESC; i++) {
1179 if (sc->rx_data[i].mbuf) {
1180 /* Unload buffer from DMA */
1181 bus_dmamap_sync(sc->tsec_rx_mtag, sc->rx_data[i].map,
1182 BUS_DMASYNC_POSTREAD);
1183 bus_dmamap_unload(sc->tsec_rx_mtag,
1184 sc->rx_data[i].map);
1185
1186 /* Free buffer */
1187 m_freem(sc->rx_data[i].mbuf);
1188 }
1189 /* Destroy map for this buffer */
1190 if (sc->rx_data[i].map != NULL)
1191 bus_dmamap_destroy(sc->tsec_rx_mtag,
1192 sc->rx_data[i].map);
1193 }
1194 /* Destroy tag for RX mbufs */
1195 bus_dma_tag_destroy(sc->tsec_rx_mtag);
1196
1197 /* Unload TX/RX descriptors */
1198 tsec_free_dma_desc(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
1199 sc->tsec_tx_vaddr);
1200 tsec_free_dma_desc(sc->tsec_rx_dtag, sc->tsec_rx_dmap,
1201 sc->tsec_rx_vaddr);
1202 }
1203
1204 static void
tsec_stop(struct tsec_softc * sc)1205 tsec_stop(struct tsec_softc *sc)
1206 {
1207 if_t ifp;
1208 uint32_t tmpval;
1209
1210 TSEC_GLOBAL_LOCK_ASSERT(sc);
1211
1212 ifp = sc->tsec_ifp;
1213
1214 /* Disable interface and watchdog timer */
1215 callout_stop(&sc->tsec_callout);
1216 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE));
1217 sc->tsec_watchdog = 0;
1218
1219 /* Disable all interrupts and stop DMA */
1220 tsec_intrs_ctl(sc, 0);
1221 tsec_dma_ctl(sc, 0);
1222
1223 /* Remove pending data from TX queue */
1224 while (sc->tx_idx_tail != sc->tx_idx_head) {
1225 bus_dmamap_sync(sc->tsec_tx_mtag,
1226 sc->tx_bufmap[sc->tx_idx_tail].map,
1227 BUS_DMASYNC_POSTWRITE);
1228 bus_dmamap_unload(sc->tsec_tx_mtag,
1229 sc->tx_bufmap[sc->tx_idx_tail].map);
1230 m_freem(sc->tx_bufmap[sc->tx_idx_tail].mbuf);
1231 sc->tx_idx_tail = (sc->tx_idx_tail + 1)
1232 & (TSEC_TX_NUM_DESC - 1);
1233 }
1234
1235 /* Disable RX and TX */
1236 tmpval = TSEC_READ(sc, TSEC_REG_MACCFG1);
1237 tmpval &= ~(TSEC_MACCFG1_RX_EN | TSEC_MACCFG1_TX_EN);
1238 TSEC_WRITE(sc, TSEC_REG_MACCFG1, tmpval);
1239 DELAY(10);
1240 }
1241
1242 static void
tsec_tick(void * arg)1243 tsec_tick(void *arg)
1244 {
1245 struct tsec_softc *sc = arg;
1246 if_t ifp;
1247 int link;
1248
1249 TSEC_GLOBAL_LOCK(sc);
1250
1251 tsec_watchdog(sc);
1252
1253 ifp = sc->tsec_ifp;
1254 link = sc->tsec_link;
1255
1256 mii_tick(sc->tsec_mii);
1257
1258 if (link == 0 && sc->tsec_link == 1 &&
1259 (!if_sendq_empty(ifp)))
1260 tsec_start_locked(ifp);
1261
1262 /* Schedule another timeout one second from now. */
1263 callout_reset(&sc->tsec_callout, hz, tsec_tick, sc);
1264
1265 TSEC_GLOBAL_UNLOCK(sc);
1266 }
1267
1268 /*
1269 * This is the core RX routine. It replenishes mbufs in the descriptor and
1270 * sends data which have been dma'ed into host memory to upper layer.
1271 *
1272 * Loops at most count times if count is > 0, or until done if count < 0.
1273 */
1274 static int
tsec_receive_intr_locked(struct tsec_softc * sc,int count)1275 tsec_receive_intr_locked(struct tsec_softc *sc, int count)
1276 {
1277 struct tsec_desc *rx_desc;
1278 if_t ifp;
1279 struct rx_data_type *rx_data;
1280 struct mbuf *m;
1281 uint32_t i;
1282 int c, rx_npkts;
1283 uint16_t flags;
1284
1285 TSEC_RECEIVE_LOCK_ASSERT(sc);
1286
1287 ifp = sc->tsec_ifp;
1288 rx_data = sc->rx_data;
1289 rx_npkts = 0;
1290
1291 bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap,
1292 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1293
1294 for (c = 0; ; c++) {
1295 if (count >= 0 && count-- == 0)
1296 break;
1297
1298 rx_desc = TSEC_GET_CUR_RX_DESC(sc);
1299 flags = rx_desc->flags;
1300
1301 /* Check if there is anything to receive */
1302 if ((flags & TSEC_RXBD_E) || (c >= TSEC_RX_NUM_DESC)) {
1303 /*
1304 * Avoid generating another interrupt
1305 */
1306 if (flags & TSEC_RXBD_E)
1307 TSEC_WRITE(sc, TSEC_REG_IEVENT,
1308 TSEC_IEVENT_RXB | TSEC_IEVENT_RXF);
1309 /*
1310 * We didn't consume current descriptor and have to
1311 * return it to the queue
1312 */
1313 TSEC_BACK_CUR_RX_DESC(sc);
1314 break;
1315 }
1316
1317 if (flags & (TSEC_RXBD_LG | TSEC_RXBD_SH | TSEC_RXBD_NO |
1318 TSEC_RXBD_CR | TSEC_RXBD_OV | TSEC_RXBD_TR)) {
1319 rx_desc->length = 0;
1320 rx_desc->flags = (rx_desc->flags &
1321 ~TSEC_RXBD_ZEROONINIT) | TSEC_RXBD_E | TSEC_RXBD_I;
1322
1323 if (sc->frame != NULL) {
1324 m_free(sc->frame);
1325 sc->frame = NULL;
1326 }
1327
1328 continue;
1329 }
1330
1331 /* Ok... process frame */
1332 i = TSEC_GET_CUR_RX_DESC_CNT(sc);
1333 m = rx_data[i].mbuf;
1334 m->m_len = rx_desc->length;
1335
1336 if (sc->frame != NULL) {
1337 if ((flags & TSEC_RXBD_L) != 0)
1338 m->m_len -= m_length(sc->frame, NULL);
1339
1340 m->m_flags &= ~M_PKTHDR;
1341 m_cat(sc->frame, m);
1342 } else {
1343 sc->frame = m;
1344 }
1345
1346 m = NULL;
1347
1348 if ((flags & TSEC_RXBD_L) != 0) {
1349 m = sc->frame;
1350 sc->frame = NULL;
1351 }
1352
1353 if (tsec_new_rxbuf(sc->tsec_rx_mtag, rx_data[i].map,
1354 &rx_data[i].mbuf, &rx_data[i].paddr)) {
1355 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
1356 /*
1357 * We ran out of mbufs; didn't consume current
1358 * descriptor and have to return it to the queue.
1359 */
1360 TSEC_BACK_CUR_RX_DESC(sc);
1361 break;
1362 }
1363
1364 /* Attach new buffer to descriptor and clear flags */
1365 rx_desc->bufptr = rx_data[i].paddr;
1366 rx_desc->length = 0;
1367 rx_desc->flags = (rx_desc->flags & ~TSEC_RXBD_ZEROONINIT) |
1368 TSEC_RXBD_E | TSEC_RXBD_I;
1369
1370 if (m != NULL) {
1371 m->m_pkthdr.rcvif = ifp;
1372
1373 m_fixhdr(m);
1374 m_adj(m, -ETHER_CRC_LEN);
1375
1376 if (sc->is_etsec)
1377 tsec_offload_process_frame(sc, m);
1378
1379 TSEC_RECEIVE_UNLOCK(sc);
1380 if_input(ifp, m);
1381 TSEC_RECEIVE_LOCK(sc);
1382 rx_npkts++;
1383 }
1384 }
1385
1386 bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap,
1387 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1388
1389 /*
1390 * Make sure TSEC receiver is not halted.
1391 *
1392 * Various conditions can stop the TSEC receiver, but not all are
1393 * signaled and handled by error interrupt, so make sure the receiver
1394 * is running. Writing to TSEC_REG_RSTAT restarts the receiver when
1395 * halted, and is harmless if already running.
1396 */
1397 TSEC_WRITE(sc, TSEC_REG_RSTAT, TSEC_RSTAT_QHLT);
1398 return (rx_npkts);
1399 }
1400
1401 void
tsec_receive_intr(void * arg)1402 tsec_receive_intr(void *arg)
1403 {
1404 struct tsec_softc *sc = arg;
1405
1406 TSEC_RECEIVE_LOCK(sc);
1407
1408 #ifdef DEVICE_POLLING
1409 if (if_getcapenable(sc->tsec_ifp) & IFCAP_POLLING) {
1410 TSEC_RECEIVE_UNLOCK(sc);
1411 return;
1412 }
1413 #endif
1414
1415 /* Confirm the interrupt was received by driver */
1416 TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_RXB | TSEC_IEVENT_RXF);
1417 tsec_receive_intr_locked(sc, -1);
1418
1419 TSEC_RECEIVE_UNLOCK(sc);
1420 }
1421
1422 static void
tsec_transmit_intr_locked(struct tsec_softc * sc)1423 tsec_transmit_intr_locked(struct tsec_softc *sc)
1424 {
1425 if_t ifp;
1426 uint32_t tx_idx;
1427
1428 TSEC_TRANSMIT_LOCK_ASSERT(sc);
1429
1430 ifp = sc->tsec_ifp;
1431
1432 /* Update collision statistics */
1433 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, TSEC_READ(sc, TSEC_REG_MON_TNCL));
1434
1435 /* Reset collision counters in hardware */
1436 TSEC_WRITE(sc, TSEC_REG_MON_TSCL, 0);
1437 TSEC_WRITE(sc, TSEC_REG_MON_TMCL, 0);
1438 TSEC_WRITE(sc, TSEC_REG_MON_TLCL, 0);
1439 TSEC_WRITE(sc, TSEC_REG_MON_TXCL, 0);
1440 TSEC_WRITE(sc, TSEC_REG_MON_TNCL, 0);
1441
1442 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
1443 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1444
1445 tx_idx = sc->tx_idx_tail;
1446 while (tx_idx != sc->tx_idx_head) {
1447 struct tsec_desc *tx_desc;
1448 struct tsec_bufmap *tx_bufmap;
1449
1450 tx_desc = &sc->tsec_tx_vaddr[tx_idx];
1451 if (tx_desc->flags & TSEC_TXBD_R) {
1452 break;
1453 }
1454
1455 tx_bufmap = &sc->tx_bufmap[tx_idx];
1456 tx_idx = (tx_idx + 1) & (TSEC_TX_NUM_DESC - 1);
1457 if (tx_bufmap->mbuf == NULL)
1458 continue;
1459
1460 /*
1461 * This is the last buf in this packet, so unmap and free it.
1462 */
1463 bus_dmamap_sync(sc->tsec_tx_mtag, tx_bufmap->map,
1464 BUS_DMASYNC_POSTWRITE);
1465 bus_dmamap_unload(sc->tsec_tx_mtag, tx_bufmap->map);
1466 m_freem(tx_bufmap->mbuf);
1467 tx_bufmap->mbuf = NULL;
1468
1469 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
1470 }
1471 sc->tx_idx_tail = tx_idx;
1472 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
1473 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1474
1475 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
1476 tsec_start_locked(ifp);
1477
1478 if (sc->tx_idx_tail == sc->tx_idx_head)
1479 sc->tsec_watchdog = 0;
1480 }
1481
1482 void
tsec_transmit_intr(void * arg)1483 tsec_transmit_intr(void *arg)
1484 {
1485 struct tsec_softc *sc = arg;
1486
1487 TSEC_TRANSMIT_LOCK(sc);
1488
1489 #ifdef DEVICE_POLLING
1490 if (if_getcapenable(sc->tsec_ifp) & IFCAP_POLLING) {
1491 TSEC_TRANSMIT_UNLOCK(sc);
1492 return;
1493 }
1494 #endif
1495 /* Confirm the interrupt was received by driver */
1496 TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_TXB | TSEC_IEVENT_TXF);
1497 tsec_transmit_intr_locked(sc);
1498
1499 TSEC_TRANSMIT_UNLOCK(sc);
1500 }
1501
1502 static void
tsec_error_intr_locked(struct tsec_softc * sc,int count)1503 tsec_error_intr_locked(struct tsec_softc *sc, int count)
1504 {
1505 if_t ifp;
1506 uint32_t eflags;
1507
1508 TSEC_GLOBAL_LOCK_ASSERT(sc);
1509
1510 ifp = sc->tsec_ifp;
1511
1512 eflags = TSEC_READ(sc, TSEC_REG_IEVENT);
1513
1514 /* Clear events bits in hardware */
1515 TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_RXC | TSEC_IEVENT_BSY |
1516 TSEC_IEVENT_EBERR | TSEC_IEVENT_MSRO | TSEC_IEVENT_BABT |
1517 TSEC_IEVENT_TXC | TSEC_IEVENT_TXE | TSEC_IEVENT_LC |
1518 TSEC_IEVENT_CRL | TSEC_IEVENT_XFUN);
1519
1520 /* Check transmitter errors */
1521 if (eflags & TSEC_IEVENT_TXE) {
1522 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1523
1524 if (eflags & TSEC_IEVENT_LC)
1525 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
1526
1527 TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT);
1528 }
1529
1530 /* Check for discarded frame due to a lack of buffers */
1531 if (eflags & TSEC_IEVENT_BSY) {
1532 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
1533 }
1534
1535 if (if_getflags(ifp) & IFF_DEBUG)
1536 if_printf(ifp, "tsec_error_intr(): event flags: 0x%x\n",
1537 eflags);
1538
1539 if (eflags & TSEC_IEVENT_EBERR) {
1540 if_printf(ifp, "System bus error occurred during"
1541 "DMA transaction (flags: 0x%x)\n", eflags);
1542 tsec_init_locked(sc);
1543 }
1544
1545 if (eflags & TSEC_IEVENT_BABT)
1546 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1547
1548 if (eflags & TSEC_IEVENT_BABR)
1549 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1550 }
1551
1552 void
tsec_error_intr(void * arg)1553 tsec_error_intr(void *arg)
1554 {
1555 struct tsec_softc *sc = arg;
1556
1557 TSEC_GLOBAL_LOCK(sc);
1558 tsec_error_intr_locked(sc, -1);
1559 TSEC_GLOBAL_UNLOCK(sc);
1560 }
1561
1562 int
tsec_miibus_readreg(device_t dev,int phy,int reg)1563 tsec_miibus_readreg(device_t dev, int phy, int reg)
1564 {
1565 struct tsec_softc *sc;
1566 int timeout;
1567 int rv;
1568
1569 sc = device_get_softc(dev);
1570
1571 TSEC_PHY_LOCK();
1572 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMADD, (phy << 8) | reg);
1573 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCOM, 0);
1574 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCOM, TSEC_MIIMCOM_READCYCLE);
1575
1576 timeout = tsec_mii_wait(sc, TSEC_MIIMIND_NOTVALID | TSEC_MIIMIND_BUSY);
1577 rv = TSEC_PHY_READ(sc, TSEC_REG_MIIMSTAT);
1578 TSEC_PHY_UNLOCK();
1579
1580 if (timeout)
1581 device_printf(dev, "Timeout while reading from PHY!\n");
1582
1583 return (rv);
1584 }
1585
1586 int
tsec_miibus_writereg(device_t dev,int phy,int reg,int value)1587 tsec_miibus_writereg(device_t dev, int phy, int reg, int value)
1588 {
1589 struct tsec_softc *sc;
1590 int timeout;
1591
1592 sc = device_get_softc(dev);
1593
1594 TSEC_PHY_LOCK();
1595 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMADD, (phy << 8) | reg);
1596 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCON, value);
1597 timeout = tsec_mii_wait(sc, TSEC_MIIMIND_BUSY);
1598 TSEC_PHY_UNLOCK();
1599
1600 if (timeout)
1601 device_printf(dev, "Timeout while writing to PHY!\n");
1602
1603 return (0);
1604 }
1605
1606 void
tsec_miibus_statchg(device_t dev)1607 tsec_miibus_statchg(device_t dev)
1608 {
1609 struct tsec_softc *sc;
1610 struct mii_data *mii;
1611 uint32_t ecntrl, id, tmp;
1612 int link;
1613
1614 sc = device_get_softc(dev);
1615 mii = sc->tsec_mii;
1616 link = ((mii->mii_media_status & IFM_ACTIVE) ? 1 : 0);
1617
1618 tmp = TSEC_READ(sc, TSEC_REG_MACCFG2) & ~TSEC_MACCFG2_IF;
1619
1620 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
1621 tmp |= TSEC_MACCFG2_FULLDUPLEX;
1622 else
1623 tmp &= ~TSEC_MACCFG2_FULLDUPLEX;
1624
1625 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1626 case IFM_1000_T:
1627 case IFM_1000_SX:
1628 tmp |= TSEC_MACCFG2_GMII;
1629 sc->tsec_link = link;
1630 break;
1631 case IFM_100_TX:
1632 case IFM_10_T:
1633 tmp |= TSEC_MACCFG2_MII;
1634 sc->tsec_link = link;
1635 break;
1636 case IFM_NONE:
1637 if (link)
1638 device_printf(dev, "No speed selected but link "
1639 "active!\n");
1640 sc->tsec_link = 0;
1641 return;
1642 default:
1643 sc->tsec_link = 0;
1644 device_printf(dev, "Unknown speed (%d), link %s!\n",
1645 IFM_SUBTYPE(mii->mii_media_active),
1646 ((link) ? "up" : "down"));
1647 return;
1648 }
1649 TSEC_WRITE(sc, TSEC_REG_MACCFG2, tmp);
1650
1651 /* XXX kludge - use circumstantial evidence for reduced mode. */
1652 id = TSEC_READ(sc, TSEC_REG_ID2);
1653 if (id & 0xffff) {
1654 ecntrl = TSEC_READ(sc, TSEC_REG_ECNTRL) & ~TSEC_ECNTRL_R100M;
1655 ecntrl |= (tmp & TSEC_MACCFG2_MII) ? TSEC_ECNTRL_R100M : 0;
1656 TSEC_WRITE(sc, TSEC_REG_ECNTRL, ecntrl);
1657 }
1658 }
1659
1660 static void
tsec_add_sysctls(struct tsec_softc * sc)1661 tsec_add_sysctls(struct tsec_softc *sc)
1662 {
1663 struct sysctl_ctx_list *ctx;
1664 struct sysctl_oid_list *children;
1665 struct sysctl_oid *tree;
1666
1667 ctx = device_get_sysctl_ctx(sc->dev);
1668 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev));
1669 tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "int_coal",
1670 CTLFLAG_RD | CTLFLAG_MPSAFE, 0, "TSEC Interrupts coalescing");
1671 children = SYSCTL_CHILDREN(tree);
1672
1673 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_time",
1674 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, TSEC_IC_RX,
1675 tsec_sysctl_ic_time, "I", "IC RX time threshold (0-65535)");
1676 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_count",
1677 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, TSEC_IC_RX,
1678 tsec_sysctl_ic_count, "I", "IC RX frame count threshold (0-255)");
1679
1680 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_time",
1681 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, TSEC_IC_TX,
1682 tsec_sysctl_ic_time, "I", "IC TX time threshold (0-65535)");
1683 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_count",
1684 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, TSEC_IC_TX,
1685 tsec_sysctl_ic_count, "I", "IC TX frame count threshold (0-255)");
1686 }
1687
1688 /*
1689 * With Interrupt Coalescing (IC) active, a transmit/receive frame
1690 * interrupt is raised either upon:
1691 *
1692 * - threshold-defined period of time elapsed, or
1693 * - threshold-defined number of frames is received/transmitted,
1694 * whichever occurs first.
1695 *
1696 * The following sysctls regulate IC behaviour (for TX/RX separately):
1697 *
1698 * dev.tsec.<unit>.int_coal.rx_time
1699 * dev.tsec.<unit>.int_coal.rx_count
1700 * dev.tsec.<unit>.int_coal.tx_time
1701 * dev.tsec.<unit>.int_coal.tx_count
1702 *
1703 * Values:
1704 *
1705 * - 0 for either time or count disables IC on the given TX/RX path
1706 *
1707 * - count: 1-255 (expresses frame count number; note that value of 1 is
1708 * effectively IC off)
1709 *
1710 * - time: 1-65535 (value corresponds to a real time period and is
1711 * expressed in units equivalent to 64 TSEC interface clocks, i.e. one timer
1712 * threshold unit is 26.5 us, 2.56 us, or 512 ns, corresponding to 10 Mbps,
1713 * 100 Mbps, or 1Gbps, respectively. For detailed discussion consult the
1714 * TSEC reference manual.
1715 */
1716 static int
tsec_sysctl_ic_time(SYSCTL_HANDLER_ARGS)1717 tsec_sysctl_ic_time(SYSCTL_HANDLER_ARGS)
1718 {
1719 int error;
1720 uint32_t time;
1721 struct tsec_softc *sc = (struct tsec_softc *)arg1;
1722
1723 time = (arg2 == TSEC_IC_RX) ? sc->rx_ic_time : sc->tx_ic_time;
1724
1725 error = sysctl_handle_int(oidp, &time, 0, req);
1726 if (error != 0)
1727 return (error);
1728
1729 if (time > 65535)
1730 return (EINVAL);
1731
1732 TSEC_IC_LOCK(sc);
1733 if (arg2 == TSEC_IC_RX) {
1734 sc->rx_ic_time = time;
1735 tsec_set_rxic(sc);
1736 } else {
1737 sc->tx_ic_time = time;
1738 tsec_set_txic(sc);
1739 }
1740 TSEC_IC_UNLOCK(sc);
1741
1742 return (0);
1743 }
1744
1745 static int
tsec_sysctl_ic_count(SYSCTL_HANDLER_ARGS)1746 tsec_sysctl_ic_count(SYSCTL_HANDLER_ARGS)
1747 {
1748 int error;
1749 uint32_t count;
1750 struct tsec_softc *sc = (struct tsec_softc *)arg1;
1751
1752 count = (arg2 == TSEC_IC_RX) ? sc->rx_ic_count : sc->tx_ic_count;
1753
1754 error = sysctl_handle_int(oidp, &count, 0, req);
1755 if (error != 0)
1756 return (error);
1757
1758 if (count > 255)
1759 return (EINVAL);
1760
1761 TSEC_IC_LOCK(sc);
1762 if (arg2 == TSEC_IC_RX) {
1763 sc->rx_ic_count = count;
1764 tsec_set_rxic(sc);
1765 } else {
1766 sc->tx_ic_count = count;
1767 tsec_set_txic(sc);
1768 }
1769 TSEC_IC_UNLOCK(sc);
1770
1771 return (0);
1772 }
1773
1774 static void
tsec_set_rxic(struct tsec_softc * sc)1775 tsec_set_rxic(struct tsec_softc *sc)
1776 {
1777 uint32_t rxic_val;
1778
1779 if (sc->rx_ic_count == 0 || sc->rx_ic_time == 0)
1780 /* Disable RX IC */
1781 rxic_val = 0;
1782 else {
1783 rxic_val = 0x80000000;
1784 rxic_val |= (sc->rx_ic_count << 21);
1785 rxic_val |= sc->rx_ic_time;
1786 }
1787
1788 TSEC_WRITE(sc, TSEC_REG_RXIC, rxic_val);
1789 }
1790
1791 static void
tsec_set_txic(struct tsec_softc * sc)1792 tsec_set_txic(struct tsec_softc *sc)
1793 {
1794 uint32_t txic_val;
1795
1796 if (sc->tx_ic_count == 0 || sc->tx_ic_time == 0)
1797 /* Disable TX IC */
1798 txic_val = 0;
1799 else {
1800 txic_val = 0x80000000;
1801 txic_val |= (sc->tx_ic_count << 21);
1802 txic_val |= sc->tx_ic_time;
1803 }
1804
1805 TSEC_WRITE(sc, TSEC_REG_TXIC, txic_val);
1806 }
1807
1808 static void
tsec_offload_setup(struct tsec_softc * sc)1809 tsec_offload_setup(struct tsec_softc *sc)
1810 {
1811 if_t ifp = sc->tsec_ifp;
1812 uint32_t reg;
1813
1814 TSEC_GLOBAL_LOCK_ASSERT(sc);
1815
1816 reg = TSEC_READ(sc, TSEC_REG_TCTRL);
1817 reg |= TSEC_TCTRL_IPCSEN | TSEC_TCTRL_TUCSEN;
1818
1819 if (if_getcapenable(ifp) & IFCAP_TXCSUM)
1820 if_sethwassist(ifp, TSEC_CHECKSUM_FEATURES);
1821 else
1822 if_sethwassist(ifp, 0);
1823
1824 TSEC_WRITE(sc, TSEC_REG_TCTRL, reg);
1825
1826 reg = TSEC_READ(sc, TSEC_REG_RCTRL);
1827 reg &= ~(TSEC_RCTRL_IPCSEN | TSEC_RCTRL_TUCSEN | TSEC_RCTRL_PRSDEP);
1828 reg |= TSEC_RCTRL_PRSDEP_PARSE_L2 | TSEC_RCTRL_VLEX;
1829
1830 if (if_getcapenable(ifp) & IFCAP_RXCSUM)
1831 reg |= TSEC_RCTRL_IPCSEN | TSEC_RCTRL_TUCSEN |
1832 TSEC_RCTRL_PRSDEP_PARSE_L234;
1833
1834 TSEC_WRITE(sc, TSEC_REG_RCTRL, reg);
1835 }
1836
1837 static void
tsec_offload_process_frame(struct tsec_softc * sc,struct mbuf * m)1838 tsec_offload_process_frame(struct tsec_softc *sc, struct mbuf *m)
1839 {
1840 struct tsec_rx_fcb rx_fcb;
1841 int csum_flags = 0;
1842 int protocol, flags;
1843
1844 TSEC_RECEIVE_LOCK_ASSERT(sc);
1845
1846 m_copydata(m, 0, sizeof(struct tsec_rx_fcb), (caddr_t)(&rx_fcb));
1847 flags = rx_fcb.flags;
1848 protocol = rx_fcb.protocol;
1849
1850 if (TSEC_RX_FCB_IP_CSUM_CHECKED(flags)) {
1851 csum_flags |= CSUM_IP_CHECKED;
1852
1853 if ((flags & TSEC_RX_FCB_IP_CSUM_ERROR) == 0)
1854 csum_flags |= CSUM_IP_VALID;
1855 }
1856
1857 if ((protocol == IPPROTO_TCP || protocol == IPPROTO_UDP) &&
1858 TSEC_RX_FCB_TCP_UDP_CSUM_CHECKED(flags) &&
1859 (flags & TSEC_RX_FCB_TCP_UDP_CSUM_ERROR) == 0) {
1860 csum_flags |= CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
1861 m->m_pkthdr.csum_data = 0xFFFF;
1862 }
1863
1864 m->m_pkthdr.csum_flags = csum_flags;
1865
1866 if (flags & TSEC_RX_FCB_VLAN) {
1867 m->m_pkthdr.ether_vtag = rx_fcb.vlan;
1868 m->m_flags |= M_VLANTAG;
1869 }
1870
1871 m_adj(m, sizeof(struct tsec_rx_fcb));
1872 }
1873
1874 static u_int
tsec_hash_maddr(void * arg,struct sockaddr_dl * sdl,u_int cnt)1875 tsec_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
1876 {
1877 uint32_t h, *hashtable = arg;
1878
1879 h = (ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) >> 24) & 0xFF;
1880 hashtable[(h >> 5)] |= 1 << (0x1F - (h & 0x1F));
1881
1882 return (1);
1883 }
1884
1885 static void
tsec_setup_multicast(struct tsec_softc * sc)1886 tsec_setup_multicast(struct tsec_softc *sc)
1887 {
1888 uint32_t hashtable[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
1889 if_t ifp = sc->tsec_ifp;
1890 int i;
1891
1892 TSEC_GLOBAL_LOCK_ASSERT(sc);
1893
1894 if (if_getflags(ifp) & IFF_ALLMULTI) {
1895 for (i = 0; i < 8; i++)
1896 TSEC_WRITE(sc, TSEC_REG_GADDR(i), 0xFFFFFFFF);
1897
1898 return;
1899 }
1900
1901 if_foreach_llmaddr(ifp, tsec_hash_maddr, &hashtable);
1902
1903 for (i = 0; i < 8; i++)
1904 TSEC_WRITE(sc, TSEC_REG_GADDR(i), hashtable[i]);
1905 }
1906
1907 static int
tsec_set_mtu(struct tsec_softc * sc,unsigned int mtu)1908 tsec_set_mtu(struct tsec_softc *sc, unsigned int mtu)
1909 {
1910
1911 mtu += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN;
1912
1913 TSEC_GLOBAL_LOCK_ASSERT(sc);
1914
1915 if (mtu >= TSEC_MIN_FRAME_SIZE && mtu <= TSEC_MAX_FRAME_SIZE) {
1916 TSEC_WRITE(sc, TSEC_REG_MAXFRM, mtu);
1917 return (mtu);
1918 }
1919
1920 return (0);
1921 }
1922