1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "../dmub_srv.h"
27 #include "dmub_dcn20.h"
28 #include "dmub_dcn21.h"
29 #include "dmub_cmd.h"
30 #include "dmub_dcn30.h"
31 #include "dmub_dcn301.h"
32 #include "dmub_dcn302.h"
33 #include "dmub_dcn303.h"
34 #include "dmub_dcn31.h"
35 #include "dmub_dcn314.h"
36 #include "dmub_dcn315.h"
37 #include "dmub_dcn316.h"
38 #include "dmub_dcn32.h"
39 #include "os_types.h"
40 /*
41 * Note: the DMUB service is standalone. No additional headers should be
42 * added below or above this line unless they reside within the DMUB
43 * folder.
44 */
45
46 /* Alignment for framebuffer memory. */
47 #define DMUB_FB_ALIGNMENT (1024 * 1024)
48
49 /* Stack size. */
50 #define DMUB_STACK_SIZE (128 * 1024)
51
52 /* Context size. */
53 #define DMUB_CONTEXT_SIZE (512 * 1024)
54
55 /* Mailbox size : Ring buffers are required for both inbox and outbox */
56 #define DMUB_MAILBOX_SIZE ((2 * DMUB_RB_SIZE))
57
58 /* Default state size if meta is absent. */
59 #define DMUB_FW_STATE_SIZE (64 * 1024)
60
61 /* Default tracebuffer size if meta is absent. */
62 #define DMUB_TRACE_BUFFER_SIZE (64 * 1024)
63
64
65 /* Default scratch mem size. */
66 #define DMUB_SCRATCH_MEM_SIZE (256)
67
68 /* Number of windows in use. */
69 #define DMUB_NUM_WINDOWS (DMUB_WINDOW_TOTAL)
70 /* Base addresses. */
71
72 #define DMUB_CW0_BASE (0x60000000)
73 #define DMUB_CW1_BASE (0x61000000)
74 #define DMUB_CW3_BASE (0x63000000)
75 #define DMUB_CW4_BASE (0x64000000)
76 #define DMUB_CW5_BASE (0x65000000)
77 #define DMUB_CW6_BASE (0x66000000)
78
79 #define DMUB_REGION5_BASE (0xA0000000)
80
dmub_align(uint32_t val,uint32_t factor)81 static inline uint32_t dmub_align(uint32_t val, uint32_t factor)
82 {
83 return (val + factor - 1) / factor * factor;
84 }
85
dmub_flush_buffer_mem(const struct dmub_fb * fb)86 void dmub_flush_buffer_mem(const struct dmub_fb *fb)
87 {
88 const uint8_t *base = (const uint8_t *)fb->cpu_addr;
89 uint8_t buf[64];
90 uint32_t pos, end;
91
92 /**
93 * Read 64-byte chunks since we don't want to store a
94 * large temporary buffer for this purpose.
95 */
96 end = fb->size / sizeof(buf) * sizeof(buf);
97
98 for (pos = 0; pos < end; pos += sizeof(buf))
99 dmub_memcpy(buf, base + pos, sizeof(buf));
100
101 /* Read anything leftover into the buffer. */
102 if (end < fb->size)
103 dmub_memcpy(buf, base + pos, fb->size - end);
104 }
105
106 static const struct dmub_fw_meta_info *
dmub_get_fw_meta_info_from_blob(const uint8_t * blob,uint32_t blob_size,uint32_t meta_offset)107 dmub_get_fw_meta_info_from_blob(const uint8_t *blob, uint32_t blob_size, uint32_t meta_offset)
108 {
109 const union dmub_fw_meta *meta;
110
111 if (!blob || !blob_size)
112 return NULL;
113
114 if (blob_size < sizeof(union dmub_fw_meta) + meta_offset)
115 return NULL;
116
117 meta = (const union dmub_fw_meta *)(blob + blob_size - meta_offset -
118 sizeof(union dmub_fw_meta));
119
120 if (meta->info.magic_value != DMUB_FW_META_MAGIC)
121 return NULL;
122
123 return &meta->info;
124 }
125
126 static const struct dmub_fw_meta_info *
dmub_get_fw_meta_info(const struct dmub_srv_region_params * params)127 dmub_get_fw_meta_info(const struct dmub_srv_region_params *params)
128 {
129 const struct dmub_fw_meta_info *info = NULL;
130
131 if (params->fw_bss_data && params->bss_data_size) {
132 /* Legacy metadata region. */
133 info = dmub_get_fw_meta_info_from_blob(params->fw_bss_data,
134 params->bss_data_size,
135 DMUB_FW_META_OFFSET);
136 } else if (params->fw_inst_const && params->inst_const_size) {
137 /* Combined metadata region - can be aligned to 16-bytes. */
138 uint32_t i;
139
140 for (i = 0; i < 16; ++i) {
141 info = dmub_get_fw_meta_info_from_blob(
142 params->fw_inst_const, params->inst_const_size, i);
143
144 if (info)
145 break;
146 }
147 }
148
149 return info;
150 }
151
dmub_srv_hw_setup(struct dmub_srv * dmub,enum dmub_asic asic)152 static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic)
153 {
154 struct dmub_srv_hw_funcs *funcs = &dmub->hw_funcs;
155
156 switch (asic) {
157 case DMUB_ASIC_DCN20:
158 case DMUB_ASIC_DCN21:
159 case DMUB_ASIC_DCN30:
160 case DMUB_ASIC_DCN301:
161 case DMUB_ASIC_DCN302:
162 case DMUB_ASIC_DCN303:
163 dmub->regs = &dmub_srv_dcn20_regs;
164
165 funcs->reset = dmub_dcn20_reset;
166 funcs->reset_release = dmub_dcn20_reset_release;
167 funcs->backdoor_load = dmub_dcn20_backdoor_load;
168 funcs->setup_windows = dmub_dcn20_setup_windows;
169 funcs->setup_mailbox = dmub_dcn20_setup_mailbox;
170 funcs->get_inbox1_wptr = dmub_dcn20_get_inbox1_wptr;
171 funcs->get_inbox1_rptr = dmub_dcn20_get_inbox1_rptr;
172 funcs->set_inbox1_wptr = dmub_dcn20_set_inbox1_wptr;
173 funcs->is_supported = dmub_dcn20_is_supported;
174 funcs->is_hw_init = dmub_dcn20_is_hw_init;
175 funcs->set_gpint = dmub_dcn20_set_gpint;
176 funcs->is_gpint_acked = dmub_dcn20_is_gpint_acked;
177 funcs->get_gpint_response = dmub_dcn20_get_gpint_response;
178 funcs->get_fw_status = dmub_dcn20_get_fw_boot_status;
179 funcs->enable_dmub_boot_options = dmub_dcn20_enable_dmub_boot_options;
180 funcs->skip_dmub_panel_power_sequence = dmub_dcn20_skip_dmub_panel_power_sequence;
181 funcs->get_current_time = dmub_dcn20_get_current_time;
182
183 // Out mailbox register access functions for RN and above
184 funcs->setup_out_mailbox = dmub_dcn20_setup_out_mailbox;
185 funcs->get_outbox1_wptr = dmub_dcn20_get_outbox1_wptr;
186 funcs->set_outbox1_rptr = dmub_dcn20_set_outbox1_rptr;
187
188 //outbox0 call stacks
189 funcs->setup_outbox0 = dmub_dcn20_setup_outbox0;
190 funcs->get_outbox0_wptr = dmub_dcn20_get_outbox0_wptr;
191 funcs->set_outbox0_rptr = dmub_dcn20_set_outbox0_rptr;
192
193 funcs->get_diagnostic_data = dmub_dcn20_get_diagnostic_data;
194
195 if (asic == DMUB_ASIC_DCN21)
196 dmub->regs = &dmub_srv_dcn21_regs;
197
198 if (asic == DMUB_ASIC_DCN30) {
199 dmub->regs = &dmub_srv_dcn30_regs;
200
201 funcs->backdoor_load = dmub_dcn30_backdoor_load;
202 funcs->setup_windows = dmub_dcn30_setup_windows;
203 }
204 if (asic == DMUB_ASIC_DCN301) {
205 dmub->regs = &dmub_srv_dcn301_regs;
206
207 funcs->backdoor_load = dmub_dcn30_backdoor_load;
208 funcs->setup_windows = dmub_dcn30_setup_windows;
209 }
210 if (asic == DMUB_ASIC_DCN302) {
211 dmub->regs = &dmub_srv_dcn302_regs;
212
213 funcs->backdoor_load = dmub_dcn30_backdoor_load;
214 funcs->setup_windows = dmub_dcn30_setup_windows;
215 }
216 if (asic == DMUB_ASIC_DCN303) {
217 dmub->regs = &dmub_srv_dcn303_regs;
218
219 funcs->backdoor_load = dmub_dcn30_backdoor_load;
220 funcs->setup_windows = dmub_dcn30_setup_windows;
221 }
222 break;
223
224 case DMUB_ASIC_DCN31:
225 case DMUB_ASIC_DCN31B:
226 case DMUB_ASIC_DCN314:
227 case DMUB_ASIC_DCN315:
228 case DMUB_ASIC_DCN316:
229 if (asic == DMUB_ASIC_DCN314) {
230 dmub->regs_dcn31 = &dmub_srv_dcn314_regs;
231 funcs->is_psrsu_supported = dmub_dcn314_is_psrsu_supported;
232 } else if (asic == DMUB_ASIC_DCN315) {
233 dmub->regs_dcn31 = &dmub_srv_dcn315_regs;
234 } else if (asic == DMUB_ASIC_DCN316) {
235 dmub->regs_dcn31 = &dmub_srv_dcn316_regs;
236 } else {
237 dmub->regs_dcn31 = &dmub_srv_dcn31_regs;
238 funcs->is_psrsu_supported = dmub_dcn31_is_psrsu_supported;
239 }
240 funcs->reset = dmub_dcn31_reset;
241 funcs->reset_release = dmub_dcn31_reset_release;
242 funcs->backdoor_load = dmub_dcn31_backdoor_load;
243 funcs->setup_windows = dmub_dcn31_setup_windows;
244 funcs->setup_mailbox = dmub_dcn31_setup_mailbox;
245 funcs->get_inbox1_wptr = dmub_dcn31_get_inbox1_wptr;
246 funcs->get_inbox1_rptr = dmub_dcn31_get_inbox1_rptr;
247 funcs->set_inbox1_wptr = dmub_dcn31_set_inbox1_wptr;
248 funcs->setup_out_mailbox = dmub_dcn31_setup_out_mailbox;
249 funcs->get_outbox1_wptr = dmub_dcn31_get_outbox1_wptr;
250 funcs->set_outbox1_rptr = dmub_dcn31_set_outbox1_rptr;
251 funcs->is_supported = dmub_dcn31_is_supported;
252 funcs->is_hw_init = dmub_dcn31_is_hw_init;
253 funcs->set_gpint = dmub_dcn31_set_gpint;
254 funcs->is_gpint_acked = dmub_dcn31_is_gpint_acked;
255 funcs->get_gpint_response = dmub_dcn31_get_gpint_response;
256 funcs->get_gpint_dataout = dmub_dcn31_get_gpint_dataout;
257 funcs->get_fw_status = dmub_dcn31_get_fw_boot_status;
258 funcs->get_fw_boot_option = dmub_dcn31_get_fw_boot_option;
259 funcs->enable_dmub_boot_options = dmub_dcn31_enable_dmub_boot_options;
260 funcs->skip_dmub_panel_power_sequence = dmub_dcn31_skip_dmub_panel_power_sequence;
261 //outbox0 call stacks
262 funcs->setup_outbox0 = dmub_dcn31_setup_outbox0;
263 funcs->get_outbox0_wptr = dmub_dcn31_get_outbox0_wptr;
264 funcs->set_outbox0_rptr = dmub_dcn31_set_outbox0_rptr;
265
266 funcs->get_diagnostic_data = dmub_dcn31_get_diagnostic_data;
267 funcs->should_detect = dmub_dcn31_should_detect;
268 funcs->get_current_time = dmub_dcn31_get_current_time;
269
270 break;
271
272 case DMUB_ASIC_DCN32:
273 case DMUB_ASIC_DCN321:
274 dmub->regs_dcn32 = &dmub_srv_dcn32_regs;
275 funcs->configure_dmub_in_system_memory = dmub_dcn32_configure_dmub_in_system_memory;
276 funcs->send_inbox0_cmd = dmub_dcn32_send_inbox0_cmd;
277 funcs->clear_inbox0_ack_register = dmub_dcn32_clear_inbox0_ack_register;
278 funcs->read_inbox0_ack_register = dmub_dcn32_read_inbox0_ack_register;
279 funcs->reset = dmub_dcn32_reset;
280 funcs->reset_release = dmub_dcn32_reset_release;
281 funcs->backdoor_load = dmub_dcn32_backdoor_load;
282 funcs->backdoor_load_zfb_mode = dmub_dcn32_backdoor_load_zfb_mode;
283 funcs->setup_windows = dmub_dcn32_setup_windows;
284 funcs->setup_mailbox = dmub_dcn32_setup_mailbox;
285 funcs->get_inbox1_wptr = dmub_dcn32_get_inbox1_wptr;
286 funcs->get_inbox1_rptr = dmub_dcn32_get_inbox1_rptr;
287 funcs->set_inbox1_wptr = dmub_dcn32_set_inbox1_wptr;
288 funcs->setup_out_mailbox = dmub_dcn32_setup_out_mailbox;
289 funcs->get_outbox1_wptr = dmub_dcn32_get_outbox1_wptr;
290 funcs->set_outbox1_rptr = dmub_dcn32_set_outbox1_rptr;
291 funcs->is_supported = dmub_dcn32_is_supported;
292 funcs->is_hw_init = dmub_dcn32_is_hw_init;
293 funcs->set_gpint = dmub_dcn32_set_gpint;
294 funcs->is_gpint_acked = dmub_dcn32_is_gpint_acked;
295 funcs->get_gpint_response = dmub_dcn32_get_gpint_response;
296 funcs->get_gpint_dataout = dmub_dcn32_get_gpint_dataout;
297 funcs->get_fw_status = dmub_dcn32_get_fw_boot_status;
298 funcs->enable_dmub_boot_options = dmub_dcn32_enable_dmub_boot_options;
299 funcs->skip_dmub_panel_power_sequence = dmub_dcn32_skip_dmub_panel_power_sequence;
300
301 /* outbox0 call stacks */
302 funcs->setup_outbox0 = dmub_dcn32_setup_outbox0;
303 funcs->get_outbox0_wptr = dmub_dcn32_get_outbox0_wptr;
304 funcs->set_outbox0_rptr = dmub_dcn32_set_outbox0_rptr;
305 funcs->get_current_time = dmub_dcn32_get_current_time;
306 funcs->get_diagnostic_data = dmub_dcn32_get_diagnostic_data;
307
308 break;
309
310 default:
311 return false;
312 }
313
314 return true;
315 }
316
dmub_srv_create(struct dmub_srv * dmub,const struct dmub_srv_create_params * params)317 enum dmub_status dmub_srv_create(struct dmub_srv *dmub,
318 const struct dmub_srv_create_params *params)
319 {
320 enum dmub_status status = DMUB_STATUS_OK;
321
322 dmub_memset(dmub, 0, sizeof(*dmub));
323
324 dmub->funcs = params->funcs;
325 dmub->user_ctx = params->user_ctx;
326 dmub->asic = params->asic;
327 dmub->fw_version = params->fw_version;
328 dmub->is_virtual = params->is_virtual;
329
330 /* Setup asic dependent hardware funcs. */
331 if (!dmub_srv_hw_setup(dmub, params->asic)) {
332 status = DMUB_STATUS_INVALID;
333 goto cleanup;
334 }
335
336 /* Override (some) hardware funcs based on user params. */
337 if (params->hw_funcs) {
338 if (params->hw_funcs->emul_get_inbox1_rptr)
339 dmub->hw_funcs.emul_get_inbox1_rptr =
340 params->hw_funcs->emul_get_inbox1_rptr;
341
342 if (params->hw_funcs->emul_set_inbox1_wptr)
343 dmub->hw_funcs.emul_set_inbox1_wptr =
344 params->hw_funcs->emul_set_inbox1_wptr;
345
346 if (params->hw_funcs->is_supported)
347 dmub->hw_funcs.is_supported =
348 params->hw_funcs->is_supported;
349 }
350
351 /* Sanity checks for required hw func pointers. */
352 if (!dmub->hw_funcs.get_inbox1_rptr ||
353 !dmub->hw_funcs.set_inbox1_wptr) {
354 status = DMUB_STATUS_INVALID;
355 goto cleanup;
356 }
357
358 cleanup:
359 if (status == DMUB_STATUS_OK)
360 dmub->sw_init = true;
361 else
362 dmub_srv_destroy(dmub);
363
364 return status;
365 }
366
dmub_srv_destroy(struct dmub_srv * dmub)367 void dmub_srv_destroy(struct dmub_srv *dmub)
368 {
369 dmub_memset(dmub, 0, sizeof(*dmub));
370 }
371
372 enum dmub_status
dmub_srv_calc_region_info(struct dmub_srv * dmub,const struct dmub_srv_region_params * params,struct dmub_srv_region_info * out)373 dmub_srv_calc_region_info(struct dmub_srv *dmub,
374 const struct dmub_srv_region_params *params,
375 struct dmub_srv_region_info *out)
376 {
377 struct dmub_region *inst = &out->regions[DMUB_WINDOW_0_INST_CONST];
378 struct dmub_region *stack = &out->regions[DMUB_WINDOW_1_STACK];
379 struct dmub_region *data = &out->regions[DMUB_WINDOW_2_BSS_DATA];
380 struct dmub_region *bios = &out->regions[DMUB_WINDOW_3_VBIOS];
381 struct dmub_region *mail = &out->regions[DMUB_WINDOW_4_MAILBOX];
382 struct dmub_region *trace_buff = &out->regions[DMUB_WINDOW_5_TRACEBUFF];
383 struct dmub_region *fw_state = &out->regions[DMUB_WINDOW_6_FW_STATE];
384 struct dmub_region *scratch_mem = &out->regions[DMUB_WINDOW_7_SCRATCH_MEM];
385 const struct dmub_fw_meta_info *fw_info;
386 uint32_t fw_state_size = DMUB_FW_STATE_SIZE;
387 uint32_t trace_buffer_size = DMUB_TRACE_BUFFER_SIZE;
388 uint32_t scratch_mem_size = DMUB_SCRATCH_MEM_SIZE;
389 uint32_t previous_top = 0;
390 if (!dmub->sw_init)
391 return DMUB_STATUS_INVALID;
392
393 memset(out, 0, sizeof(*out));
394
395 out->num_regions = DMUB_NUM_WINDOWS;
396
397 inst->base = 0x0;
398 inst->top = inst->base + params->inst_const_size;
399
400 data->base = dmub_align(inst->top, 256);
401 data->top = data->base + params->bss_data_size;
402
403 /*
404 * All cache windows below should be aligned to the size
405 * of the DMCUB cache line, 64 bytes.
406 */
407
408 stack->base = dmub_align(data->top, 256);
409 stack->top = stack->base + DMUB_STACK_SIZE + DMUB_CONTEXT_SIZE;
410
411 bios->base = dmub_align(stack->top, 256);
412 bios->top = bios->base + params->vbios_size;
413
414 if (params->is_mailbox_in_inbox) {
415 mail->base = 0;
416 mail->top = mail->base + DMUB_MAILBOX_SIZE;
417 previous_top = bios->top;
418 } else {
419 mail->base = dmub_align(bios->top, 256);
420 mail->top = mail->base + DMUB_MAILBOX_SIZE;
421 previous_top = mail->top;
422 }
423
424 fw_info = dmub_get_fw_meta_info(params);
425
426 if (fw_info) {
427 fw_state_size = fw_info->fw_region_size;
428 trace_buffer_size = fw_info->trace_buffer_size;
429
430 /**
431 * If DM didn't fill in a version, then fill it in based on
432 * the firmware meta now that we have it.
433 *
434 * TODO: Make it easier for driver to extract this out to
435 * pass during creation.
436 */
437 if (dmub->fw_version == 0)
438 dmub->fw_version = fw_info->fw_version;
439 }
440
441 trace_buff->base = dmub_align(previous_top, 256);
442 trace_buff->top = trace_buff->base + dmub_align(trace_buffer_size, 64);
443
444 fw_state->base = dmub_align(trace_buff->top, 256);
445 fw_state->top = fw_state->base + dmub_align(fw_state_size, 64);
446
447 scratch_mem->base = dmub_align(fw_state->top, 256);
448 scratch_mem->top = scratch_mem->base + dmub_align(scratch_mem_size, 64);
449
450 out->fb_size = dmub_align(scratch_mem->top, 4096);
451
452 if (params->is_mailbox_in_inbox)
453 out->inbox_size = dmub_align(mail->top, 4096);
454
455 return DMUB_STATUS_OK;
456 }
457
dmub_srv_calc_mem_info(struct dmub_srv * dmub,const struct dmub_srv_memory_params * params,struct dmub_srv_fb_info * out)458 enum dmub_status dmub_srv_calc_mem_info(struct dmub_srv *dmub,
459 const struct dmub_srv_memory_params *params,
460 struct dmub_srv_fb_info *out)
461 {
462 uint8_t *cpu_base;
463 uint64_t gpu_base;
464 uint32_t i;
465
466 if (!dmub->sw_init)
467 return DMUB_STATUS_INVALID;
468
469 memset(out, 0, sizeof(*out));
470
471 if (params->region_info->num_regions != DMUB_NUM_WINDOWS)
472 return DMUB_STATUS_INVALID;
473
474 cpu_base = (uint8_t *)params->cpu_fb_addr;
475 gpu_base = params->gpu_fb_addr;
476
477 for (i = 0; i < DMUB_NUM_WINDOWS; ++i) {
478 const struct dmub_region *reg =
479 ¶ms->region_info->regions[i];
480
481 out->fb[i].cpu_addr = cpu_base + reg->base;
482 out->fb[i].gpu_addr = gpu_base + reg->base;
483
484 if (i == DMUB_WINDOW_4_MAILBOX && params->cpu_inbox_addr != 0) {
485 out->fb[i].cpu_addr = (uint8_t *)params->cpu_inbox_addr + reg->base;
486 out->fb[i].gpu_addr = params->gpu_inbox_addr + reg->base;
487 }
488
489 out->fb[i].size = reg->top - reg->base;
490 }
491
492 out->num_fb = DMUB_NUM_WINDOWS;
493
494 return DMUB_STATUS_OK;
495 }
496
dmub_srv_has_hw_support(struct dmub_srv * dmub,bool * is_supported)497 enum dmub_status dmub_srv_has_hw_support(struct dmub_srv *dmub,
498 bool *is_supported)
499 {
500 *is_supported = false;
501
502 if (!dmub->sw_init)
503 return DMUB_STATUS_INVALID;
504
505 if (dmub->hw_funcs.is_supported)
506 *is_supported = dmub->hw_funcs.is_supported(dmub);
507
508 return DMUB_STATUS_OK;
509 }
510
dmub_srv_is_hw_init(struct dmub_srv * dmub,bool * is_hw_init)511 enum dmub_status dmub_srv_is_hw_init(struct dmub_srv *dmub, bool *is_hw_init)
512 {
513 *is_hw_init = false;
514
515 if (!dmub->sw_init)
516 return DMUB_STATUS_INVALID;
517
518 if (!dmub->hw_init)
519 return DMUB_STATUS_OK;
520
521 if (dmub->hw_funcs.is_hw_init)
522 *is_hw_init = dmub->hw_funcs.is_hw_init(dmub);
523
524 return DMUB_STATUS_OK;
525 }
526
dmub_srv_hw_init(struct dmub_srv * dmub,const struct dmub_srv_hw_params * params)527 enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,
528 const struct dmub_srv_hw_params *params)
529 {
530 struct dmub_fb *inst_fb = params->fb[DMUB_WINDOW_0_INST_CONST];
531 struct dmub_fb *stack_fb = params->fb[DMUB_WINDOW_1_STACK];
532 struct dmub_fb *data_fb = params->fb[DMUB_WINDOW_2_BSS_DATA];
533 struct dmub_fb *bios_fb = params->fb[DMUB_WINDOW_3_VBIOS];
534 struct dmub_fb *mail_fb = params->fb[DMUB_WINDOW_4_MAILBOX];
535 struct dmub_fb *tracebuff_fb = params->fb[DMUB_WINDOW_5_TRACEBUFF];
536 struct dmub_fb *fw_state_fb = params->fb[DMUB_WINDOW_6_FW_STATE];
537 struct dmub_fb *scratch_mem_fb = params->fb[DMUB_WINDOW_7_SCRATCH_MEM];
538
539 struct dmub_rb_init_params rb_params, outbox0_rb_params;
540 struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6;
541 struct dmub_region inbox1, outbox1, outbox0;
542
543 if (!dmub->sw_init)
544 return DMUB_STATUS_INVALID;
545
546 if (!inst_fb || !stack_fb || !data_fb || !bios_fb || !mail_fb ||
547 !tracebuff_fb || !fw_state_fb || !scratch_mem_fb) {
548 ASSERT(0);
549 return DMUB_STATUS_INVALID;
550 }
551
552 dmub->fb_base = params->fb_base;
553 dmub->fb_offset = params->fb_offset;
554 dmub->psp_version = params->psp_version;
555
556 if (dmub->hw_funcs.reset)
557 dmub->hw_funcs.reset(dmub);
558
559 /* reset the cache of the last wptr as well now that hw is reset */
560 dmub->inbox1_last_wptr = 0;
561
562 cw0.offset.quad_part = inst_fb->gpu_addr;
563 cw0.region.base = DMUB_CW0_BASE;
564 cw0.region.top = cw0.region.base + inst_fb->size - 1;
565
566 cw1.offset.quad_part = stack_fb->gpu_addr;
567 cw1.region.base = DMUB_CW1_BASE;
568 cw1.region.top = cw1.region.base + stack_fb->size - 1;
569
570 if (params->fw_in_system_memory && dmub->hw_funcs.configure_dmub_in_system_memory)
571 dmub->hw_funcs.configure_dmub_in_system_memory(dmub);
572
573 if (params->load_inst_const && dmub->hw_funcs.backdoor_load) {
574 /**
575 * Read back all the instruction memory so we don't hang the
576 * DMCUB when backdoor loading if the write from x86 hasn't been
577 * flushed yet. This only occurs in backdoor loading.
578 */
579 dmub_flush_buffer_mem(inst_fb);
580
581 if (params->fw_in_system_memory && dmub->hw_funcs.backdoor_load_zfb_mode)
582 dmub->hw_funcs.backdoor_load_zfb_mode(dmub, &cw0, &cw1);
583 else
584 dmub->hw_funcs.backdoor_load(dmub, &cw0, &cw1);
585 }
586
587 cw2.offset.quad_part = data_fb->gpu_addr;
588 cw2.region.base = DMUB_CW0_BASE + inst_fb->size;
589 cw2.region.top = cw2.region.base + data_fb->size;
590
591 cw3.offset.quad_part = bios_fb->gpu_addr;
592 cw3.region.base = DMUB_CW3_BASE;
593 cw3.region.top = cw3.region.base + bios_fb->size;
594
595 cw4.offset.quad_part = mail_fb->gpu_addr;
596 cw4.region.base = DMUB_CW4_BASE;
597 cw4.region.top = cw4.region.base + mail_fb->size;
598
599 /**
600 * Doubled the mailbox region to accomodate inbox and outbox.
601 * Note: Currently, currently total mailbox size is 16KB. It is split
602 * equally into 8KB between inbox and outbox. If this config is
603 * changed, then uncached base address configuration of outbox1
604 * has to be updated in funcs->setup_out_mailbox.
605 */
606 inbox1.base = cw4.region.base;
607 inbox1.top = cw4.region.base + DMUB_RB_SIZE;
608 outbox1.base = inbox1.top;
609 outbox1.top = cw4.region.top;
610
611 cw5.offset.quad_part = tracebuff_fb->gpu_addr;
612 cw5.region.base = DMUB_CW5_BASE;
613 cw5.region.top = cw5.region.base + tracebuff_fb->size;
614
615 outbox0.base = DMUB_REGION5_BASE + TRACE_BUFFER_ENTRY_OFFSET;
616 outbox0.top = outbox0.base + tracebuff_fb->size - TRACE_BUFFER_ENTRY_OFFSET;
617
618 cw6.offset.quad_part = fw_state_fb->gpu_addr;
619 cw6.region.base = DMUB_CW6_BASE;
620 cw6.region.top = cw6.region.base + fw_state_fb->size;
621
622 dmub->fw_state = fw_state_fb->cpu_addr;
623
624 dmub->scratch_mem_fb = *scratch_mem_fb;
625
626 if (dmub->hw_funcs.setup_windows)
627 dmub->hw_funcs.setup_windows(dmub, &cw2, &cw3, &cw4, &cw5, &cw6);
628
629 if (dmub->hw_funcs.setup_outbox0)
630 dmub->hw_funcs.setup_outbox0(dmub, &outbox0);
631
632 if (dmub->hw_funcs.setup_mailbox)
633 dmub->hw_funcs.setup_mailbox(dmub, &inbox1);
634 if (dmub->hw_funcs.setup_out_mailbox)
635 dmub->hw_funcs.setup_out_mailbox(dmub, &outbox1);
636
637 dmub_memset(&rb_params, 0, sizeof(rb_params));
638 rb_params.ctx = dmub;
639 rb_params.base_address = mail_fb->cpu_addr;
640 rb_params.capacity = DMUB_RB_SIZE;
641 dmub_rb_init(&dmub->inbox1_rb, &rb_params);
642
643 // Initialize outbox1 ring buffer
644 rb_params.ctx = dmub;
645 rb_params.base_address = (void *) ((uint8_t *) (mail_fb->cpu_addr) + DMUB_RB_SIZE);
646 rb_params.capacity = DMUB_RB_SIZE;
647 dmub_rb_init(&dmub->outbox1_rb, &rb_params);
648
649 dmub_memset(&outbox0_rb_params, 0, sizeof(outbox0_rb_params));
650 outbox0_rb_params.ctx = dmub;
651 outbox0_rb_params.base_address = (void *)((uintptr_t)(tracebuff_fb->cpu_addr) + TRACE_BUFFER_ENTRY_OFFSET);
652 outbox0_rb_params.capacity = tracebuff_fb->size - dmub_align(TRACE_BUFFER_ENTRY_OFFSET, 64);
653 dmub_rb_init(&dmub->outbox0_rb, &outbox0_rb_params);
654
655 /* Report to DMUB what features are supported by current driver */
656 if (dmub->hw_funcs.enable_dmub_boot_options)
657 dmub->hw_funcs.enable_dmub_boot_options(dmub, params);
658
659 if (dmub->hw_funcs.skip_dmub_panel_power_sequence && !dmub->is_virtual)
660 dmub->hw_funcs.skip_dmub_panel_power_sequence(dmub,
661 params->skip_panel_power_sequence);
662
663 if (dmub->hw_funcs.reset_release && !dmub->is_virtual)
664 dmub->hw_funcs.reset_release(dmub);
665
666 dmub->hw_init = true;
667
668 return DMUB_STATUS_OK;
669 }
670
dmub_srv_sync_inbox1(struct dmub_srv * dmub)671 enum dmub_status dmub_srv_sync_inbox1(struct dmub_srv *dmub)
672 {
673 if (!dmub->sw_init)
674 return DMUB_STATUS_INVALID;
675
676 if (dmub->hw_funcs.get_inbox1_rptr && dmub->hw_funcs.get_inbox1_wptr) {
677 uint32_t rptr = dmub->hw_funcs.get_inbox1_rptr(dmub);
678 uint32_t wptr = dmub->hw_funcs.get_inbox1_wptr(dmub);
679
680 if (rptr > dmub->inbox1_rb.capacity || wptr > dmub->inbox1_rb.capacity) {
681 return DMUB_STATUS_HW_FAILURE;
682 } else {
683 dmub->inbox1_rb.rptr = rptr;
684 dmub->inbox1_rb.wrpt = wptr;
685 dmub->inbox1_last_wptr = dmub->inbox1_rb.wrpt;
686 }
687 }
688
689 return DMUB_STATUS_OK;
690 }
691
dmub_srv_hw_reset(struct dmub_srv * dmub)692 enum dmub_status dmub_srv_hw_reset(struct dmub_srv *dmub)
693 {
694 if (!dmub->sw_init)
695 return DMUB_STATUS_INVALID;
696
697 if (dmub->hw_funcs.reset)
698 dmub->hw_funcs.reset(dmub);
699
700 /* mailboxes have been reset in hw, so reset the sw state as well */
701 dmub->inbox1_last_wptr = 0;
702 dmub->inbox1_rb.wrpt = 0;
703 dmub->inbox1_rb.rptr = 0;
704 dmub->outbox0_rb.wrpt = 0;
705 dmub->outbox0_rb.rptr = 0;
706 dmub->outbox1_rb.wrpt = 0;
707 dmub->outbox1_rb.rptr = 0;
708
709 dmub->hw_init = false;
710
711 return DMUB_STATUS_OK;
712 }
713
dmub_srv_cmd_queue(struct dmub_srv * dmub,const union dmub_rb_cmd * cmd)714 enum dmub_status dmub_srv_cmd_queue(struct dmub_srv *dmub,
715 const union dmub_rb_cmd *cmd)
716 {
717 if (!dmub->hw_init)
718 return DMUB_STATUS_INVALID;
719
720 if (dmub->inbox1_rb.rptr > dmub->inbox1_rb.capacity ||
721 dmub->inbox1_rb.wrpt > dmub->inbox1_rb.capacity) {
722 return DMUB_STATUS_HW_FAILURE;
723 }
724
725 if (dmub_rb_push_front(&dmub->inbox1_rb, cmd))
726 return DMUB_STATUS_OK;
727
728 return DMUB_STATUS_QUEUE_FULL;
729 }
730
dmub_srv_cmd_execute(struct dmub_srv * dmub)731 enum dmub_status dmub_srv_cmd_execute(struct dmub_srv *dmub)
732 {
733 struct dmub_rb flush_rb;
734
735 if (!dmub->hw_init)
736 return DMUB_STATUS_INVALID;
737
738 /**
739 * Read back all the queued commands to ensure that they've
740 * been flushed to framebuffer memory. Otherwise DMCUB might
741 * read back stale, fully invalid or partially invalid data.
742 */
743 flush_rb = dmub->inbox1_rb;
744 flush_rb.rptr = dmub->inbox1_last_wptr;
745 dmub_rb_flush_pending(&flush_rb);
746
747 dmub->hw_funcs.set_inbox1_wptr(dmub, dmub->inbox1_rb.wrpt);
748
749 dmub->inbox1_last_wptr = dmub->inbox1_rb.wrpt;
750
751 return DMUB_STATUS_OK;
752 }
753
dmub_srv_wait_for_auto_load(struct dmub_srv * dmub,uint32_t timeout_us)754 enum dmub_status dmub_srv_wait_for_auto_load(struct dmub_srv *dmub,
755 uint32_t timeout_us)
756 {
757 uint32_t i;
758
759 if (!dmub->hw_init)
760 return DMUB_STATUS_INVALID;
761
762 for (i = 0; i <= timeout_us; i += 100) {
763 union dmub_fw_boot_status status = dmub->hw_funcs.get_fw_status(dmub);
764
765 if (status.bits.dal_fw && status.bits.mailbox_rdy)
766 return DMUB_STATUS_OK;
767
768 udelay(100);
769 }
770
771 return DMUB_STATUS_TIMEOUT;
772 }
773
dmub_srv_wait_for_idle(struct dmub_srv * dmub,uint32_t timeout_us)774 enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv *dmub,
775 uint32_t timeout_us)
776 {
777 uint32_t i, rptr;
778
779 if (!dmub->hw_init)
780 return DMUB_STATUS_INVALID;
781
782 for (i = 0; i <= timeout_us; ++i) {
783 rptr = dmub->hw_funcs.get_inbox1_rptr(dmub);
784
785 if (rptr > dmub->inbox1_rb.capacity)
786 return DMUB_STATUS_HW_FAILURE;
787
788 dmub->inbox1_rb.rptr = rptr;
789
790 if (dmub_rb_empty(&dmub->inbox1_rb))
791 return DMUB_STATUS_OK;
792
793 udelay(1);
794 }
795
796 return DMUB_STATUS_TIMEOUT;
797 }
798
799 enum dmub_status
dmub_srv_send_gpint_command(struct dmub_srv * dmub,enum dmub_gpint_command command_code,uint16_t param,uint32_t timeout_us)800 dmub_srv_send_gpint_command(struct dmub_srv *dmub,
801 enum dmub_gpint_command command_code,
802 uint16_t param, uint32_t timeout_us)
803 {
804 union dmub_gpint_data_register reg;
805 uint32_t i;
806
807 if (!dmub->sw_init)
808 return DMUB_STATUS_INVALID;
809
810 if (!dmub->hw_funcs.set_gpint)
811 return DMUB_STATUS_INVALID;
812
813 if (!dmub->hw_funcs.is_gpint_acked)
814 return DMUB_STATUS_INVALID;
815
816 reg.bits.status = 1;
817 reg.bits.command_code = command_code;
818 reg.bits.param = param;
819
820 dmub->hw_funcs.set_gpint(dmub, reg);
821
822 for (i = 0; i < timeout_us; ++i) {
823 udelay(1);
824
825 if (dmub->hw_funcs.is_gpint_acked(dmub, reg))
826 return DMUB_STATUS_OK;
827 }
828
829 return DMUB_STATUS_TIMEOUT;
830 }
831
dmub_srv_get_gpint_response(struct dmub_srv * dmub,uint32_t * response)832 enum dmub_status dmub_srv_get_gpint_response(struct dmub_srv *dmub,
833 uint32_t *response)
834 {
835 *response = 0;
836
837 if (!dmub->sw_init)
838 return DMUB_STATUS_INVALID;
839
840 if (!dmub->hw_funcs.get_gpint_response)
841 return DMUB_STATUS_INVALID;
842
843 *response = dmub->hw_funcs.get_gpint_response(dmub);
844
845 return DMUB_STATUS_OK;
846 }
847
dmub_srv_get_gpint_dataout(struct dmub_srv * dmub,uint32_t * dataout)848 enum dmub_status dmub_srv_get_gpint_dataout(struct dmub_srv *dmub,
849 uint32_t *dataout)
850 {
851 *dataout = 0;
852
853 if (!dmub->sw_init)
854 return DMUB_STATUS_INVALID;
855
856 if (!dmub->hw_funcs.get_gpint_dataout)
857 return DMUB_STATUS_INVALID;
858
859 *dataout = dmub->hw_funcs.get_gpint_dataout(dmub);
860
861 return DMUB_STATUS_OK;
862 }
863
dmub_srv_get_fw_boot_status(struct dmub_srv * dmub,union dmub_fw_boot_status * status)864 enum dmub_status dmub_srv_get_fw_boot_status(struct dmub_srv *dmub,
865 union dmub_fw_boot_status *status)
866 {
867 status->all = 0;
868
869 if (!dmub->sw_init)
870 return DMUB_STATUS_INVALID;
871
872 if (dmub->hw_funcs.get_fw_status)
873 *status = dmub->hw_funcs.get_fw_status(dmub);
874
875 return DMUB_STATUS_OK;
876 }
877
dmub_srv_get_fw_boot_option(struct dmub_srv * dmub,union dmub_fw_boot_options * option)878 enum dmub_status dmub_srv_get_fw_boot_option(struct dmub_srv *dmub,
879 union dmub_fw_boot_options *option)
880 {
881 option->all = 0;
882
883 if (!dmub->sw_init)
884 return DMUB_STATUS_INVALID;
885
886 if (dmub->hw_funcs.get_fw_boot_option)
887 *option = dmub->hw_funcs.get_fw_boot_option(dmub);
888
889 return DMUB_STATUS_OK;
890 }
891
dmub_srv_set_skip_panel_power_sequence(struct dmub_srv * dmub,bool skip)892 enum dmub_status dmub_srv_set_skip_panel_power_sequence(struct dmub_srv *dmub,
893 bool skip)
894 {
895 if (!dmub->sw_init)
896 return DMUB_STATUS_INVALID;
897
898 if (dmub->hw_funcs.skip_dmub_panel_power_sequence && !dmub->is_virtual)
899 dmub->hw_funcs.skip_dmub_panel_power_sequence(dmub, skip);
900
901 return DMUB_STATUS_OK;
902 }
903
dmub_srv_cmd_with_reply_data(struct dmub_srv * dmub,union dmub_rb_cmd * cmd)904 enum dmub_status dmub_srv_cmd_with_reply_data(struct dmub_srv *dmub,
905 union dmub_rb_cmd *cmd)
906 {
907 enum dmub_status status = DMUB_STATUS_OK;
908
909 // Queue command
910 status = dmub_srv_cmd_queue(dmub, cmd);
911
912 if (status != DMUB_STATUS_OK)
913 return status;
914
915 // Execute command
916 status = dmub_srv_cmd_execute(dmub);
917
918 if (status != DMUB_STATUS_OK)
919 return status;
920
921 // Wait for DMUB to process command
922 status = dmub_srv_wait_for_idle(dmub, 100000);
923
924 if (status != DMUB_STATUS_OK)
925 return status;
926
927 // Copy data back from ring buffer into command
928 dmub_rb_get_return_data(&dmub->inbox1_rb, cmd);
929
930 return status;
931 }
932
dmub_rb_out_trace_buffer_front(struct dmub_rb * rb,void * entry)933 static inline bool dmub_rb_out_trace_buffer_front(struct dmub_rb *rb,
934 void *entry)
935 {
936 const uint64_t *src = (const uint64_t *)(rb->base_address) + rb->rptr / sizeof(uint64_t);
937 uint64_t *dst = (uint64_t *)entry;
938 uint8_t i;
939 uint8_t loop_count;
940
941 if (rb->rptr == rb->wrpt)
942 return false;
943
944 loop_count = sizeof(struct dmcub_trace_buf_entry) / sizeof(uint64_t);
945 // copying data
946 for (i = 0; i < loop_count; i++)
947 *dst++ = *src++;
948
949 rb->rptr += sizeof(struct dmcub_trace_buf_entry);
950
951 rb->rptr %= rb->capacity;
952
953 return true;
954 }
955
dmub_srv_get_outbox0_msg(struct dmub_srv * dmub,struct dmcub_trace_buf_entry * entry)956 bool dmub_srv_get_outbox0_msg(struct dmub_srv *dmub, struct dmcub_trace_buf_entry *entry)
957 {
958 dmub->outbox0_rb.wrpt = dmub->hw_funcs.get_outbox0_wptr(dmub);
959
960 return dmub_rb_out_trace_buffer_front(&dmub->outbox0_rb, (void *)entry);
961 }
962
dmub_srv_get_diagnostic_data(struct dmub_srv * dmub,struct dmub_diagnostic_data * diag_data)963 bool dmub_srv_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data)
964 {
965 if (!dmub || !dmub->hw_funcs.get_diagnostic_data || !diag_data)
966 return false;
967 dmub->hw_funcs.get_diagnostic_data(dmub, diag_data);
968 return true;
969 }
970
dmub_srv_should_detect(struct dmub_srv * dmub)971 bool dmub_srv_should_detect(struct dmub_srv *dmub)
972 {
973 if (!dmub->hw_init || !dmub->hw_funcs.should_detect)
974 return false;
975
976 return dmub->hw_funcs.should_detect(dmub);
977 }
978
dmub_srv_clear_inbox0_ack(struct dmub_srv * dmub)979 enum dmub_status dmub_srv_clear_inbox0_ack(struct dmub_srv *dmub)
980 {
981 if (!dmub->hw_init || !dmub->hw_funcs.clear_inbox0_ack_register)
982 return DMUB_STATUS_INVALID;
983
984 dmub->hw_funcs.clear_inbox0_ack_register(dmub);
985 return DMUB_STATUS_OK;
986 }
987
dmub_srv_wait_for_inbox0_ack(struct dmub_srv * dmub,uint32_t timeout_us)988 enum dmub_status dmub_srv_wait_for_inbox0_ack(struct dmub_srv *dmub, uint32_t timeout_us)
989 {
990 uint32_t i = 0;
991 uint32_t ack = 0;
992
993 if (!dmub->hw_init || !dmub->hw_funcs.read_inbox0_ack_register)
994 return DMUB_STATUS_INVALID;
995
996 for (i = 0; i <= timeout_us; i++) {
997 ack = dmub->hw_funcs.read_inbox0_ack_register(dmub);
998 if (ack)
999 return DMUB_STATUS_OK;
1000 udelay(1);
1001 }
1002 return DMUB_STATUS_TIMEOUT;
1003 }
1004
dmub_srv_send_inbox0_cmd(struct dmub_srv * dmub,union dmub_inbox0_data_register data)1005 enum dmub_status dmub_srv_send_inbox0_cmd(struct dmub_srv *dmub,
1006 union dmub_inbox0_data_register data)
1007 {
1008 if (!dmub->hw_init || !dmub->hw_funcs.send_inbox0_cmd)
1009 return DMUB_STATUS_INVALID;
1010
1011 dmub->hw_funcs.send_inbox0_cmd(dmub, data);
1012 return DMUB_STATUS_OK;
1013 }
1014