1// Intel megafunction declarations, to avoid Yosys complaining. 2`default_nettype none 3 4(* blackbox *) 5module altera_pll 6#( 7 parameter reference_clock_frequency = "0 ps", 8 parameter fractional_vco_multiplier = "false", 9 parameter pll_type = "General", 10 parameter pll_subtype = "General", 11 parameter number_of_clocks = 1, 12 parameter operation_mode = "internal feedback", 13 parameter deserialization_factor = 4, 14 parameter data_rate = 0, 15 16 parameter sim_additional_refclk_cycles_to_lock = 0, 17 parameter output_clock_frequency0 = "0 ps", 18 parameter phase_shift0 = "0 ps", 19 parameter duty_cycle0 = 50, 20 21 parameter output_clock_frequency1 = "0 ps", 22 parameter phase_shift1 = "0 ps", 23 parameter duty_cycle1 = 50, 24 25 parameter output_clock_frequency2 = "0 ps", 26 parameter phase_shift2 = "0 ps", 27 parameter duty_cycle2 = 50, 28 29 parameter output_clock_frequency3 = "0 ps", 30 parameter phase_shift3 = "0 ps", 31 parameter duty_cycle3 = 50, 32 33 parameter output_clock_frequency4 = "0 ps", 34 parameter phase_shift4 = "0 ps", 35 parameter duty_cycle4 = 50, 36 37 parameter output_clock_frequency5 = "0 ps", 38 parameter phase_shift5 = "0 ps", 39 parameter duty_cycle5 = 50, 40 41 parameter output_clock_frequency6 = "0 ps", 42 parameter phase_shift6 = "0 ps", 43 parameter duty_cycle6 = 50, 44 45 parameter output_clock_frequency7 = "0 ps", 46 parameter phase_shift7 = "0 ps", 47 parameter duty_cycle7 = 50, 48 49 parameter output_clock_frequency8 = "0 ps", 50 parameter phase_shift8 = "0 ps", 51 parameter duty_cycle8 = 50, 52 53 parameter output_clock_frequency9 = "0 ps", 54 parameter phase_shift9 = "0 ps", 55 parameter duty_cycle9 = 50, 56 57 58 parameter output_clock_frequency10 = "0 ps", 59 parameter phase_shift10 = "0 ps", 60 parameter duty_cycle10 = 50, 61 62 parameter output_clock_frequency11 = "0 ps", 63 parameter phase_shift11 = "0 ps", 64 parameter duty_cycle11 = 50, 65 66 parameter output_clock_frequency12 = "0 ps", 67 parameter phase_shift12 = "0 ps", 68 parameter duty_cycle12 = 50, 69 70 parameter output_clock_frequency13 = "0 ps", 71 parameter phase_shift13 = "0 ps", 72 parameter duty_cycle13 = 50, 73 74 parameter output_clock_frequency14 = "0 ps", 75 parameter phase_shift14 = "0 ps", 76 parameter duty_cycle14 = 50, 77 78 parameter output_clock_frequency15 = "0 ps", 79 parameter phase_shift15 = "0 ps", 80 parameter duty_cycle15 = 50, 81 82 parameter output_clock_frequency16 = "0 ps", 83 parameter phase_shift16 = "0 ps", 84 parameter duty_cycle16 = 50, 85 86 parameter output_clock_frequency17 = "0 ps", 87 parameter phase_shift17 = "0 ps", 88 parameter duty_cycle17 = 50, 89 90 parameter clock_name_0 = "", 91 parameter clock_name_1 = "", 92 parameter clock_name_2 = "", 93 parameter clock_name_3 = "", 94 parameter clock_name_4 = "", 95 parameter clock_name_5 = "", 96 parameter clock_name_6 = "", 97 parameter clock_name_7 = "", 98 parameter clock_name_8 = "", 99 100 parameter clock_name_global_0 = "false", 101 parameter clock_name_global_1 = "false", 102 parameter clock_name_global_2 = "false", 103 parameter clock_name_global_3 = "false", 104 parameter clock_name_global_4 = "false", 105 parameter clock_name_global_5 = "false", 106 parameter clock_name_global_6 = "false", 107 parameter clock_name_global_7 = "false", 108 parameter clock_name_global_8 = "false", 109 110 parameter m_cnt_hi_div = 1, 111 parameter m_cnt_lo_div = 1, 112 parameter m_cnt_bypass_en = "false", 113 parameter m_cnt_odd_div_duty_en = "false", 114 parameter n_cnt_hi_div = 1, 115 parameter n_cnt_lo_div = 1, 116 parameter n_cnt_bypass_en = "false", 117 parameter n_cnt_odd_div_duty_en = "false", 118 parameter c_cnt_hi_div0 = 1, 119 parameter c_cnt_lo_div0 = 1, 120 parameter c_cnt_bypass_en0 = "false", 121 parameter c_cnt_in_src0 = "ph_mux_clk", 122 parameter c_cnt_odd_div_duty_en0 = "false", 123 parameter c_cnt_prst0 = 1, 124 parameter c_cnt_ph_mux_prst0 = 0, 125 parameter c_cnt_hi_div1 = 1, 126 parameter c_cnt_lo_div1 = 1, 127 parameter c_cnt_bypass_en1 = "false", 128 parameter c_cnt_in_src1 = "ph_mux_clk", 129 parameter c_cnt_odd_div_duty_en1 = "false", 130 parameter c_cnt_prst1 = 1, 131 parameter c_cnt_ph_mux_prst1 = 0, 132 parameter c_cnt_hi_div2 = 1, 133 parameter c_cnt_lo_div2 = 1, 134 parameter c_cnt_bypass_en2 = "false", 135 parameter c_cnt_in_src2 = "ph_mux_clk", 136 parameter c_cnt_odd_div_duty_en2 = "false", 137 parameter c_cnt_prst2 = 1, 138 parameter c_cnt_ph_mux_prst2 = 0, 139 parameter c_cnt_hi_div3 = 1, 140 parameter c_cnt_lo_div3 = 1, 141 parameter c_cnt_bypass_en3 = "false", 142 parameter c_cnt_in_src3 = "ph_mux_clk", 143 parameter c_cnt_odd_div_duty_en3 = "false", 144 parameter c_cnt_prst3 = 1, 145 parameter c_cnt_ph_mux_prst3 = 0, 146 parameter c_cnt_hi_div4 = 1, 147 parameter c_cnt_lo_div4 = 1, 148 parameter c_cnt_bypass_en4 = "false", 149 parameter c_cnt_in_src4 = "ph_mux_clk", 150 parameter c_cnt_odd_div_duty_en4 = "false", 151 parameter c_cnt_prst4 = 1, 152 parameter c_cnt_ph_mux_prst4 = 0, 153 parameter c_cnt_hi_div5 = 1, 154 parameter c_cnt_lo_div5 = 1, 155 parameter c_cnt_bypass_en5 = "false", 156 parameter c_cnt_in_src5 = "ph_mux_clk", 157 parameter c_cnt_odd_div_duty_en5 = "false", 158 parameter c_cnt_prst5 = 1, 159 parameter c_cnt_ph_mux_prst5 = 0, 160 parameter c_cnt_hi_div6 = 1, 161 parameter c_cnt_lo_div6 = 1, 162 parameter c_cnt_bypass_en6 = "false", 163 parameter c_cnt_in_src6 = "ph_mux_clk", 164 parameter c_cnt_odd_div_duty_en6 = "false", 165 parameter c_cnt_prst6 = 1, 166 parameter c_cnt_ph_mux_prst6 = 0, 167 parameter c_cnt_hi_div7 = 1, 168 parameter c_cnt_lo_div7 = 1, 169 parameter c_cnt_bypass_en7 = "false", 170 parameter c_cnt_in_src7 = "ph_mux_clk", 171 parameter c_cnt_odd_div_duty_en7 = "false", 172 parameter c_cnt_prst7 = 1, 173 parameter c_cnt_ph_mux_prst7 = 0, 174 parameter c_cnt_hi_div8 = 1, 175 parameter c_cnt_lo_div8 = 1, 176 parameter c_cnt_bypass_en8 = "false", 177 parameter c_cnt_in_src8 = "ph_mux_clk", 178 parameter c_cnt_odd_div_duty_en8 = "false", 179 parameter c_cnt_prst8 = 1, 180 parameter c_cnt_ph_mux_prst8 = 0, 181 parameter c_cnt_hi_div9 = 1, 182 parameter c_cnt_lo_div9 = 1, 183 parameter c_cnt_bypass_en9 = "false", 184 parameter c_cnt_in_src9 = "ph_mux_clk", 185 parameter c_cnt_odd_div_duty_en9 = "false", 186 parameter c_cnt_prst9 = 1, 187 parameter c_cnt_ph_mux_prst9 = 0, 188 parameter c_cnt_hi_div10 = 1, 189 parameter c_cnt_lo_div10 = 1, 190 parameter c_cnt_bypass_en10 = "false", 191 parameter c_cnt_in_src10 = "ph_mux_clk", 192 parameter c_cnt_odd_div_duty_en10 = "false", 193 parameter c_cnt_prst10 = 1, 194 parameter c_cnt_ph_mux_prst10 = 0, 195 parameter c_cnt_hi_div11 = 1, 196 parameter c_cnt_lo_div11 = 1, 197 parameter c_cnt_bypass_en11 = "false", 198 parameter c_cnt_in_src11 = "ph_mux_clk", 199 parameter c_cnt_odd_div_duty_en11 = "false", 200 parameter c_cnt_prst11 = 1, 201 parameter c_cnt_ph_mux_prst11 = 0, 202 parameter c_cnt_hi_div12 = 1, 203 parameter c_cnt_lo_div12 = 1, 204 parameter c_cnt_bypass_en12 = "false", 205 parameter c_cnt_in_src12 = "ph_mux_clk", 206 parameter c_cnt_odd_div_duty_en12 = "false", 207 parameter c_cnt_prst12 = 1, 208 parameter c_cnt_ph_mux_prst12 = 0, 209 parameter c_cnt_hi_div13 = 1, 210 parameter c_cnt_lo_div13 = 1, 211 parameter c_cnt_bypass_en13 = "false", 212 parameter c_cnt_in_src13 = "ph_mux_clk", 213 parameter c_cnt_odd_div_duty_en13 = "false", 214 parameter c_cnt_prst13 = 1, 215 parameter c_cnt_ph_mux_prst13 = 0, 216 parameter c_cnt_hi_div14 = 1, 217 parameter c_cnt_lo_div14 = 1, 218 parameter c_cnt_bypass_en14 = "false", 219 parameter c_cnt_in_src14 = "ph_mux_clk", 220 parameter c_cnt_odd_div_duty_en14 = "false", 221 parameter c_cnt_prst14 = 1, 222 parameter c_cnt_ph_mux_prst14 = 0, 223 parameter c_cnt_hi_div15 = 1, 224 parameter c_cnt_lo_div15 = 1, 225 parameter c_cnt_bypass_en15 = "false", 226 parameter c_cnt_in_src15 = "ph_mux_clk", 227 parameter c_cnt_odd_div_duty_en15 = "false", 228 parameter c_cnt_prst15 = 1, 229 parameter c_cnt_ph_mux_prst15 = 0, 230 parameter c_cnt_hi_div16 = 1, 231 parameter c_cnt_lo_div16 = 1, 232 parameter c_cnt_bypass_en16 = "false", 233 parameter c_cnt_in_src16 = "ph_mux_clk", 234 parameter c_cnt_odd_div_duty_en16 = "false", 235 parameter c_cnt_prst16 = 1, 236 parameter c_cnt_ph_mux_prst16 = 0, 237 parameter c_cnt_hi_div17 = 1, 238 parameter c_cnt_lo_div17 = 1, 239 parameter c_cnt_bypass_en17 = "false", 240 parameter c_cnt_in_src17 = "ph_mux_clk", 241 parameter c_cnt_odd_div_duty_en17 = "false", 242 parameter c_cnt_prst17 = 1, 243 parameter c_cnt_ph_mux_prst17 = 0, 244 parameter pll_vco_div = 1, 245 parameter pll_slf_rst = "false", 246 parameter pll_bw_sel = "low", 247 parameter pll_output_clk_frequency = "0 MHz", 248 parameter pll_cp_current = 0, 249 parameter pll_bwctrl = 0, 250 parameter pll_fractional_division = 1, 251 parameter pll_fractional_cout = 24, 252 parameter pll_dsm_out_sel = "1st_order", 253 parameter mimic_fbclk_type = "gclk", 254 parameter pll_fbclk_mux_1 = "glb", 255 parameter pll_fbclk_mux_2 = "fb_1", 256 parameter pll_m_cnt_in_src = "ph_mux_clk", 257 parameter pll_vcoph_div = 1, 258 parameter refclk1_frequency = "0 MHz", 259 parameter pll_clkin_0_src = "clk_0", 260 parameter pll_clkin_1_src = "clk_0", 261 parameter pll_clk_loss_sw_en = "false", 262 parameter pll_auto_clk_sw_en = "false", 263 parameter pll_manu_clk_sw_en = "false", 264 parameter pll_clk_sw_dly = 0, 265 parameter pll_extclk_0_cnt_src = "pll_extclk_cnt_src_vss", 266 parameter pll_extclk_1_cnt_src = "pll_extclk_cnt_src_vss" 267) ( 268 //input 269 input refclk, 270 input refclk1, 271 input fbclk, 272 input rst, 273 input phase_en, 274 input updn, 275 input [2:0] num_phase_shifts, 276 input scanclk, 277 input [4:0] cntsel, 278 input [63:0] reconfig_to_pll, 279 input extswitch, 280 input adjpllin, 281 input cclk, 282 283 //output 284 output [ number_of_clocks -1 : 0] outclk, 285 output fboutclk, 286 output locked, 287 output phase_done, 288 output [63:0] reconfig_from_pll, 289 output activeclk, 290 output [1:0] clkbad, 291 output [7:0] phout, 292 output [1:0] lvds_clk, 293 output [1:0] loaden, 294 output [1:0] extclk_out, 295 output [ number_of_clocks -1 : 0] cascade_out, 296 297 //inout 298 inout zdbfbclk 299); 300 301endmodule 302 303 304(* blackbox *) 305module altera_std_synchronizer(clk, din, dout, reset_n); 306 307parameter depth = 2; 308 309input clk; 310input reset_n; 311input din; 312output dout; 313 314endmodule 315 316(* blackbox *) 317module altddio_in ( 318 datain, // required port, DDR input data 319 inclock, // required port, input reference clock to sample data by 320 inclocken, // enable data clock 321 aset, // asynchronous set 322 aclr, // asynchronous clear 323 sset, // synchronous set 324 sclr, // synchronous clear 325 dataout_h, // data sampled at the rising edge of inclock 326 dataout_l // data sampled at the falling edge of inclock 327); 328 329parameter width = 1; 330parameter power_up_high = "OFF"; 331parameter invert_input_clocks = "OFF"; 332parameter intended_device_family = "Stratix"; 333parameter lpm_type = "altddio_in"; 334parameter lpm_hint = "UNUSED"; 335 336input [width-1:0] datain; 337input inclock; 338input inclocken; 339input aset; 340input aclr; 341input sset; 342input sclr; 343 344output [width-1:0] dataout_h; 345output [width-1:0] dataout_l; 346 347endmodule 348 349 350(* blackbox *) 351module altddio_out ( 352 datain_h, 353 datain_l, 354 outclock, 355 outclocken, 356 aset, 357 aclr, 358 sset, 359 sclr, 360 oe, 361 dataout, 362 oe_out 363); 364 365parameter width = 1; 366parameter power_up_high = "OFF"; 367parameter oe_reg = "UNUSED"; 368parameter extend_oe_disable = "UNUSED"; 369parameter intended_device_family = "Stratix"; 370parameter invert_output = "OFF"; 371parameter lpm_type = "altddio_out"; 372parameter lpm_hint = "UNUSED"; 373 374input [width-1:0] datain_h; 375input [width-1:0] datain_l; 376input outclock; 377input outclocken; 378input aset; 379input aclr; 380input sset; 381input sclr; 382input oe; 383 384output [width-1:0] dataout; 385output [width-1:0] oe_out; 386 387endmodule 388 389 390(* blackbox *) 391module altddio_bidir ( 392 datain_h, 393 datain_l, 394 inclock, 395 inclocken, 396 outclock, 397 outclocken, 398 aset, 399 aclr, 400 sset, 401 sclr, 402 oe, 403 dataout_h, 404 dataout_l, 405 combout, 406 oe_out, 407 dqsundelayedout, 408 padio 409); 410 411// GLOBAL PARAMETER DECLARATION 412parameter width = 1; // required parameter 413parameter power_up_high = "OFF"; 414parameter oe_reg = "UNUSED"; 415parameter extend_oe_disable = "UNUSED"; 416parameter implement_input_in_lcell = "UNUSED"; 417parameter invert_output = "OFF"; 418parameter intended_device_family = "Stratix"; 419parameter lpm_type = "altddio_bidir"; 420parameter lpm_hint = "UNUSED"; 421 422// INPUT PORT DECLARATION 423input [width-1:0] datain_h; 424input [width-1:0] datain_l; 425input inclock; 426input inclocken; 427input outclock; 428input outclocken; 429input aset; 430input aclr; 431input sset; 432input sclr; 433input oe; 434 435// OUTPUT PORT DECLARATION 436output [width-1:0] dataout_h; 437output [width-1:0] dataout_l; 438output [width-1:0] combout; 439output [width-1:0] oe_out; 440output [width-1:0] dqsundelayedout; 441// BIDIRECTIONAL PORT DECLARATION 442inout [width-1:0] padio; 443 444endmodule 445 446 447(* blackbox *) 448module altiobuf_in(datain, dataout); 449 450parameter enable_bus_hold = "FALSE"; 451parameter use_differential_mode = "FALSE"; 452parameter number_of_channels = 1; 453 454input [number_of_channels-1:0] datain; 455output [number_of_channels-1:0] dataout; 456 457endmodule 458 459(* blackbox *) 460module altiobuf_out(datain, dataout); 461 462parameter enable_bus_hold = "FALSE"; 463parameter use_differential_mode = "FALSE"; 464parameter use_oe = "FALSE"; 465parameter number_of_channels = 1; 466 467input [number_of_channels-1:0] datain; 468output [number_of_channels-1:0] dataout; 469 470endmodule 471 472(* blackbox *) 473module altiobuf_bidir(dataio, oe, datain, dataout); 474 475parameter number_of_channels = 1; 476parameter enable_bus_hold = "OFF"; 477 478inout [number_of_channels-1:0] dataio; 479input [number_of_channels-1:0] datain; 480output [number_of_channels-1:0] dataout; 481input [number_of_channels-1:0] oe; 482 483endmodule 484 485(* blackbox *) 486module altsyncram(clock0, clock1, address_a, data_a, rden_a, wren_a, byteena_a, q_a, addressstall_a, address_b, data_b, rden_b, wren_b, byteena_b, q_b, addressstall_b, clocken0, clocken1, clocken2, clocken3, aclr0, aclr1, eccstatus); 487 488parameter lpm_type = "altsyncram"; 489parameter operation_mode = "dual_port"; 490parameter ram_block_type = "auto"; 491parameter intended_device_family = "auto"; 492parameter power_up_uninitialized = "false"; 493parameter read_during_write_mode_mixed_ports = "dontcare"; 494parameter byte_size = 8; 495parameter widthad_a = 1; 496parameter width_a = 1; 497parameter width_byteena_a = 1; 498parameter numwords_a = 1; 499parameter clock_enable_input_a = "clocken0"; 500parameter widthad_b = 1; 501parameter width_b = 1; 502parameter numwords_b = 1; 503parameter address_aclr_b = "aclr0"; 504parameter address_reg_b = ""; 505parameter outdata_aclr_b = "aclr0"; 506parameter outdata_reg_b = ""; 507parameter clock_enable_input_b = "clocken0"; 508parameter clock_enable_output_b = "clocken0"; 509 510input clock0, clock1; 511input [widthad_a-1:0] address_a; 512input [width_a-1:0] data_a; 513input rden_a; 514input wren_a; 515input [(width_a/8)-1:0] byteena_a; 516input addressstall_a; 517 518output [width_a-1:0] q_a; 519 520input wren_b; 521input rden_b; 522input [widthad_b-1:0] address_b; 523input [width_b-1:0] data_b; 524input [(width_b/8)-1:0] byteena_b; 525input addressstall_b; 526 527output [width_b-1:0] q_b; 528 529input clocken0; 530input clocken1; 531input clocken2; 532input clocken3; 533 534input aclr0; 535input aclr1; 536 537output eccstatus; 538 539endmodule 540 541(* blackbox *) 542module cyclonev_mlab_cell(portaaddr, portadatain, portbaddr, portbdataout, ena0, clk0, clk1); 543 544parameter logical_ram_name = ""; 545parameter logical_ram_depth = 32; 546parameter logical_ram_width = 20; 547parameter mixed_port_feed_through_mode = "new"; 548parameter first_bit_number = 0; 549parameter first_address = 0; 550parameter last_address = 31; 551parameter address_width = 5; 552parameter data_width = 1; 553parameter byte_enable_mask_width = 1; 554parameter port_b_data_out_clock = "NONE"; 555parameter [639:0] mem_init0 = 640'b0; 556 557input [address_width-1:0] portaaddr, portbaddr; 558input [data_width-1:0] portadatain; 559output [data_width-1:0] portbdataout; 560input ena0, clk0, clk1; 561 562endmodule 563 564(* blackbox *) 565module cyclonev_mac(ax, ay, resulta); 566 567parameter ax_width = 9; 568parameter signed_max = "true"; 569parameter ay_scan_in_width = 9; 570parameter signed_may = "true"; 571parameter result_a_width = 18; 572parameter operation_mode = "M9x9"; 573 574input [ax_width-1:0] ax; 575input [ay_scan_in_width-1:0] ay; 576output [result_a_width-1:0] resulta; 577 578endmodule 579 580(* blackbox *) 581module cyclone10gx_mac(ax, ay, resulta); 582 583parameter ax_width = 18; 584parameter signed_max = "true"; 585parameter ay_scan_in_width = 18; 586parameter signed_may = "true"; 587parameter result_a_width = 36; 588parameter operation_mode = "M18X18_FULL"; 589 590input [ax_width-1:0] ax; 591input [ay_scan_in_width-1:0] ay; 592output [result_a_width-1:0] resulta; 593 594endmodule 595 596(* blackbox *) 597module cyclonev_ram_block(portaaddr, portadatain, portawe, portbaddr, portbdataout, portbre, clk0); 598 599parameter operation_mode = "dual_port"; 600parameter logical_ram_name = ""; 601parameter port_a_address_width = 10; 602parameter port_a_data_width = 10; 603parameter port_a_logical_ram_depth = 1024; 604parameter port_a_logical_ram_width = 10; 605parameter port_a_first_address = 0; 606parameter port_a_last_address = 1023; 607parameter port_a_first_bit_number = 0; 608parameter port_b_address_width = 10; 609parameter port_b_data_width = 10; 610parameter port_b_logical_ram_depth = 1024; 611parameter port_b_logical_ram_width = 10; 612parameter port_b_first_address = 0; 613parameter port_b_last_address = 1023; 614parameter port_b_first_bit_number = 0; 615parameter port_b_address_clock = "clock0"; 616parameter port_b_read_enable_clock = "clock0"; 617parameter mem_init0 = ""; 618parameter mem_init1 = ""; 619parameter mem_init2 = ""; 620parameter mem_init3 = ""; 621parameter mem_init4 = ""; 622 623input [port_a_address_width-1:0] portaaddr; 624input [port_b_address_width-1:0] portbaddr; 625input [port_a_data_width-1:0] portadatain; 626output [port_b_data_width-1:0] portbdataout; 627input clk0, portawe, portbre; 628 629endmodule 630 631(* blackbox *) 632module cyclone10gx_io_ibuf(i, ibar, dynamicterminationcontrol, o); 633 634parameter differential_mode ="false"; 635parameter bus_hold = "false"; 636parameter simulate_z_as = "Z"; 637parameter lpm_type = "cyclone10gx_io_ibuf"; 638 639(* iopad_external_pin *) input i; 640(* iopad_external_pin *) input ibar; 641input dynamicterminationcontrol; 642output o; 643 644endmodule 645 646(* blackbox *) 647module cyclone10gx_io_obuf(i, oe, dynamicterminationcontrol, seriesterminationcontrol, parallelterminationcontrol, devoe, o, obar); 648 649parameter open_drain_output = "false"; 650parameter bus_hold = "false"; 651parameter shift_series_termination_control = "false"; 652parameter sim_dynamic_termination_control_is_connected = "false"; 653parameter lpm_type = "cyclone10gx_io_obuf"; 654 655input i; 656input oe; 657input devoe; 658input dynamicterminationcontrol; 659input [15:0] seriesterminationcontrol; 660input [15:0] parallelterminationcontrol; 661(* iopad_external_pin *) output o; 662(* iopad_external_pin *) output obar; 663 664endmodule 665 666(* blackbox *) 667module cyclonev_clkena(inclk, ena, enaout, outclk); 668 669parameter clock_type = "auto"; 670parameter ena_register_mode = "always enabled"; 671parameter lpm_type = "cyclonev_clkena"; 672parameter ena_register_power_up = "high"; 673parameter disable_mode = "low"; 674parameter test_syn = "high"; 675 676input inclk; 677input ena; 678output enaout; 679output outclk; 680 681endmodule 682 683(* blackbox *) 684module cyclone10gx_clkena(inclk, ena, enaout, outclk); 685 686parameter clock_type = "auto"; 687parameter ena_register_mode = "always enabled"; 688parameter lpm_type = "cyclone10gx_clkena"; 689parameter ena_register_power_up = "high"; 690parameter disable_mode = "low"; 691parameter test_syn = "high"; 692 693input inclk; 694input ena; 695output enaout; 696output outclk; 697 698endmodule 699 700// Internal interfaces 701(* keep *) 702module cyclonev_oscillator(oscena, clkout, clkout1); 703 704input oscena; 705output clkout; 706output clkout1; 707 708endmodule 709 710// HPS interfaces 711(* keep *) 712module cyclonev_hps_interface_mpu_general_purpose(gp_in, gp_out); 713 714input [31:0] gp_in; 715output [31:0] gp_out; 716 717endmodule 718