1 //===-- MipsSubtarget.h - Define Subtarget for the Mips ---------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file declares the Mips specific subclass of TargetSubtargetInfo. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H 14 #define LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H 15 16 #include "MCTargetDesc/MipsABIInfo.h" 17 #include "MipsFrameLowering.h" 18 #include "MipsISelLowering.h" 19 #include "MipsInstrInfo.h" 20 #include "llvm/CodeGen/GlobalISel/CallLowering.h" 21 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h" 22 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h" 23 #include "llvm/CodeGen/RegisterBankInfo.h" 24 #include "llvm/CodeGen/SelectionDAGTargetInfo.h" 25 #include "llvm/CodeGen/TargetSubtargetInfo.h" 26 #include "llvm/IR/DataLayout.h" 27 #include "llvm/MC/MCInstrItineraries.h" 28 #include "llvm/Support/ErrorHandling.h" 29 #include <string> 30 31 #define GET_SUBTARGETINFO_HEADER 32 #include "MipsGenSubtargetInfo.inc" 33 34 namespace llvm { 35 class StringRef; 36 37 class MipsTargetMachine; 38 39 class MipsSubtarget : public MipsGenSubtargetInfo { 40 virtual void anchor(); 41 42 enum MipsArchEnum { 43 MipsDefault, 44 Mips1, Mips2, Mips32, Mips32r2, Mips32r3, Mips32r5, Mips32r6, Mips32Max, 45 Mips3, Mips4, Mips5, Mips64, Mips64r2, Mips64r3, Mips64r5, Mips64r6 46 }; 47 48 enum class CPU { P5600 }; 49 50 // Used to avoid printing dsp warnings multiple times. 51 static bool DspWarningPrinted; 52 53 // Used to avoid printing msa warnings multiple times. 54 static bool MSAWarningPrinted; 55 56 // Used to avoid printing crc warnings multiple times. 57 static bool CRCWarningPrinted; 58 59 // Used to avoid printing ginv warnings multiple times. 60 static bool GINVWarningPrinted; 61 62 // Used to avoid printing Mips1 warnings multiple times. 63 static bool MIPS1WarningPrinted; 64 65 // Used to avoid printing virt warnings multiple times. 66 static bool VirtWarningPrinted; 67 68 // Mips architecture version 69 MipsArchEnum MipsArchVersion; 70 71 // Processor implementation (unused but required to exist by 72 // tablegen-erated code). 73 CPU ProcImpl; 74 75 // IsLittle - The target is Little Endian 76 bool IsLittle; 77 78 // IsSoftFloat - The target does not support any floating point instructions. 79 bool IsSoftFloat; 80 81 // IsSingleFloat - The target only supports single precision float 82 // point operations. This enable the target to use all 32 32-bit 83 // floating point registers instead of only using even ones. 84 bool IsSingleFloat; 85 86 // IsFPXX - MIPS O32 modeless ABI. 87 bool IsFPXX; 88 89 // NoABICalls - Disable SVR4-style position-independent code. 90 bool NoABICalls; 91 92 // Abs2008 - Use IEEE 754-2008 abs.fmt instruction. 93 bool Abs2008; 94 95 // IsFP64bit - The target processor has 64-bit floating point registers. 96 bool IsFP64bit; 97 98 /// Are odd single-precision registers permitted? 99 /// This corresponds to -modd-spreg and -mno-odd-spreg 100 bool UseOddSPReg; 101 102 // IsNan2008 - IEEE 754-2008 NaN encoding. 103 bool IsNaN2008bit; 104 105 // IsGP64bit - General-purpose registers are 64 bits wide 106 bool IsGP64bit; 107 108 // IsPTR64bit - Pointers are 64 bit wide 109 bool IsPTR64bit; 110 111 // HasVFPU - Processor has a vector floating point unit. 112 bool HasVFPU; 113 114 // CPU supports cnMIPS (Cavium Networks Octeon CPU). 115 bool HasCnMips; 116 117 // CPU supports cnMIPSP (Cavium Networks Octeon+ CPU). 118 bool HasCnMipsP; 119 120 // isLinux - Target system is Linux. Is false we consider ELFOS for now. 121 bool IsLinux; 122 123 // UseSmallSection - Small section is used. 124 bool UseSmallSection; 125 126 /// Features related to the presence of specific instructions. 127 128 // HasMips3_32 - The subset of MIPS-III instructions added to MIPS32 129 bool HasMips3_32; 130 131 // HasMips3_32r2 - The subset of MIPS-III instructions added to MIPS32r2 132 bool HasMips3_32r2; 133 134 // HasMips4_32 - Has the subset of MIPS-IV present in MIPS32 135 bool HasMips4_32; 136 137 // HasMips4_32r2 - Has the subset of MIPS-IV present in MIPS32r2 138 bool HasMips4_32r2; 139 140 // HasMips5_32r2 - Has the subset of MIPS-V present in MIPS32r2 141 bool HasMips5_32r2; 142 143 // InMips16 -- can process Mips16 instructions 144 bool InMips16Mode; 145 146 // Mips16 hard float 147 bool InMips16HardFloat; 148 149 // InMicroMips -- can process MicroMips instructions 150 bool InMicroMipsMode; 151 152 // HasDSP, HasDSPR2, HasDSPR3 -- supports DSP ASE. 153 bool HasDSP, HasDSPR2, HasDSPR3; 154 155 // Has3D -- Supports Mips3D ASE. 156 bool Has3D; 157 158 // Allow mixed Mips16 and Mips32 in one source file 159 bool AllowMixed16_32; 160 161 // Optimize for space by compiling all functions as Mips 16 unless 162 // it needs floating point. Functions needing floating point are 163 // compiled as Mips32 164 bool Os16; 165 166 // HasMSA -- supports MSA ASE. 167 bool HasMSA; 168 169 // UseTCCInDIV -- Enables the use of trapping in the assembler. 170 bool UseTCCInDIV; 171 172 // Sym32 -- On Mips64 symbols are 32 bits. 173 bool HasSym32; 174 175 // HasEVA -- supports EVA ASE. 176 bool HasEVA; 177 178 // nomadd4 - disables generation of 4-operand madd.s, madd.d and 179 // related instructions. 180 bool DisableMadd4; 181 182 // HasMT -- support MT ASE. 183 bool HasMT; 184 185 // HasCRC -- supports R6 CRC ASE 186 bool HasCRC; 187 188 // HasVirt -- supports Virtualization ASE 189 bool HasVirt; 190 191 // HasGINV -- supports R6 Global INValidate ASE 192 bool HasGINV; 193 194 // Use hazard variants of the jump register instructions for indirect 195 // function calls and jump tables. 196 bool UseIndirectJumpsHazard; 197 198 // Disable use of the `jal` instruction. 199 bool UseLongCalls = false; 200 201 // Assume 32-bit GOT. 202 bool UseXGOT = false; 203 204 /// The minimum alignment known to hold of the stack frame on 205 /// entry to the function and which must be maintained by every function. 206 Align stackAlignment; 207 208 /// The overridden stack alignment. 209 MaybeAlign StackAlignOverride; 210 211 InstrItineraryData InstrItins; 212 213 // We can override the determination of whether we are in mips16 mode 214 // as from the command line 215 enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode; 216 217 const MipsTargetMachine &TM; 218 219 Triple TargetTriple; 220 221 const SelectionDAGTargetInfo TSInfo; 222 std::unique_ptr<const MipsInstrInfo> InstrInfo; 223 std::unique_ptr<const MipsFrameLowering> FrameLowering; 224 std::unique_ptr<const MipsTargetLowering> TLInfo; 225 226 public: 227 bool isPositionIndependent() const; 228 /// This overrides the PostRAScheduler bit in the SchedModel for each CPU. 229 bool enablePostRAScheduler() const override; 230 void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override; 231 CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const override; 232 233 bool isABI_N64() const; 234 bool isABI_N32() const; 235 bool isABI_O32() const; 236 const MipsABIInfo &getABI() const; isABI_FPXX()237 bool isABI_FPXX() const { return isABI_O32() && IsFPXX; } 238 239 /// This constructor initializes the data members to match that 240 /// of the specified triple. 241 MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS, bool little, 242 const MipsTargetMachine &TM, MaybeAlign StackAlignOverride); 243 244 /// ParseSubtargetFeatures - Parses features string setting specified 245 /// subtarget options. Definition of function is auto generated by tblgen. 246 void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS); 247 hasMips1()248 bool hasMips1() const { return MipsArchVersion >= Mips1; } hasMips2()249 bool hasMips2() const { return MipsArchVersion >= Mips2; } hasMips3()250 bool hasMips3() const { return MipsArchVersion >= Mips3; } hasMips4()251 bool hasMips4() const { return MipsArchVersion >= Mips4; } hasMips5()252 bool hasMips5() const { return MipsArchVersion >= Mips5; } hasMips4_32()253 bool hasMips4_32() const { return HasMips4_32; } hasMips4_32r2()254 bool hasMips4_32r2() const { return HasMips4_32r2; } hasMips32()255 bool hasMips32() const { 256 return (MipsArchVersion >= Mips32 && MipsArchVersion < Mips32Max) || 257 hasMips64(); 258 } hasMips32r2()259 bool hasMips32r2() const { 260 return (MipsArchVersion >= Mips32r2 && MipsArchVersion < Mips32Max) || 261 hasMips64r2(); 262 } hasMips32r3()263 bool hasMips32r3() const { 264 return (MipsArchVersion >= Mips32r3 && MipsArchVersion < Mips32Max) || 265 hasMips64r2(); 266 } hasMips32r5()267 bool hasMips32r5() const { 268 return (MipsArchVersion >= Mips32r5 && MipsArchVersion < Mips32Max) || 269 hasMips64r5(); 270 } hasMips32r6()271 bool hasMips32r6() const { 272 return (MipsArchVersion >= Mips32r6 && MipsArchVersion < Mips32Max) || 273 hasMips64r6(); 274 } hasMips64()275 bool hasMips64() const { return MipsArchVersion >= Mips64; } hasMips64r2()276 bool hasMips64r2() const { return MipsArchVersion >= Mips64r2; } hasMips64r3()277 bool hasMips64r3() const { return MipsArchVersion >= Mips64r3; } hasMips64r5()278 bool hasMips64r5() const { return MipsArchVersion >= Mips64r5; } hasMips64r6()279 bool hasMips64r6() const { return MipsArchVersion >= Mips64r6; } 280 hasCnMips()281 bool hasCnMips() const { return HasCnMips; } hasCnMipsP()282 bool hasCnMipsP() const { return HasCnMipsP; } 283 isLittle()284 bool isLittle() const { return IsLittle; } isABICalls()285 bool isABICalls() const { return !NoABICalls; } isFPXX()286 bool isFPXX() const { return IsFPXX; } isFP64bit()287 bool isFP64bit() const { return IsFP64bit; } useOddSPReg()288 bool useOddSPReg() const { return UseOddSPReg; } noOddSPReg()289 bool noOddSPReg() const { return !UseOddSPReg; } isNaN2008()290 bool isNaN2008() const { return IsNaN2008bit; } inAbs2008Mode()291 bool inAbs2008Mode() const { return Abs2008; } isGP64bit()292 bool isGP64bit() const { return IsGP64bit; } isGP32bit()293 bool isGP32bit() const { return !IsGP64bit; } getGPRSizeInBytes()294 unsigned getGPRSizeInBytes() const { return isGP64bit() ? 8 : 4; } isPTR64bit()295 bool isPTR64bit() const { return IsPTR64bit; } isPTR32bit()296 bool isPTR32bit() const { return !IsPTR64bit; } hasSym32()297 bool hasSym32() const { 298 return (HasSym32 && isABI_N64()) || isABI_N32() || isABI_O32(); 299 } isSingleFloat()300 bool isSingleFloat() const { return IsSingleFloat; } isTargetELF()301 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); } hasVFPU()302 bool hasVFPU() const { return HasVFPU; } inMips16Mode()303 bool inMips16Mode() const { return InMips16Mode; } inMips16ModeDefault()304 bool inMips16ModeDefault() const { 305 return InMips16Mode; 306 } 307 // Hard float for mips16 means essentially to compile as soft float 308 // but to use a runtime library for soft float that is written with 309 // native mips32 floating point instructions (those runtime routines 310 // run in mips32 hard float mode). inMips16HardFloat()311 bool inMips16HardFloat() const { 312 return inMips16Mode() && InMips16HardFloat; 313 } inMicroMipsMode()314 bool inMicroMipsMode() const { return InMicroMipsMode && !InMips16Mode; } inMicroMips32r6Mode()315 bool inMicroMips32r6Mode() const { 316 return inMicroMipsMode() && hasMips32r6(); 317 } hasDSP()318 bool hasDSP() const { return HasDSP; } hasDSPR2()319 bool hasDSPR2() const { return HasDSPR2; } hasDSPR3()320 bool hasDSPR3() const { return HasDSPR3; } has3D()321 bool has3D() const { return Has3D; } hasMSA()322 bool hasMSA() const { return HasMSA; } disableMadd4()323 bool disableMadd4() const { return DisableMadd4; } hasEVA()324 bool hasEVA() const { return HasEVA; } hasMT()325 bool hasMT() const { return HasMT; } hasCRC()326 bool hasCRC() const { return HasCRC; } hasVirt()327 bool hasVirt() const { return HasVirt; } hasGINV()328 bool hasGINV() const { return HasGINV; } useIndirectJumpsHazard()329 bool useIndirectJumpsHazard() const { 330 return UseIndirectJumpsHazard && hasMips32r2(); 331 } useSmallSection()332 bool useSmallSection() const { return UseSmallSection; } 333 hasStandardEncoding()334 bool hasStandardEncoding() const { return !InMips16Mode && !InMicroMipsMode; } 335 useSoftFloat()336 bool useSoftFloat() const { return IsSoftFloat; } 337 useLongCalls()338 bool useLongCalls() const { return UseLongCalls; } 339 useXGOT()340 bool useXGOT() const { return UseXGOT; } 341 enableLongBranchPass()342 bool enableLongBranchPass() const { 343 return hasStandardEncoding() || inMicroMipsMode() || allowMixed16_32(); 344 } 345 346 /// Features related to the presence of specific instructions. hasExtractInsert()347 bool hasExtractInsert() const { return !inMips16Mode() && hasMips32r2(); } hasMTHC1()348 bool hasMTHC1() const { return hasMips32r2(); } 349 allowMixed16_32()350 bool allowMixed16_32() const { return inMips16ModeDefault() | 351 AllowMixed16_32; } 352 os16()353 bool os16() const { return Os16; } 354 isTargetNaCl()355 bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); } 356 isXRaySupported()357 bool isXRaySupported() const override { return true; } 358 359 // for now constant islands are on for the whole compilation unit but we only 360 // really use them if in addition we are in mips16 mode 361 static bool useConstantIslands(); 362 getStackAlignment()363 Align getStackAlignment() const { return stackAlignment; } 364 365 // Grab relocation model 366 Reloc::Model getRelocationModel() const; 367 368 MipsSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS, 369 const TargetMachine &TM); 370 371 /// Does the system support unaligned memory access. 372 /// 373 /// MIPS32r6/MIPS64r6 require full unaligned access support but does not 374 /// specify which component of the system provides it. Hardware, software, and 375 /// hybrid implementations are all valid. systemSupportsUnalignedAccess()376 bool systemSupportsUnalignedAccess() const { return hasMips32r6(); } 377 378 // Set helper classes 379 void setHelperClassesMips16(); 380 void setHelperClassesMipsSE(); 381 getSelectionDAGInfo()382 const SelectionDAGTargetInfo *getSelectionDAGInfo() const override { 383 return &TSInfo; 384 } getInstrInfo()385 const MipsInstrInfo *getInstrInfo() const override { return InstrInfo.get(); } getFrameLowering()386 const TargetFrameLowering *getFrameLowering() const override { 387 return FrameLowering.get(); 388 } getRegisterInfo()389 const MipsRegisterInfo *getRegisterInfo() const override { 390 return &InstrInfo->getRegisterInfo(); 391 } getTargetLowering()392 const MipsTargetLowering *getTargetLowering() const override { 393 return TLInfo.get(); 394 } getInstrItineraryData()395 const InstrItineraryData *getInstrItineraryData() const override { 396 return &InstrItins; 397 } 398 399 protected: 400 // GlobalISel related APIs. 401 std::unique_ptr<CallLowering> CallLoweringInfo; 402 std::unique_ptr<LegalizerInfo> Legalizer; 403 std::unique_ptr<RegisterBankInfo> RegBankInfo; 404 std::unique_ptr<InstructionSelector> InstSelector; 405 406 public: 407 const CallLowering *getCallLowering() const override; 408 const LegalizerInfo *getLegalizerInfo() const override; 409 const RegisterBankInfo *getRegBankInfo() const override; 410 InstructionSelector *getInstructionSelector() const override; 411 }; 412 } // End llvm namespace 413 414 #endif 415