1 /* 2 * Copyright (c) 1988, 1992, 1993 3 * The Regents of the University of California. All rights reserved. 4 * 5 * This software was developed by the Computer Systems Engineering group 6 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 7 * contributed to Berkeley. 8 * 9 * All advertising materials mentioning features or use of this software 10 * must display the following acknowledgement: 11 * This product includes software developed by the University of 12 * California, Lawrence Berkeley Laboratory. 13 * 14 * %sccs.include.redist.c% 15 * 16 * @(#)espreg.h 8.2 (Berkeley) 12/14/93 17 * 18 * from: $Header: espreg.h,v 1.7 92/11/26 02:28:10 torek Exp $ (LBL) 19 * 20 * Derived from Mary Baker's devSCSIC90.c from the Berkeley 21 * Sprite project, which is: 22 * 23 * Copyright 1988 Regents of the University of California 24 * Permission to use, copy, modify, and distribute this 25 * software and its documentation for any purpose and without 26 * fee is hereby granted, provided that the above copyright 27 * notice appear in all copies. The University of California 28 * makes no representations about the suitability of this 29 * software for any purpose. It is provided "as is" without 30 * express or implied warranty. 31 */ 32 33 /* 34 * Emulex ESP100, ESP100A, and ESP200 registers, as found on the 35 * Sun-4c Sbus. 36 * 37 * The registers are all bytes, and all on longword boundaries. 38 * Grody to the max! 39 */ 40 struct espreg { 41 u_char esp_tcl; /* transfer count low (byte 0) (rw) */ 42 u_char esp_xxx0[3]; 43 u_char esp_tch; /* transfer count high (byte 1) (rw) */ 44 u_char esp_xxx1[3]; 45 u_char esp_fifo; /* fifo data register (rw) */ 46 u_char esp_xxx2[3]; 47 u_char esp_cmd; /* command (rw) */ 48 u_char esp_xxx3[3]; 49 u_char esp_stat; /* status (ro); scsi id (wo) */ 50 #define esp_id esp_stat 51 u_char esp_xxx4[3]; 52 u_char esp_intr; /* interrupt (ro); timeout (wo) */ 53 #define esp_timeout esp_intr 54 u_char esp_xxx5[3]; 55 u_char esp_step; /* sequence step (ro); sync period (wo) */ 56 #define esp_syncperiod esp_step 57 u_char esp_xxx6[3]; 58 u_char esp_fflags; /* fifo flags (ro); sync offset (wo) */ 59 #define esp_syncoff esp_fflags 60 u_char esp_xxx7[3]; 61 u_char esp_conf1; /* configuration #1 (rw) */ 62 u_char esp_xxx8[3]; 63 u_char esp_ccf; /* clock conversion factor (wo) */ 64 u_char esp_xxx9[3]; 65 u_char esp_test; /* test (do not use) */ 66 u_char esp_xxxA[3]; 67 u_char esp_conf2; /* configuration #2 (rw, ESP100A/2xx) */ 68 u_char esp_xxxB[3]; 69 u_char esp_conf3; /* configuration #3 (rw, ESP-236) */ 70 u_char esp_xxxC[3]; 71 }; 72 73 /* THE REST OF THESE NAMES COULD STAND TO BE SHORTENED */ 74 75 /* 76 * Bits in esp_cmd. Note that the cmd register is two levels deep (see 77 * Emulex documentation, p. 4-3); our typical usage is to set the command, 78 * then set it again with DMA. 79 * 80 * Targets will use disconnected and target mode commands; initiators will use 81 * disconnected and initiator mode commands. Bit 0x40 indicates disconnected 82 * mode, 0x20 target mode, and 0x10 initiator mode. (However, everyone can 83 * use the miscellaneous commands, which have none of those bits set.) 84 */ 85 #define ESPCMD_DMA 0x80 /* flag => do DMA */ 86 87 /* miscellaneous */ 88 #define ESPCMD_NOP 0x00 /* do nothing */ 89 #define ESPCMD_FLUSH_FIFO 0x01 /* flush FIFO */ 90 #define ESPCMD_RESET_CHIP 0x02 /* reset ESP chip */ 91 #define ESPCMD_RESET_BUS 0x03 /* reset SCSI bus */ 92 /* NB: fifo flush takes time, may need delay or NOP to allow completion */ 93 94 /* disconnected */ 95 #define ESPCMD_RESEL_SEQ 0x40 /* reselect sequence */ 96 #define ESPCMD_SEL_NATN 0x41 /* select without ATN sequence */ 97 #define ESPCMD_SEL_ATN 0x42 /* select with ATN sequence */ 98 #define ESPCMD_SEL_ATNS 0x43 /* select with ATN & stop seq */ 99 #define ESPCMD_SEL_ENA 0x44 /* enable selection/reselection */ 100 #define ESPCMD_SEL_DIS 0x45 /* disable selection/reselection */ 101 #define ESPCMD_SEL_ATN3 0x46 /* select with ATN3 sequence */ 102 103 /* target state */ 104 #define ESPCMD_SEND_MSG 0x20 /* send message */ 105 #define ESPCMD_SEND_STATUS 0x21 /* send status */ 106 #define ESPCMD_SEND_DATA 0x22 /* send data */ 107 #define ESPCMD_DIS_SEQ 0x23 /* disconnect sequence */ 108 #define ESPCMD_TERM_SEQ 0x24 /* terminate sequence */ 109 #define ESPCMD_TARG_COMP 0x25 /* target command complete sequence */ 110 #define ESPCMD_DISCONNECT 0x27 /* disconnect */ 111 #define ESPCMD_RCV_MSG 0x28 /* receive message sequence */ 112 #define ESPCMD_RCV_CMD 0x29 /* receive command */ 113 #define ESPCMD_RCV_DATA 0x2a /* receive data */ 114 #define ESPCMD_REC_CMD_SEQ 0x2b /* receive command sequence */ 115 #define ESPCMD_STOP_DMA 0x04 /* stop DMA (see p. 4-6) */ 116 /* ESPCMD_TARG_ABORT 0x06 target abort sequence */ 117 118 /* initiator state */ 119 #define ESPCMD_XFER_INFO 0x10 /* transfer information */ 120 #define ESPCMD_INIT_COMP 0x11 /* initiator command complete seq */ 121 #define ESPCMD_MSG_ACCEPT 0x12 /* message accepted */ 122 #define ESPCMD_XFER_PAD 0x18 /* transfer pad (use only w/ DMA) */ 123 #define ESPCMD_SET_ATN 0x1a /* set ATN */ 124 #define ESPCMD_RESET_ATN 0x1b /* reset ATN */ 125 126 /* 127 * Bits in esp_stat. 128 * Bits 3 through 7 are latched until esp_intr is read; 129 * bits 0 through 2 (the phase) are not normally latched. 130 * The interrupt bit is set even if interrupts are disabled. 131 * Hardware or software reset, or reading esp_intr, will 132 * clear the interrupt and turn off ESPSTAT_INT. 133 */ 134 #ifdef notdef 135 #define ESPSTAT_INT 0x80 /* ASC interrupting processor */ 136 #else 137 #define ESPSTAT_XXX 0x80 /* rumored unreliable: use dma IP */ 138 #endif 139 #define ESPSTAT_GE 0x40 /* gross error */ 140 #define ESPSTAT_PE 0x20 /* parity error */ 141 #define ESPSTAT_ERR 0x60 /* pseudo composite */ 142 #define ESPSTAT_TC 0x10 /* terminal count */ 143 #define ESPSTAT_VGC 0x08 /* valid group code */ 144 #define ESPSTAT_MSG 0x04 /* MSG line from SCSI bus */ 145 #define ESPSTAT_CD 0x02 /* CD line from SCSI bus */ 146 #define ESPSTAT_IO 0x01 /* IO line from SCSI bus */ 147 #define ESPSTAT_PHASE 7 /* phase mask */ 148 #define ESPPHASE_DATA_OUT 0 /* data out */ 149 #define ESPPHASE_DATA_IN 1 /* data in */ 150 #define ESPPHASE_CMD 2 /* command */ 151 #define ESPPHASE_STATUS 3 /* status */ 152 #define ESPPHASE_MSG_OUT 6 /* message out (w.r.t. initiator) */ 153 #define ESPPHASE_MSG_IN 7 /* message in */ 154 155 #ifdef ESP_PHASE_NAMES 156 /* printed as `... during %s phase' */ 157 char *espphases[] = 158 { "data out", "data in", "command", "status", 159 "impossible(4)", "impossible(5)", "message out", "message in" }; 160 #endif 161 162 #define ESPSTAT_BITS "\20\10INT\7GE\6PE\5TC\4VGC\3MSG\2CD\1IO" 163 164 /* 165 * Bits in esp_intr. 166 */ 167 #define ESPINTR_SBR 0x80 /* SCSI bus reset detected */ 168 #define ESPINTR_ILC 0x40 /* illegal command */ 169 #define ESPINTR_DSC 0x20 /* target disconnected, or timeout */ 170 #define ESPINTR_SVC 0x10 /* a device wants bus service */ 171 #define ESPINTR_CMP 0x08 /* function complete */ 172 #define ESPINTR_RSL 0x04 /* reselected */ 173 #define ESPINTR_SAT 0x02 /* selected with ATN */ 174 #define ESPINTR_SEL 0x01 /* selected (no ATN) */ 175 176 #define ESPINTR_BITS "\20\10SBR\7ILC\6DSC\5SVC\4CMP\3RSL\2SAT\1SEL" 177 178 /* 179 * Formula for select/reselect timeout (esp_timeout). 180 * TU = 7682 * CCF * TCP 181 * T / TU = register value 182 * CCF = clock conversion factor 183 * TCP = input clock period (in same units as T) 184 * TU = time unit (i.e., the esp_timeout register counts in TUs) 185 * T = desired timeout 186 * (i.e., we want ceil(timeout / (7682*ccf*tcp))). If timeout is in ms., 187 * and tcp is in MHz, then (ccf * 7682)/tcp gives us 1000*TU, and 188 * 1000*timeout/(1000*TU) gives us our result (but remember to round up). 189 * 190 * N.B.: The register value 0 gives a TU of 256. 191 */ 192 #define ESPTIMO_REGVAL(timo_ms, ccf, mhz) \ 193 howmany(1000 * (timo_ms), ((ccf) * 7682) / (mhz)) 194 195 /* 196 * Value in esp_step. These tell us how much of a `sequence' completed, 197 * and apply to the following sequenced operations: 198 * [initiator] 199 * select without ATN 200 * select with ATN 201 * select with ATN3 202 * select with ATN and stop 203 * [target] 204 * bus-initiated select with ATN 205 * bus-initiated select 206 * receive command sequence 207 * command complete sequence 208 * disconnect sequence 209 * terminate sequence 210 * The actual values are too complicated to define here, except that 211 * code 4 always means `everything worked and the command went out' 212 * (and is thus typical for everything except ATN-and-stop). 213 */ 214 #define ESPSTEP_MASK 0x07 /* only these bits are valid */ 215 #define ESPSTEP_DONE 4 /* command went out */ 216 217 /* 218 * Synchronous transfer period (esp_syncperiod, 5 bits). 219 * The minimum clocks-per-period is 5 and the max is 35; 220 * the default on reset is 5. Note that a period value of 4 221 * actually gives 5 clocks. 222 */ 223 #define ESP_CLOCKS_TO_PERIOD(nclocks) ((nclocks) & 31) 224 225 /* 226 * Bits in fifo flags (esp_fflags) register. The FIFO itself 227 * is only 16 bytes, so the byte count fits in 5 bits. Normally 228 * a copy of the sequence step register appears in the top 3 bits, 229 * but in test mode the chip re-uses one of those for a synchronous 230 * offset bit; in any case, they are pretty much worthless. 231 * 232 * Note that the fifo flags register must not be read while the 233 * fifo is changing. 234 */ 235 #define ESP_NFIFO(fflags) ((fflags) & 0x1f) 236 237 #define ESPFFLAGS_TM_SOFFNZ 0x20 /* nonzero sync offset (test mode) */ 238 239 /* 240 * Bits in esp_conf1. 241 */ 242 #define ESPCONF1_SLOW_CABLE 0x80 /* ``slow cable'' mode */ 243 #define ESPCONF1_REPORT 0x40 /* disable reporting of interrupts 244 from scsi bus reset command */ 245 #define ESPCONF1_PARTST 0x20 /* parity test mode */ 246 #define ESPCONF1_PARENB 0x10 /* enable parity */ 247 #define ESPCONF1_TEST 0x08 /* chip test mode */ 248 #define ESPCONF1_ID_MASK 0x07 /* SCSI bus ID field */ 249 250 #define ESPCONF1_BITS "\20\10SLOW_CABLE\7REPORT\6PARTST\5PARENB\4TEST" 251 252 /* 253 * Values for clock conversion factor (esp_ccf). 254 */ 255 #define ESPCCF_FROMMHZ(mhz) (((mhz) + 4) / 5) 256 #define ESPCCF_MIN 2 /* minimum CCF value */ 257 258 /* 259 * Bits in esp_test (for board testing only; can only be used in test mode). 260 */ 261 #define ESPTEST_MBZ 0xf8 /* reserved; must be 0 */ 262 #define ESPTEST_TRISTATE 0x04 /* all output pins tristated */ 263 #define ESPTEST_INITIATOR 0x02 /* operate as initiator */ 264 #define ESPTEST_TARGET 0x01 /* operate as target */ 265 266 /* 267 * Bits in esp_conf2. 268 */ 269 #define ESPCONF2_RSVD 0xe0 /* reserved */ 270 #define ESPCONF2_TRISTATE_DMA 0x10 /* tristate the DMA REQ pin */ 271 #define ESPCONF2_SCSI2 0x08 /* enable SCSI 2 (see p. 4-18) */ 272 #define ESPCONF2_TBPA 0x04 /* enable target bad parity abort */ 273 #define ESPCONF2_RPE 0x02 /* register parity ena (ESP2xx only) */ 274 #define ESPCONF2_DPE 0x01 /* DMA parity enable (ESP2xx only) */ 275