1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Christian König.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Christian König
25 * Rafał Miłecki
26 */
27 #include <linux/hdmi.h>
28 #include <drm/drmP.h>
29 #include <drm/radeon_drm.h>
30 #include "radeon.h"
31 #include "radeon_asic.h"
32 #include "radeon_audio.h"
33 #include "evergreend.h"
34 #include "atom.h"
35
36 /* enable the audio stream */
37 void dce4_audio_enable(struct radeon_device *rdev,
38 struct r600_audio_pin *pin,
39 u8 enable_mask);
dce4_audio_enable(struct radeon_device * rdev,struct r600_audio_pin * pin,u8 enable_mask)40 void dce4_audio_enable(struct radeon_device *rdev,
41 struct r600_audio_pin *pin,
42 u8 enable_mask)
43 {
44 u32 tmp = RREG32(AZ_HOT_PLUG_CONTROL);
45
46 if (!pin)
47 return;
48
49 if (enable_mask) {
50 tmp |= AUDIO_ENABLED;
51 if (enable_mask & 1)
52 tmp |= PIN0_AUDIO_ENABLED;
53 if (enable_mask & 2)
54 tmp |= PIN1_AUDIO_ENABLED;
55 if (enable_mask & 4)
56 tmp |= PIN2_AUDIO_ENABLED;
57 if (enable_mask & 8)
58 tmp |= PIN3_AUDIO_ENABLED;
59 } else {
60 tmp &= ~(AUDIO_ENABLED |
61 PIN0_AUDIO_ENABLED |
62 PIN1_AUDIO_ENABLED |
63 PIN2_AUDIO_ENABLED |
64 PIN3_AUDIO_ENABLED);
65 }
66
67 WREG32(AZ_HOT_PLUG_CONTROL, tmp);
68 }
69
70 void evergreen_hdmi_update_acr(struct drm_encoder *encoder, long offset,
71 const struct radeon_hdmi_acr *acr);
evergreen_hdmi_update_acr(struct drm_encoder * encoder,long offset,const struct radeon_hdmi_acr * acr)72 void evergreen_hdmi_update_acr(struct drm_encoder *encoder, long offset,
73 const struct radeon_hdmi_acr *acr)
74 {
75 struct drm_device *dev = encoder->dev;
76 struct radeon_device *rdev = dev->dev_private;
77 int bpc = 8;
78
79 if (encoder->crtc) {
80 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
81 bpc = radeon_crtc->bpc;
82 }
83
84 if (bpc > 8)
85 WREG32(HDMI_ACR_PACKET_CONTROL + offset,
86 HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */
87 else
88 WREG32(HDMI_ACR_PACKET_CONTROL + offset,
89 HDMI_ACR_SOURCE | /* select SW CTS value */
90 HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */
91
92 WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr->cts_32khz));
93 WREG32(HDMI_ACR_32_1 + offset, acr->n_32khz);
94
95 WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr->cts_44_1khz));
96 WREG32(HDMI_ACR_44_1 + offset, acr->n_44_1khz);
97
98 WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr->cts_48khz));
99 WREG32(HDMI_ACR_48_1 + offset, acr->n_48khz);
100 }
101
102 void dce4_afmt_write_latency_fields(struct drm_encoder *encoder,
103 struct drm_connector *connector, struct drm_display_mode *mode);
dce4_afmt_write_latency_fields(struct drm_encoder * encoder,struct drm_connector * connector,struct drm_display_mode * mode)104 void dce4_afmt_write_latency_fields(struct drm_encoder *encoder,
105 struct drm_connector *connector, struct drm_display_mode *mode)
106 {
107 struct radeon_device *rdev = encoder->dev->dev_private;
108 u32 tmp = 0;
109
110 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
111 if (connector->latency_present[1])
112 tmp = VIDEO_LIPSYNC(connector->video_latency[1]) |
113 AUDIO_LIPSYNC(connector->audio_latency[1]);
114 else
115 tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);
116 } else {
117 if (connector->latency_present[0])
118 tmp = VIDEO_LIPSYNC(connector->video_latency[0]) |
119 AUDIO_LIPSYNC(connector->audio_latency[0]);
120 else
121 tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);
122 }
123 WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC, tmp);
124 }
125
126 void dce4_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder,
127 u8 *sadb, int sad_count);
dce4_afmt_hdmi_write_speaker_allocation(struct drm_encoder * encoder,u8 * sadb,int sad_count)128 void dce4_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder,
129 u8 *sadb, int sad_count)
130 {
131 struct radeon_device *rdev = encoder->dev->dev_private;
132 u32 tmp;
133
134 /* program the speaker allocation */
135 tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER);
136 tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK);
137 /* set HDMI mode */
138 tmp |= HDMI_CONNECTION;
139 if (sad_count)
140 tmp |= SPEAKER_ALLOCATION(sadb[0]);
141 else
142 tmp |= SPEAKER_ALLOCATION(5); /* stereo */
143 WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp);
144 }
145
146 void dce4_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder,
147 u8 *sadb, int sad_count);
dce4_afmt_dp_write_speaker_allocation(struct drm_encoder * encoder,u8 * sadb,int sad_count)148 void dce4_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder,
149 u8 *sadb, int sad_count)
150 {
151 struct radeon_device *rdev = encoder->dev->dev_private;
152 u32 tmp;
153
154 /* program the speaker allocation */
155 tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER);
156 tmp &= ~(HDMI_CONNECTION | SPEAKER_ALLOCATION_MASK);
157 /* set DP mode */
158 tmp |= DP_CONNECTION;
159 if (sad_count)
160 tmp |= SPEAKER_ALLOCATION(sadb[0]);
161 else
162 tmp |= SPEAKER_ALLOCATION(5); /* stereo */
163 WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp);
164 }
165
166 void evergreen_hdmi_write_sad_regs(struct drm_encoder *encoder,
167 struct cea_sad *sads, int sad_count);
evergreen_hdmi_write_sad_regs(struct drm_encoder * encoder,struct cea_sad * sads,int sad_count)168 void evergreen_hdmi_write_sad_regs(struct drm_encoder *encoder,
169 struct cea_sad *sads, int sad_count)
170 {
171 int i;
172 struct radeon_device *rdev = encoder->dev->dev_private;
173 static const u16 eld_reg_to_type[][2] = {
174 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
175 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
176 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
177 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
178 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
179 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
180 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
181 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
182 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
183 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
184 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
185 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
186 };
187
188 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
189 u32 value = 0;
190 u8 stereo_freqs = 0;
191 int max_channels = -1;
192 int j;
193
194 for (j = 0; j < sad_count; j++) {
195 struct cea_sad *sad = &sads[j];
196
197 if (sad->format == eld_reg_to_type[i][1]) {
198 if (sad->channels > max_channels) {
199 value = MAX_CHANNELS(sad->channels) |
200 DESCRIPTOR_BYTE_2(sad->byte2) |
201 SUPPORTED_FREQUENCIES(sad->freq);
202 max_channels = sad->channels;
203 }
204
205 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
206 stereo_freqs |= sad->freq;
207 else
208 break;
209 }
210 }
211
212 value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs);
213
214 WREG32_ENDPOINT(0, eld_reg_to_type[i][0], value);
215 }
216 }
217
218 /*
219 * build a AVI Info Frame
220 */
221 void evergreen_set_avi_packet(struct radeon_device *rdev, u32 offset,
222 unsigned char *buffer, size_t size);
evergreen_set_avi_packet(struct radeon_device * rdev,u32 offset,unsigned char * buffer,size_t size)223 void evergreen_set_avi_packet(struct radeon_device *rdev, u32 offset,
224 unsigned char *buffer, size_t size)
225 {
226 uint8_t *frame = buffer + 3;
227
228 WREG32(AFMT_AVI_INFO0 + offset,
229 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
230 WREG32(AFMT_AVI_INFO1 + offset,
231 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
232 WREG32(AFMT_AVI_INFO2 + offset,
233 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
234 WREG32(AFMT_AVI_INFO3 + offset,
235 frame[0xC] | (frame[0xD] << 8) | (buffer[1] << 24));
236
237 WREG32_P(HDMI_INFOFRAME_CONTROL1 + offset,
238 HDMI_AVI_INFO_LINE(2), /* anything other than 0 */
239 ~HDMI_AVI_INFO_LINE_MASK);
240 }
241
242 void dce4_hdmi_audio_set_dto(struct radeon_device *rdev,
243 struct radeon_crtc *crtc, unsigned int clock);
dce4_hdmi_audio_set_dto(struct radeon_device * rdev,struct radeon_crtc * crtc,unsigned int clock)244 void dce4_hdmi_audio_set_dto(struct radeon_device *rdev,
245 struct radeon_crtc *crtc, unsigned int clock)
246 {
247 unsigned int max_ratio = clock / 24000;
248 u32 dto_phase;
249 u32 wallclock_ratio;
250 u32 value;
251
252 if (max_ratio >= 8) {
253 dto_phase = 192 * 1000;
254 wallclock_ratio = 3;
255 } else if (max_ratio >= 4) {
256 dto_phase = 96 * 1000;
257 wallclock_ratio = 2;
258 } else if (max_ratio >= 2) {
259 dto_phase = 48 * 1000;
260 wallclock_ratio = 1;
261 } else {
262 dto_phase = 24 * 1000;
263 wallclock_ratio = 0;
264 }
265
266 value = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
267 value |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);
268 value &= ~DCCG_AUDIO_DTO1_USE_512FBR_DTO;
269 WREG32(DCCG_AUDIO_DTO0_CNTL, value);
270
271 /* Two dtos; generally use dto0 for HDMI */
272 value = 0;
273
274 if (crtc)
275 value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id);
276
277 WREG32(DCCG_AUDIO_DTO_SOURCE, value);
278
279 /* Express [24MHz / target pixel clock] as an exact rational
280 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
281 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
282 */
283 WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase);
284 WREG32(DCCG_AUDIO_DTO0_MODULE, clock);
285 }
286
287 void dce4_dp_audio_set_dto(struct radeon_device *rdev,
288 struct radeon_crtc *crtc, unsigned int clock);
dce4_dp_audio_set_dto(struct radeon_device * rdev,struct radeon_crtc * crtc,unsigned int clock)289 void dce4_dp_audio_set_dto(struct radeon_device *rdev,
290 struct radeon_crtc *crtc, unsigned int clock)
291 {
292 u32 value;
293
294 value = RREG32(DCCG_AUDIO_DTO1_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
295 value |= DCCG_AUDIO_DTO1_USE_512FBR_DTO;
296 WREG32(DCCG_AUDIO_DTO1_CNTL, value);
297
298 /* Two dtos; generally use dto1 for DP */
299 value = 0;
300 value |= DCCG_AUDIO_DTO_SEL;
301
302 if (crtc)
303 value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id);
304
305 WREG32(DCCG_AUDIO_DTO_SOURCE, value);
306
307 /* Express [24MHz / target pixel clock] as an exact rational
308 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
309 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
310 */
311 if (ASIC_IS_DCE41(rdev)) {
312 unsigned int div = (RREG32(DCE41_DENTIST_DISPCLK_CNTL) &
313 DENTIST_DPREFCLK_WDIVIDER_MASK) >>
314 DENTIST_DPREFCLK_WDIVIDER_SHIFT;
315 div = radeon_audio_decode_dfs_div(div);
316
317 if (div)
318 clock = 100 * clock / div;
319 }
320
321 WREG32(DCCG_AUDIO_DTO1_PHASE, 24000);
322 WREG32(DCCG_AUDIO_DTO1_MODULE, clock);
323 }
324
325 void dce4_set_vbi_packet(struct drm_encoder *encoder, u32 offset);
dce4_set_vbi_packet(struct drm_encoder * encoder,u32 offset)326 void dce4_set_vbi_packet(struct drm_encoder *encoder, u32 offset)
327 {
328 struct drm_device *dev = encoder->dev;
329 struct radeon_device *rdev = dev->dev_private;
330
331 WREG32(HDMI_VBI_PACKET_CONTROL + offset,
332 HDMI_NULL_SEND | /* send null packets when required */
333 HDMI_GC_SEND | /* send general control packets */
334 HDMI_GC_CONT); /* send general control packets every frame */
335 }
336
337 void dce4_hdmi_set_color_depth(struct drm_encoder *encoder, u32 offset, int bpc);
dce4_hdmi_set_color_depth(struct drm_encoder * encoder,u32 offset,int bpc)338 void dce4_hdmi_set_color_depth(struct drm_encoder *encoder, u32 offset, int bpc)
339 {
340 struct drm_device *dev = encoder->dev;
341 struct radeon_device *rdev = dev->dev_private;
342 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
343 uint32_t val;
344
345 val = RREG32(HDMI_CONTROL + offset);
346 val &= ~HDMI_DEEP_COLOR_ENABLE;
347 val &= ~HDMI_DEEP_COLOR_DEPTH_MASK;
348
349 switch (bpc) {
350 case 0:
351 case 6:
352 case 8:
353 case 16:
354 default:
355 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
356 connector->name, bpc);
357 break;
358 case 10:
359 val |= HDMI_DEEP_COLOR_ENABLE;
360 val |= HDMI_DEEP_COLOR_DEPTH(HDMI_30BIT_DEEP_COLOR);
361 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
362 connector->name);
363 break;
364 case 12:
365 val |= HDMI_DEEP_COLOR_ENABLE;
366 val |= HDMI_DEEP_COLOR_DEPTH(HDMI_36BIT_DEEP_COLOR);
367 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
368 connector->name);
369 break;
370 }
371
372 WREG32(HDMI_CONTROL + offset, val);
373 }
374
375 void dce4_set_audio_packet(struct drm_encoder *encoder, u32 offset);
dce4_set_audio_packet(struct drm_encoder * encoder,u32 offset)376 void dce4_set_audio_packet(struct drm_encoder *encoder, u32 offset)
377 {
378 struct drm_device *dev = encoder->dev;
379 struct radeon_device *rdev = dev->dev_private;
380
381 WREG32(AFMT_INFOFRAME_CONTROL0 + offset,
382 AFMT_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */
383
384 WREG32(AFMT_60958_0 + offset,
385 AFMT_60958_CS_CHANNEL_NUMBER_L(1));
386
387 WREG32(AFMT_60958_1 + offset,
388 AFMT_60958_CS_CHANNEL_NUMBER_R(2));
389
390 WREG32(AFMT_60958_2 + offset,
391 AFMT_60958_CS_CHANNEL_NUMBER_2(3) |
392 AFMT_60958_CS_CHANNEL_NUMBER_3(4) |
393 AFMT_60958_CS_CHANNEL_NUMBER_4(5) |
394 AFMT_60958_CS_CHANNEL_NUMBER_5(6) |
395 AFMT_60958_CS_CHANNEL_NUMBER_6(7) |
396 AFMT_60958_CS_CHANNEL_NUMBER_7(8));
397
398 WREG32(AFMT_AUDIO_PACKET_CONTROL2 + offset,
399 AFMT_AUDIO_CHANNEL_ENABLE(0xff));
400
401 WREG32(HDMI_AUDIO_PACKET_CONTROL + offset,
402 HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */
403 HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */
404
405 /* allow 60958 channel status and send audio packets fields to be updated */
406 WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + offset,
407 AFMT_RESET_FIFO_WHEN_AUDIO_DIS | AFMT_60958_CS_UPDATE);
408 }
409
410
411 void dce4_set_mute(struct drm_encoder *encoder, u32 offset, bool mute);
dce4_set_mute(struct drm_encoder * encoder,u32 offset,bool mute)412 void dce4_set_mute(struct drm_encoder *encoder, u32 offset, bool mute)
413 {
414 struct drm_device *dev = encoder->dev;
415 struct radeon_device *rdev = dev->dev_private;
416
417 if (mute)
418 WREG32_OR(HDMI_GC + offset, HDMI_GC_AVMUTE);
419 else
420 WREG32_AND(HDMI_GC + offset, ~HDMI_GC_AVMUTE);
421 }
422
423 void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable);
evergreen_hdmi_enable(struct drm_encoder * encoder,bool enable)424 void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable)
425 {
426 struct drm_device *dev = encoder->dev;
427 struct radeon_device *rdev = dev->dev_private;
428 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
429 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
430
431 if (!dig || !dig->afmt)
432 return;
433
434 if (enable) {
435 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
436
437 if (connector && drm_detect_monitor_audio(radeon_connector_edid(connector))) {
438 WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset,
439 HDMI_AVI_INFO_SEND | /* enable AVI info frames */
440 HDMI_AVI_INFO_CONT | /* required for audio info values to be updated */
441 HDMI_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */
442 HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */
443 WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset,
444 AFMT_AUDIO_SAMPLE_SEND);
445 } else {
446 WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset,
447 HDMI_AVI_INFO_SEND | /* enable AVI info frames */
448 HDMI_AVI_INFO_CONT); /* required for audio info values to be updated */
449 WREG32_AND(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset,
450 ~AFMT_AUDIO_SAMPLE_SEND);
451 }
452 } else {
453 WREG32_AND(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset,
454 ~AFMT_AUDIO_SAMPLE_SEND);
455 WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, 0);
456 }
457
458 dig->afmt->enabled = enable;
459
460 DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n",
461 enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id);
462 }
463
464 void evergreen_dp_enable(struct drm_encoder *encoder, bool enable);
evergreen_dp_enable(struct drm_encoder * encoder,bool enable)465 void evergreen_dp_enable(struct drm_encoder *encoder, bool enable)
466 {
467 struct drm_device *dev = encoder->dev;
468 struct radeon_device *rdev = dev->dev_private;
469 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
470 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
471 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
472
473 if (!dig || !dig->afmt)
474 return;
475
476 if (enable && connector &&
477 drm_detect_monitor_audio(radeon_connector_edid(connector))) {
478 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
479 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
480 struct radeon_connector_atom_dig *dig_connector;
481 uint32_t val;
482
483 WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset,
484 AFMT_AUDIO_SAMPLE_SEND);
485
486 WREG32(EVERGREEN_DP_SEC_TIMESTAMP + dig->afmt->offset,
487 EVERGREEN_DP_SEC_TIMESTAMP_MODE(1));
488
489 if (!ASIC_IS_DCE6(rdev) && radeon_connector->con_priv) {
490 dig_connector = radeon_connector->con_priv;
491 val = RREG32(EVERGREEN_DP_SEC_AUD_N + dig->afmt->offset);
492 val &= ~EVERGREEN_DP_SEC_N_BASE_MULTIPLE(0xf);
493
494 if (dig_connector->dp_clock == 162000)
495 val |= EVERGREEN_DP_SEC_N_BASE_MULTIPLE(3);
496 else
497 val |= EVERGREEN_DP_SEC_N_BASE_MULTIPLE(5);
498
499 WREG32(EVERGREEN_DP_SEC_AUD_N + dig->afmt->offset, val);
500 }
501
502 WREG32(EVERGREEN_DP_SEC_CNTL + dig->afmt->offset,
503 EVERGREEN_DP_SEC_ASP_ENABLE | /* Audio packet transmission */
504 EVERGREEN_DP_SEC_ATP_ENABLE | /* Audio timestamp packet transmission */
505 EVERGREEN_DP_SEC_AIP_ENABLE | /* Audio infoframe packet transmission */
506 EVERGREEN_DP_SEC_STREAM_ENABLE); /* Master enable for secondary stream engine */
507 } else {
508 WREG32(EVERGREEN_DP_SEC_CNTL + dig->afmt->offset, 0);
509 WREG32_AND(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset,
510 ~AFMT_AUDIO_SAMPLE_SEND);
511 }
512
513 dig->afmt->enabled = enable;
514 }
515