1 /*
2 * Copyright (c) 2013 Patrick Wildt <patrick@blueri.se>
3 *
4 * Permission to use, copy, modify, and distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <sys/param.h>
18 #include <sys/systm.h>
19 #include <sys/device.h>
20 #include <sys/rwlock.h>
21
22 #include <machine/bus.h>
23 #include <machine/fdt.h>
24
25 #include <dev/ofw/openfirm.h>
26 #include <dev/ofw/ofw_pinctrl.h>
27 #include <dev/ofw/fdt.h>
28
29 #include <dev/i2c/i2cvar.h>
30
31 #include <armv7/exynos/exclockvar.h>
32
33 /* registers */
34 #define I2C_CON 0x00 /* control register */
35 #define I2C_STAT 0x04 /* control/status register */
36 #define I2C_ADD 0x08 /* address register */
37 #define I2C_DS 0x0C /* transmit/receive data shift register */
38 #define I2C_LC 0x10 /* multi-master line control register */
39
40 /* bits and bytes */
41 #define I2C_CON_TXCLKVAL_MASK (0xf << 0) /* tx clock = i2cclk / (i2ccon[3:0] + 1) */
42 #define I2C_CON_INTPENDING (0x1 << 4) /* 0 = no interrupt pending/clear, 1 = pending */
43 #define I2C_CON_TXRX_INT (0x1 << 5) /* enable/disable */
44 #define I2C_CON_TXCLKSRC_16 (0x0 << 6) /* i2clk = fpclk/16 */
45 #define I2C_CON_TXCLKSRC_512 (0x1 << 6) /* i2clk = fpclk/512 */
46 #define I2C_CON_ACK (0x1 << 7)
47 #define I2C_STAT_LAST_RVCD_BIT (0x1 << 0) /* last received bit 0 => ack, 1 => no ack */
48 #define I2C_STAT_ADDR_ZERO_FLAG (0x1 << 1) /* 0 => start/stop cond. detected, 1 => received slave addr 0xb */
49 #define I2C_STAT_ADDR_SLAVE_ZERO_FLAG (0x1 << 2) /* 0 => start/stop cond. detected, 1 => received slave addr matches i2cadd */
50 #define I2C_STAT_ARBITRATION (0x1 << 3) /* 0 => successful, 1 => failed */
51 #define I2C_STAT_SERIAL_OUTPUT (0x1 << 4) /* 0 => disable tx/rx, 1 => enable tx/rx */
52 #define I2C_STAT_BUSY_SIGNAL (0x1 << 5) /* 0 => not busy / stop signal generation, 1 => busy / start signal generation */
53 #define I2C_STAT_MODE_SEL_SLAVE_RX (0x0 << 6) /* slave receive mode */
54 #define I2C_STAT_MODE_SEL_SLAVE_TX (0x1 << 6) /* slave transmit mode */
55 #define I2C_STAT_MODE_SEL_MASTER_RX (0x2 << 6) /* master receive mode */
56 #define I2C_STAT_MODE_SEL_MASTER_TX (0x3 << 6) /* master transmit */
57 #define I2C_ADD_SLAVE_ADDR(x) (((x) & 0x7f) << 1)
58 #define I2C_DS_DATA_SHIFT(x) (((x) & 0xff) << 0)
59
60 #define I2C_ACK 0
61 #define I2C_NACK 1
62 #define I2C_TIMEOUT 2
63
64 struct exiic_softc {
65 struct device sc_dev;
66 bus_space_tag_t sc_iot;
67 bus_space_handle_t sc_ioh;
68 bus_size_t sc_ios;
69 void *sc_ih;
70 int sc_node;
71
72 struct rwlock sc_buslock;
73 struct i2c_controller i2c_tag;
74
75 uint16_t frequency;
76 uint16_t intr_status;
77 };
78
79 int exiic_match(struct device *, void *, void *);
80 void exiic_attach(struct device *, struct device *, void *);
81 int exiic_detach(struct device *, int);
82 void exiic_scan(struct device *, struct i2cbus_attach_args *, void *);
83 void exiic_setspeed(struct exiic_softc *, int);
84 int exiic_wait_state(struct exiic_softc *, uint32_t, uint32_t, uint32_t);
85
86 void exiic_xfer_start(struct exiic_softc *);
87 int exiic_xfer_wait(struct exiic_softc *);
88 int exiic_i2c_acquire_bus(void *, int);
89 void exiic_i2c_release_bus(void *, int);
90 int exiic_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, size_t,
91 void *, size_t, int);
92
93 #define HREAD4(sc, reg) \
94 (bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
95 #define HWRITE4(sc, reg, val) \
96 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
97 #define HSET4(sc, reg, bits) \
98 HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
99 #define HCLR4(sc, reg, bits) \
100 HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
101
102
103 const struct cfattach exiic_ca = {
104 sizeof(struct exiic_softc), exiic_match, exiic_attach, exiic_detach
105 };
106
107 struct cfdriver exiic_cd = {
108 NULL, "exiic", DV_DULL
109 };
110
111 int
exiic_match(struct device * parent,void * match,void * aux)112 exiic_match(struct device *parent, void *match, void *aux)
113 {
114 struct fdt_attach_args *faa = aux;
115
116 return OF_is_compatible(faa->fa_node, "samsung,s3c2440-i2c");
117 }
118
119 void
exiic_attach(struct device * parent,struct device * self,void * aux)120 exiic_attach(struct device *parent, struct device *self, void *aux)
121 {
122 struct exiic_softc *sc = (struct exiic_softc *)self;
123 struct fdt_attach_args *faa = aux;
124 struct i2cbus_attach_args iba;
125
126 pinctrl_byname(faa->fa_node, "default");
127
128 sc->sc_iot = faa->fa_iot;
129 sc->sc_node = faa->fa_node;
130 if (bus_space_map(sc->sc_iot, faa->fa_reg[0].addr,
131 faa->fa_reg[0].size, 0, &sc->sc_ioh))
132 panic("%s: bus_space_map failed!", __func__);
133
134 printf("\n");
135
136 rw_init(&sc->sc_buslock, sc->sc_dev.dv_xname);
137
138 sc->i2c_tag.ic_cookie = sc;
139 sc->i2c_tag.ic_acquire_bus = exiic_i2c_acquire_bus;
140 sc->i2c_tag.ic_release_bus = exiic_i2c_release_bus;
141 sc->i2c_tag.ic_exec = exiic_i2c_exec;
142
143 bzero(&iba, sizeof iba);
144 iba.iba_name = "iic";
145 iba.iba_tag = &sc->i2c_tag;
146 iba.iba_bus_scan = exiic_scan;
147 iba.iba_bus_scan_arg = &sc->sc_node;
148 config_found(&sc->sc_dev, &iba, NULL);
149 }
150
151 void
exiic_scan(struct device * self,struct i2cbus_attach_args * iba,void * aux)152 exiic_scan(struct device *self, struct i2cbus_attach_args *iba, void *aux)
153 {
154 int iba_node = *(int *)aux;
155 extern int iic_print(void *, const char *);
156 struct i2c_attach_args ia;
157 char name[32];
158 uint32_t reg[1];
159 int node;
160
161 for (node = OF_child(iba_node); node; node = OF_peer(node)) {
162 memset(name, 0, sizeof(name));
163 memset(reg, 0, sizeof(reg));
164
165 if (OF_getprop(node, "compatible", name, sizeof(name)) == -1)
166 continue;
167 if (name[0] == '\0')
168 continue;
169
170 if (OF_getprop(node, "reg", ®, sizeof(reg)) != sizeof(reg))
171 continue;
172
173 memset(&ia, 0, sizeof(ia));
174 ia.ia_tag = iba->iba_tag;
175 ia.ia_addr = bemtoh32(®[0]);
176 ia.ia_name = name;
177 ia.ia_cookie = &node;
178
179 config_found(self, &ia, iic_print);
180 }
181 }
182
183 void
exiic_setspeed(struct exiic_softc * sc,int speed)184 exiic_setspeed(struct exiic_softc *sc, int speed)
185 {
186 if (!sc->frequency) {
187 uint32_t freq, div = 0, pres = 16;
188 freq = exclock_get_i2cclk();
189
190 /* calculate prescaler and divisor values */
191 if ((freq / pres / (16 + 1)) > speed)
192 /* set prescaler to 512 */
193 pres = 512;
194
195 while ((freq / pres / (div + 1)) > speed)
196 div++;
197
198 /* set prescaler, divisor according to freq, also set ACKGEN, IRQ */
199 sc->frequency = (div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0);
200 }
201
202 HWRITE4(sc, I2C_CON, sc->frequency);
203 }
204
205 int
exiic_wait_state(struct exiic_softc * sc,uint32_t reg,uint32_t mask,uint32_t value)206 exiic_wait_state(struct exiic_softc *sc, uint32_t reg, uint32_t mask, uint32_t value)
207 {
208 uint32_t state;
209 int timeout;
210 state = HREAD4(sc, reg);
211 for (timeout = 1000; timeout > 0; timeout--) {
212 if (((state = HREAD4(sc, reg)) & mask) == value)
213 return 0;
214 delay(1000);
215 }
216 return ETIMEDOUT;
217 }
218
219 int
exiic_i2c_acquire_bus(void * cookie,int flags)220 exiic_i2c_acquire_bus(void *cookie, int flags)
221 {
222 struct exiic_softc *sc = cookie;
223 int ret = rw_enter(&sc->sc_buslock, RW_WRITE);
224
225 if (!ret) {
226 /* set speed to 100 Kbps */
227 exiic_setspeed(sc, 100);
228
229 /* STOP */
230 HWRITE4(sc, I2C_STAT, 0);
231 HWRITE4(sc, I2C_ADD, 0);
232 HWRITE4(sc, I2C_STAT, I2C_STAT_MODE_SEL_MASTER_TX
233 | I2C_STAT_SERIAL_OUTPUT);
234 }
235
236 return ret;
237 }
238
239 void
exiic_i2c_release_bus(void * cookie,int flags)240 exiic_i2c_release_bus(void *cookie, int flags)
241 {
242 struct exiic_softc *sc = cookie;
243
244 (void) rw_exit(&sc->sc_buslock);
245 }
246
247 int
exiic_i2c_exec(void * cookie,i2c_op_t op,i2c_addr_t _addr,const void * cmdbuf,size_t cmdlen,void * databuf,size_t datalen,int flags)248 exiic_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t _addr,
249 const void *cmdbuf, size_t cmdlen, void *databuf, size_t datalen, int flags)
250 {
251 struct exiic_softc *sc = cookie;
252 uint32_t ret = 0;
253 u_int8_t addr = 0;
254 int i = 0;
255
256 addr = (_addr & 0x7f) << 1;
257
258 /* clock gating */
259 //exccm_enable_i2c(sc->unit);
260
261 if (exiic_wait_state(sc, I2C_STAT, I2C_STAT_BUSY_SIGNAL, 0)) {
262 printf("%s: busy\n", __func__);
263 return (EIO);
264 }
265
266 /* acknowledge generation */
267 HSET4(sc, I2C_CON, I2C_CON_ACK);
268
269 /* Send the slave-address */
270 HWRITE4(sc, I2C_DS, addr);
271 if (!I2C_OP_READ_P(op) || (cmdbuf && cmdlen))
272 HWRITE4(sc, I2C_STAT, I2C_STAT_MODE_SEL_MASTER_TX
273 | I2C_STAT_SERIAL_OUTPUT
274 | I2C_STAT_BUSY_SIGNAL);
275 else
276 HWRITE4(sc, I2C_STAT, I2C_STAT_MODE_SEL_MASTER_RX
277 | I2C_STAT_SERIAL_OUTPUT
278 | I2C_STAT_BUSY_SIGNAL);
279
280 ret = exiic_xfer_wait(sc);
281 if (ret != I2C_ACK)
282 goto fail;
283
284 /* transmit commands */
285 if (cmdbuf && cmdlen) {
286 for (i = 0; i < cmdlen; i++) {
287 HWRITE4(sc, I2C_DS, ((uint8_t *)cmdbuf)[i]);
288 exiic_xfer_start(sc);
289 ret = exiic_xfer_wait(sc);
290 if (ret != I2C_ACK)
291 goto fail;
292 }
293 }
294
295 if (I2C_OP_READ_P(op)) {
296 if (cmdbuf && cmdlen) {
297 /* write slave chip address again for actual read */
298 HWRITE4(sc, I2C_DS, addr);
299
300 /* restart */
301 HWRITE4(sc, I2C_STAT, I2C_STAT_MODE_SEL_MASTER_RX
302 | I2C_STAT_SERIAL_OUTPUT
303 | I2C_STAT_BUSY_SIGNAL);
304 exiic_xfer_start(sc);
305 ret = exiic_xfer_wait(sc);
306 if (ret != I2C_ACK)
307 goto fail;
308 }
309
310 for (i = 0; i < datalen && ret == I2C_ACK; i++) {
311 /* disable ACK for final read */
312 if (i == datalen - 1)
313 HCLR4(sc, I2C_CON, I2C_CON_ACK);
314 exiic_xfer_start(sc);
315 ret = exiic_xfer_wait(sc);
316 ((uint8_t *)databuf)[i] = HREAD4(sc, I2C_DS);
317 }
318 if (ret == I2C_NACK)
319 ret = I2C_ACK; /* Normal terminated read. */
320 } else {
321 for (i = 0; i < datalen && ret == I2C_ACK; i++) {
322 HWRITE4(sc, I2C_DS, ((uint8_t *)databuf)[i]);
323 exiic_xfer_start(sc);
324 ret = exiic_xfer_wait(sc);
325 }
326 }
327
328 fail:
329 /* send STOP */
330 if (op & I2C_OP_READ_WITH_STOP) {
331 HWRITE4(sc, I2C_STAT, I2C_STAT_MODE_SEL_MASTER_RX
332 | I2C_STAT_SERIAL_OUTPUT);
333 exiic_xfer_start(sc);
334 }
335
336 return ret;
337 }
338
339 void
exiic_xfer_start(struct exiic_softc * sc)340 exiic_xfer_start(struct exiic_softc *sc)
341 {
342 HCLR4(sc, I2C_CON, I2C_CON_INTPENDING);
343 }
344
345 int
exiic_xfer_wait(struct exiic_softc * sc)346 exiic_xfer_wait(struct exiic_softc *sc)
347 {
348 if (!exiic_wait_state(sc, I2C_CON, I2C_CON_INTPENDING,
349 I2C_CON_INTPENDING))
350 return (HREAD4(sc, I2C_STAT) & I2C_STAT_LAST_RVCD_BIT) ?
351 I2C_NACK : I2C_ACK;
352 else
353 return I2C_TIMEOUT;
354 }
355
356 int
exiic_detach(struct device * self,int flags)357 exiic_detach(struct device *self, int flags)
358 {
359 struct exiic_softc *sc = (struct exiic_softc *)self;
360
361 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios);
362 return 0;
363 }
364