1 /************************************************************************ 2 ************************************************************************ 3 FAUST compiler 4 Copyright (C) 2003-2018 GRAME, Centre National de Creation Musicale 5 --------------------------------------------------------------------- 6 This program is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 2 of the License, or 9 (at your option) any later version. 10 11 This program is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with this program; if not, write to the Free Software 18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19 ************************************************************************ 20 ************************************************************************/ 21 22 #pragma once 23 24 #include <cstdlib> 25 #include "property.hh" 26 #include "signalVisitor.hh" 27 #include "sigtyperules.hh" 28 #include "tree.hh" 29 #include "treeTraversal.hh" 30 #include "xtended.hh" 31 #include "old_occurences.hh" 32 33 //-------------------------Signal2VHDLVisitor------------------------------- 34 // A a signal visitor used to compile signals to vhdl code 35 //---------------------------------------------------------------------- 36 using namespace std; 37 38 class Signal2VHDLVisitor : public TreeTraversal { 39 40 private: 41 old_OccMarkup* fOccMarkup; 42 bool fVisitGen; 43 set<Tree> fVisited; // Avoid visiting a tree twice 44 map<string, bool> fEntity; 45 /** Fields used to accumulate strings for different parts of the .vhd file */ 46 string fInput; 47 string fDeclEntity; // Entity block specification part 48 string fFaustEntity; // Faust block specification 49 string fDeclSig; // Signal declaration 50 string fDeclCompnt; // Declaration of components 51 string fFaustProcess; // Implement the Faust process 52 string fMapCompnt; // Instantiating blocks 53 54 string addr_to_str(Tree t); 55 string val_to_str(Tree t); 56 57 void entity_header(string& str); 58 void generic_decl(string& str); 59 void port_decl(int input, string& str); 60 61 /** Functions generating different Faust blocks, each block is treated as an entity with declaration of inputs and outputs: 62 * - Each design must have at least one entity and one corresponding architecture 63 * that specifies the external specification of the design. 64 * - Each entity has a name assigned to it and a port list 65 * - Each port list has a direction (in/out/inout) and a type 66 */ 67 void entity_bin_op(const string& name, const char* op, string& str); // arithmetic and modulo operation 68 void entity_bin_op_concat(const string& name, const char* op, string& str); // arithmetic and modulo operation 69 void entity_cmp_op(const string& name, const char* op, string& str); // compare operation 70 void entity_delay(string& str); // delay 71 void entity_delay_var_reg(string& str); // variable delay (Using Registers) 72 void entity_delay_var_ram(string& str); // variable delay (Using Blocks RAM) 73 void entity_bypass(const string& name, string& str); // bypass module 74 void entity_select2(const string& name, string& str); // select module 75 void entity_faust(); // main module 76 77 /** Functions declaring the design entity interface for blocks that will be used 78 * later to form a hierarchical design 79 */ 80 void component_standard(const string& name, int input, string& str); // arith, mod, bypass, compare, select 81 void component_delay(string& str); // delay 82 void component_delay_var(string& str); // variable delay 83 void component_sincos(string& str); // cosinus & sinus 84 85 /* Generate the process of the Faust module, it determine the behavioral modeling of the Faust IP */ 86 void faust_process(); 87 88 /** Functions generating instance of components referenced in the declarative area 89 * - The instances are constructed after the keyword “begin” and using 90 * the port map statements to connect the ports 91 */ 92 void inst_bin_op(const string& name, Tree sig, Tree x, Tree y, string& str); // arith, mod, compare 93 void inst_delay(Tree sig, Tree x, Tree y, string& str); // delay 94 void inst_delay_var(Tree sig, Tree x, Tree y, string& str, int mxd); // variable delay 95 void inst_sincos(const string& name, Tree sig, Tree x, string& str); // cosinus & sinus 96 void inst_bypass(const string& name, Tree sig, Tree x, string& str); // bypass 97 void inst_select2(const string& name, Tree sig, Tree sel, Tree x, Tree y, string& str); // select 98 99 void decl_sig(Tree x, int msb, int lsb); // Declare the internal signals of the IP block with a type (and an initial value) 100 void input_affectation(Tree sig); 101 102 void bin_op(const string& name, const char* op, Tree sig, Tree x, Tree y); 103 void select_op(const string& name, Tree sig, Tree sel, Tree x, Tree y); 104 void cmp_op(const string& name, const char* op, Tree sig, Tree x, Tree y); 105 void sincos_op(const string& name, Tree sig, Tree x); 106 void bypass(const string& name, Tree sig, Tree x); 107 108 public: Signal2VHDLVisitor(old_OccMarkup * occ_markup)109 Signal2VHDLVisitor(old_OccMarkup* occ_markup) : TreeTraversal(), fOccMarkup(occ_markup), fVisitGen(false){}; 110 111 void self(Tree t); 112 void sigToVHDL(Tree sig, ofstream& fout); 113 114 protected: 115 void visit(Tree sig) override; 116 }; 117