1 /* 2 * Copyright © 2017 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the 13 * next paragraph) shall be included in all copies or substantial portions 14 * of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR 20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 22 * SOFTWAR OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Chen, Peng <chen.c.peng@intel.com> 26 * 27 */ 28 29 #ifndef GEN9_HEVC_ENCODER_KERNELS_H 30 #define GEN9_HEVC_ENCODER_KERNELS_H 31 32 // Scaling kernel parameters 33 typedef enum _gen9_hevc_binding_table_offset_scaling { 34 GEN9_HEVC_SCALING_FRAME_SRC_Y_INDEX = 0, 35 GEN9_HEVC_SCALING_FRAME_DST_Y_INDEX = 1, 36 GEN9_HEVC_SCALING_FRAME_MBVPROCSTATS_DST_INDEX = 4, 37 GEN9_HEVC_SCALING_NUM_SURFACES = 6 38 } gen9_hevc_binding_table_offset_scaling; 39 40 typedef struct _gen9_hevc_scaling4x_curbe_data { 41 struct { 42 unsigned int input_picture_width : 16; 43 unsigned int input_picture_height : 16; 44 } dw0; 45 46 struct { 47 unsigned int input_y_bti; 48 } dw1; 49 50 struct { 51 unsigned int output_y_bti; 52 } dw2; 53 54 struct { 55 unsigned int reserved; 56 } dw3; 57 58 struct { 59 unsigned int reserved; 60 } dw4; 61 62 struct { 63 unsigned int flatness_threshold; 64 } dw5; 65 66 struct { 67 unsigned int enable_mb_flatness_check; 68 } dw6; 69 70 struct { 71 unsigned int enable_mb_variance_output; 72 } dw7; 73 74 struct { 75 unsigned int enable_mb_pixel_average_output; 76 } dw8; 77 78 struct { 79 unsigned int reserved; 80 } dw9; 81 82 struct { 83 unsigned int mbv_proc_stat_bti; 84 } dw10; 85 86 struct { 87 unsigned int reserved; 88 } dw11; 89 } gen9_hevc_scaling4x_curbe_data; 90 91 typedef struct _gen9_hevc_scaling2x_curbe_data { 92 struct { 93 unsigned int input_picture_width : 16; 94 unsigned int input_picture_height : 16; 95 } dw0; 96 97 /* dw1-dw7 */ 98 unsigned int reserved1[7]; 99 100 struct { 101 unsigned int input_y_bti; 102 } dw8; 103 104 struct { 105 unsigned int output_y_bti; 106 } dw9; 107 } gen9_hevc_scaling2x_curbe_data; 108 109 // ME kernel parameters 110 typedef enum _gen9_hevc_binding_table_offset_me { 111 GEN9_HEVC_ME_MV_DATA_SURFACE_INDEX = 0, 112 GEN9_HEVC_ME_16X_MV_DATA_SURFACE_INDEX = 1, 113 GEN9_HEVC_ME_32X_MV_DATA_SURFACE_INDEX = 1, 114 GEN9_HEVC_ME_DISTORTION_SURFACE_INDEX = 2, 115 GEN9_HEVC_ME_BRC_DISTORTION_INDEX = 3, 116 GEN9_HEVC_ME_RESERVED0_INDEX = 4, 117 GEN9_HEVC_ME_CURR_FOR_FWD_REF_INDEX = 5, 118 GEN9_HEVC_ME_FWD_REF_IDX0_INDEX = 6, 119 GEN9_HEVC_ME_RESERVED1_INDEX = 7, 120 GEN9_HEVC_ME_FWD_REF_IDX1_INDEX = 8, 121 GEN9_HEVC_ME_RESERVED2_INDEX = 9, 122 GEN9_HEVC_ME_FWD_REF_IDX2_INDEX = 10, 123 GEN9_HEVC_ME_RESERVED3_INDEX = 11, 124 GEN9_HEVC_ME_FWD_REF_IDX3_INDEX = 12, 125 GEN9_HEVC_ME_RESERVED4_INDEX = 13, 126 GEN9_HEVC_ME_FWD_REF_IDX4_INDEX = 14, 127 GEN9_HEVC_ME_RESERVED5_INDEX = 15, 128 GEN9_HEVC_ME_FWD_REF_IDX5_INDEX = 16, 129 GEN9_HEVC_ME_RESERVED6_INDEX = 17, 130 GEN9_HEVC_ME_FWD_REF_IDX6_INDEX = 18, 131 GEN9_HEVC_ME_RESERVED7_INDEX = 19, 132 GEN9_HEVC_ME_FWD_REF_IDX7_INDEX = 20, 133 GEN9_HEVC_ME_RESERVED8_INDEX = 21, 134 GEN9_HEVC_ME_CURR_FOR_BWD_REF_INDEX = 22, 135 GEN9_HEVC_ME_BWD_REF_IDX0_INDEX = 23, 136 GEN9_HEVC_ME_RESERVED9_INDEX = 24, 137 GEN9_HEVC_ME_BWD_REF_IDX1_INDEX = 25, 138 GEN9_HEVC_ME_VDENC_STREAMIN_INDEX = 26, 139 GEN9_HEVC_ME_NUM_SURFACES_INDEX = 27 140 } gen9_hevc_binding_table_offset_me; 141 142 struct gen9_search_path_delta { 143 char gen9_search_path_delta_x: 4; 144 char gen9_search_path_delta_y: 4; 145 }; 146 147 typedef struct _gen9_hevc_me_curbe_data { 148 struct { 149 unsigned int skip_mode_enable: 1; 150 unsigned int adaptive_enable: 1; 151 unsigned int bi_mix_dis: 1; 152 unsigned int reserved0: 2; 153 unsigned int early_ime_success_enable: 1; 154 unsigned int reserved1: 1; 155 unsigned int t8x8_flag_for_inter_enable: 1; 156 unsigned int reserved2: 16; 157 unsigned int early_ime_stop: 8; 158 } dw0; 159 160 struct { 161 unsigned int max_num_mvs: 6; 162 unsigned int reserved0: 10; 163 unsigned int bi_weight: 6; 164 unsigned int reserved1: 6; 165 unsigned int uni_mix_disable: 1; 166 unsigned int reserved2: 3; 167 } dw1; 168 169 struct { 170 unsigned int max_len_sp: 8; 171 unsigned int max_num_su: 8; 172 unsigned int reserved0: 16; 173 } dw2; 174 175 struct { 176 unsigned int src_size: 2; 177 unsigned int reserved0: 2; 178 unsigned int mb_type_remap: 2; 179 unsigned int src_access: 1; 180 unsigned int ref_access: 1; 181 unsigned int search_ctrl: 3; 182 unsigned int dual_search_path_option: 1; 183 unsigned int sub_pel_mode: 2; 184 unsigned int skip_type: 1; 185 unsigned int disable_field_cache_allocation: 1; 186 unsigned int inter_chroma_mode: 1; 187 unsigned int ft_enable: 1; 188 unsigned int bme_disable_fbr: 1; 189 unsigned int block_based_skip_enable: 1; 190 unsigned int inter_sad: 2; 191 unsigned int intra_sad: 2; 192 unsigned int sub_mb_part_mask: 7; 193 unsigned int reserved1: 1; 194 } dw3; 195 196 struct { 197 unsigned int reserved0: 8; 198 unsigned int picture_height_minus1: 8; 199 unsigned int picture_width: 8; 200 unsigned int reserved1: 8; 201 } dw4; 202 203 struct { 204 unsigned int reserved0: 8; 205 unsigned int qp_prime_y: 8; 206 unsigned int ref_width: 8; 207 unsigned int ref_height: 8; 208 } dw5; 209 210 struct { 211 unsigned int reserved0: 3; 212 unsigned int write_distortions: 1; 213 unsigned int use_mv_from_prev_step: 1; 214 unsigned int reserved1: 3; 215 unsigned int super_combine_dist: 8; 216 unsigned int max_vmvr: 16; 217 } dw6; 218 219 struct { 220 unsigned int reserved0: 16; 221 unsigned int mv_cost_scale_factor: 2; 222 unsigned int bilinear_enable: 1; 223 unsigned int src_field_polarity: 1; 224 unsigned int weightedsad_harr: 1; 225 unsigned int ac_only_haar: 1; 226 unsigned int ref_id_cost_mode: 1; 227 unsigned int reserved1: 1; 228 unsigned int skip_center_mask: 8; 229 } dw7; 230 231 struct { 232 unsigned int mode_0_cost: 8; 233 unsigned int mode_1_cost: 8; 234 unsigned int mode_2_cost: 8; 235 unsigned int mode_3_cost: 8; 236 } dw8; 237 238 struct { 239 unsigned int mode_4_cost: 8; 240 unsigned int mode_5_cost: 8; 241 unsigned int mode_6_cost: 8; 242 unsigned int mode_7_cost: 8; 243 } dw9; 244 245 struct { 246 unsigned int mode_8_cost: 8; 247 unsigned int mode_9_cost: 8; 248 unsigned int ref_id_cost: 8; 249 unsigned int chroma_intra_mode_cost: 8; 250 } dw10; 251 252 struct { 253 unsigned int mv_0_cost: 8; 254 unsigned int mv_1_cost: 8; 255 unsigned int mv_2_cost: 8; 256 unsigned int mv_3_cost: 8; 257 } dw11; 258 259 struct { 260 unsigned int mv_4_cost: 8; 261 unsigned int mv_5_cost: 8; 262 unsigned int mv_6_cost: 8; 263 unsigned int mv_7_cost: 8; 264 } dw12; 265 266 struct { 267 unsigned int num_ref_idx_l0_minus1: 8; 268 unsigned int num_ref_idx_l1_minus1: 8; 269 unsigned int ref_streamin_cost: 8; 270 unsigned int roi_enable: 3; 271 unsigned int reserved0: 5; 272 } dw13; 273 274 struct { 275 unsigned int l0_ref_pic_polarity_bits: 8; 276 unsigned int l1_ref_pic_polarity_bits: 2; 277 unsigned int reserved: 22; 278 } dw14; 279 280 struct { 281 unsigned int prev_mv_read_pos_factor : 8; 282 unsigned int mv_shift_factor : 8; 283 unsigned int reserved: 16; 284 } dw15; 285 286 struct { 287 struct gen9_search_path_delta sp_delta_0; 288 struct gen9_search_path_delta sp_delta_1; 289 struct gen9_search_path_delta sp_delta_2; 290 struct gen9_search_path_delta sp_delta_3; 291 } dw16; 292 293 struct { 294 struct gen9_search_path_delta sp_delta_4; 295 struct gen9_search_path_delta sp_delta_5; 296 struct gen9_search_path_delta sp_delta_6; 297 struct gen9_search_path_delta sp_delta_7; 298 } dw17; 299 300 struct { 301 struct gen9_search_path_delta sp_delta_8; 302 struct gen9_search_path_delta sp_delta_9; 303 struct gen9_search_path_delta sp_delta_10; 304 struct gen9_search_path_delta sp_delta_11; 305 } dw18; 306 307 struct { 308 struct gen9_search_path_delta sp_delta_12; 309 struct gen9_search_path_delta sp_delta_13; 310 struct gen9_search_path_delta sp_delta_14; 311 struct gen9_search_path_delta sp_delta_15; 312 } dw19; 313 314 struct { 315 struct gen9_search_path_delta sp_delta_16; 316 struct gen9_search_path_delta sp_delta_17; 317 struct gen9_search_path_delta sp_delta_18; 318 struct gen9_search_path_delta sp_delta_19; 319 } dw20; 320 321 struct { 322 struct gen9_search_path_delta sp_delta_20; 323 struct gen9_search_path_delta sp_delta_21; 324 struct gen9_search_path_delta sp_delta_22; 325 struct gen9_search_path_delta sp_delta_23; 326 } dw21; 327 328 struct { 329 struct gen9_search_path_delta sp_delta_24; 330 struct gen9_search_path_delta sp_delta_25; 331 struct gen9_search_path_delta sp_delta_26; 332 struct gen9_search_path_delta sp_delta_27; 333 } dw22; 334 335 struct { 336 struct gen9_search_path_delta sp_delta_28; 337 struct gen9_search_path_delta sp_delta_29; 338 struct gen9_search_path_delta sp_delta_30; 339 struct gen9_search_path_delta sp_delta_31; 340 } dw23; 341 342 struct { 343 struct gen9_search_path_delta sp_delta_32; 344 struct gen9_search_path_delta sp_delta_33; 345 struct gen9_search_path_delta sp_delta_34; 346 struct gen9_search_path_delta sp_delta_35; 347 } dw24; 348 349 struct { 350 struct gen9_search_path_delta sp_delta_36; 351 struct gen9_search_path_delta sp_delta_37; 352 struct gen9_search_path_delta sp_delta_38; 353 struct gen9_search_path_delta sp_delta_39; 354 } dw25; 355 356 struct { 357 struct gen9_search_path_delta sp_delta_40; 358 struct gen9_search_path_delta sp_delta_41; 359 struct gen9_search_path_delta sp_delta_42; 360 struct gen9_search_path_delta sp_delta_43; 361 } dw26; 362 363 struct { 364 struct gen9_search_path_delta sp_delta_44; 365 struct gen9_search_path_delta sp_delta_45; 366 struct gen9_search_path_delta sp_delta_46; 367 struct gen9_search_path_delta sp_delta_47; 368 } dw27; 369 370 struct { 371 struct gen9_search_path_delta sp_delta_48; 372 struct gen9_search_path_delta sp_delta_49; 373 struct gen9_search_path_delta sp_delta_50; 374 struct gen9_search_path_delta sp_delta_51; 375 } dw28; 376 377 struct { 378 struct gen9_search_path_delta sp_delta_52; 379 struct gen9_search_path_delta sp_delta_53; 380 struct gen9_search_path_delta sp_delta_54; 381 struct gen9_search_path_delta sp_delta_55; 382 } dw29; 383 384 struct { 385 unsigned int actual_mb_width: 16; 386 unsigned int actual_mb_height: 16; 387 } dw30; 388 389 struct { 390 unsigned int reserved0; 391 } dw31; 392 393 struct { 394 unsigned int _4x_memv_output_data_surf_index; 395 } dw32; 396 397 struct { 398 unsigned int _16x_32x_memv_input_data_surf_index; 399 } dw33; 400 401 struct { 402 unsigned int _4x_me_output_dist_surf_index; 403 } dw34; 404 405 struct { 406 unsigned int _4x_me_output_brc_dist_surf_index; 407 } dw35; 408 409 struct { 410 unsigned int vme_fwd_inter_pred_surf_index; 411 } dw36; 412 413 struct { 414 unsigned int vme_bdw_inter_pred_surf_index; 415 } dw37; 416 417 struct { 418 unsigned int vdenc_stream_in_surf_index; 419 } dw38; 420 } gen9_hevc_me_curbe_data; 421 422 // MBENC kernel paramerters 423 424 typedef struct _gen9_hevc_mbenc_control_region { 425 unsigned short reserved0[2]; 426 unsigned short start_y_current_slice; 427 unsigned short start_y_next_slice; 428 unsigned short x_offset; 429 unsigned short reserved1[2]; 430 unsigned short y_offset; 431 unsigned int reserverd2[4]; 432 unsigned int alignment[8]; 433 } gen9_hevc_mbenc_control_region; 434 435 #define GEN9_HEVC_ENC_REGION_START_Y_OFFSET (32) 436 #define GEN9_HEVC_ENC_CONCURRENT_SURFACE_HEIGHT (32) 437 438 typedef struct _gen9_hevc_mbenc_downscaling2x_curbe_data { 439 struct { 440 unsigned int pic_width: 16; 441 unsigned int pic_height: 16; 442 } dw0; 443 444 struct { 445 unsigned int reserved; 446 } dw1; 447 448 struct { 449 unsigned int reserved; 450 } dw2; 451 452 struct { 453 unsigned int reserved; 454 } dw3; 455 456 struct { 457 unsigned int reserved; 458 } dw4; 459 460 struct { 461 unsigned int reserved; 462 } dw5; 463 464 struct { 465 unsigned int reserved; 466 } dw6; 467 468 struct { 469 unsigned int reserved; 470 } dw7; 471 472 struct { 473 unsigned int bti_src_y; 474 } dw8; 475 476 struct { 477 unsigned int bit_dst_y; 478 } dw9; 479 } gen9_hevc_mbenc_downscaling2x_curbe_data; 480 481 typedef struct _gen9_hevc_mbenc_32x32_pu_mode_curbe_data { 482 struct { 483 unsigned int frame_width: 16; 484 unsigned int frame_height: 16; 485 } dw0; 486 487 struct { 488 unsigned int slice_type: 2; 489 unsigned int pu_type: 2; 490 unsigned int reserved0: 1; 491 unsigned int lcu_type: 1; 492 unsigned int reserverd1: 18; 493 unsigned int brc_enable: 1; 494 unsigned int lcu_brc_enable: 1; 495 unsigned int roi_enable: 1; 496 unsigned int fast_surveillance_flag: 1; 497 unsigned int reserverd2: 3; 498 unsigned int enable_debug_dump: 1; 499 } dw1; 500 501 struct { 502 unsigned int lambda; 503 } dw2; 504 505 struct { 506 unsigned int mode_cost_32x32; 507 } dw3; 508 509 struct { 510 unsigned int early_exit; 511 } dw4; 512 513 struct { 514 unsigned int reserved; 515 } dw5; 516 517 struct { 518 unsigned int reserved; 519 } dw6; 520 521 struct { 522 unsigned int reserved; 523 } dw7; 524 525 struct { 526 unsigned int bti_32x32_pu_output; 527 } dw8; 528 529 struct { 530 unsigned int bti_src_y; 531 } dw9; 532 533 struct { 534 unsigned int bti_src_y2x; 535 } dw10; 536 537 struct { 538 unsigned int bti_slice_map; 539 } dw11; 540 541 struct { 542 unsigned int bti_src_y2x_vme; 543 } dw12; 544 545 struct { 546 unsigned int bti_brc_input; 547 } dw13; 548 549 struct { 550 unsigned int bti_lcu_qp_surface; 551 } dw14; 552 553 struct { 554 unsigned int bti_brc_data; 555 } dw15; 556 557 struct { 558 unsigned int bti_kernel_debug; 559 } dw16; 560 } gen9_hevc_mbenc_32x32_pu_mode_curbe_data; 561 562 typedef struct _gen9_hevc_mbenc_16x16_sad_curbe_data { 563 struct { 564 unsigned int frame_width: 16; 565 unsigned int frame_height: 16; 566 } dw0; 567 568 struct { 569 unsigned int log2_max_cu_size: 8; 570 unsigned int log2_min_cu_size: 8; 571 unsigned int log2_min_tu_size: 8; 572 unsigned int enable_intra_early_exit: 1; 573 unsigned int reserved: 7; 574 } dw1; 575 576 struct { 577 unsigned int slice_type: 2; 578 unsigned int sim_flag_for_inter: 1; 579 unsigned int fast_surveillance_flag: 1; 580 unsigned int reserved: 28; 581 } dw2; 582 583 struct { 584 unsigned int reserved; 585 } dw3; 586 587 struct { 588 unsigned int reserved; 589 } dw4; 590 591 struct { 592 unsigned int reserved; 593 } dw5; 594 595 struct { 596 unsigned int reserved; 597 } dw6; 598 599 struct { 600 unsigned int reserved; 601 } dw7; 602 603 struct { 604 unsigned int bti_src_y; 605 } dw8; 606 607 struct { 608 unsigned int bti_sad_16x16_pu_output; 609 } dw9; 610 611 struct { 612 unsigned int bti_32x32_pu_mode_decision; 613 } dw10; 614 615 struct { 616 unsigned int bti_slice_map; 617 } dw11; 618 619 struct { 620 unsigned int bti_simplest_intra; 621 } dw12; 622 623 struct { 624 unsigned int bti_debug; 625 } dw13; 626 } gen9_hevc_mbenc_16x16_sad_curbe_data; 627 628 typedef struct _gen9_hevc_enc_16x16_pu_curbe_data { 629 struct { 630 unsigned int frame_width: 16; 631 unsigned int frame_height: 16; 632 } dw0; 633 634 struct { 635 unsigned int log2_max_cu_size: 8; 636 unsigned int log2_min_cu_size: 8; 637 unsigned int log2_min_tu_size: 8; 638 unsigned int slice_qp: 8; 639 } dw1; 640 641 struct { 642 unsigned int fixed_point_lambda_pred_mode; 643 } dw2; 644 645 struct { 646 unsigned int lambda_scaling_factor: 8; 647 unsigned int slice_type: 2; 648 unsigned int reserved0: 6; 649 unsigned int widi_intra_refresh_en: 2; 650 unsigned int enable_rolling_intra: 1; 651 unsigned int half_update_mixed_lcu: 1; 652 unsigned int reserved1: 4; 653 unsigned int enable_intra_early_exit: 1; 654 unsigned int brc_enable: 1; 655 unsigned int lcu_brc_enable: 1; 656 unsigned int roi_enable: 1; 657 unsigned int fast_surveillance_flag: 1; 658 unsigned int reserved2: 3; 659 } dw3; 660 661 struct { 662 unsigned int penalty_for_intra_8x8_non_dc_pred_mode: 8; 663 unsigned int intra_compute_type: 8; 664 unsigned int avc_intra_8x8_mask: 8; 665 unsigned int intra_sad_adjust: 8; 666 } dw4; 667 668 struct { 669 unsigned int fixed_point_lambda_cu_mode_for_cost_calculation; 670 } dw5; 671 672 struct { 673 unsigned int screen_content_flag: 1; 674 unsigned int reserved: 31; 675 } dw6; 676 677 struct { 678 unsigned int mode_cost_intra_non_pred: 8; 679 unsigned int mode_cost_intra_16x16: 8; 680 unsigned int mode_cost_intra_8x8: 8; 681 unsigned int mode_cost_intra_4x4: 8; 682 } dw7; 683 684 struct { 685 unsigned int fixed_point_lambda_cu_mode_for_luma; 686 } dw8; 687 688 struct { 689 unsigned int widi_intra_refresh_mb_num: 16; 690 unsigned int widi_intra_refresh_unit_in_mb: 8; 691 unsigned int widi_intra_refresh_qp_delta: 8; 692 } dw9; 693 694 struct { 695 unsigned int haar_transform_mode: 2; 696 unsigned int simplified_flag_for_inter: 1; 697 unsigned int reserved: 29; 698 } dw10; 699 700 struct { 701 unsigned int reserved; 702 } dw11; 703 704 struct { 705 unsigned int reserved; 706 } dw12; 707 708 struct { 709 unsigned int reserved; 710 } dw13; 711 712 struct { 713 unsigned int reserved; 714 } dw14; 715 716 struct { 717 unsigned int reserved; 718 } dw15; 719 720 struct { 721 unsigned int bti_src_y; 722 } dw16; 723 724 struct { 725 unsigned int bti_sad_16x16_pu; 726 } dw17; 727 728 struct { 729 unsigned int bti_pak_object; 730 } dw18; 731 732 struct { 733 unsigned int bti_sad_32x32_pu_mode; 734 } dw19; 735 736 struct { 737 unsigned int bti_vme_mode_8x8; 738 } dw20; 739 740 struct { 741 unsigned int bti_slice_map; 742 } dw21; 743 744 struct { 745 unsigned int bti_vme_src; 746 } dw22; 747 748 struct { 749 unsigned int bti_brc_input; 750 } dw23; 751 752 struct { 753 unsigned int bti_simplest_intra; 754 } dw24; 755 756 struct { 757 unsigned int bti_lcu_qp_surface; 758 } dw25; 759 760 761 struct { 762 unsigned int bti_brc_data; 763 } dw26; 764 765 struct { 766 unsigned int bti_debug; 767 } dw27; 768 } gen9_hevc_enc_16x16_pu_curbe_data; 769 770 typedef struct _gen9_hevc_mbenc_8x8_pu_curbe_data { 771 struct { 772 unsigned int frame_width: 16; 773 unsigned int frame_height: 16; 774 } dw0; 775 776 struct { 777 unsigned int slice_type: 2; 778 unsigned int pu_type: 2; 779 unsigned int dc_filter_flag: 1; 780 unsigned int angle_refine_flag: 1; 781 unsigned int lcu_type: 1; 782 unsigned int screen_content_flag: 1; 783 unsigned int widi_intra_refresh_en: 2; 784 unsigned int enable_rolling_intra: 1; 785 unsigned int half_update_mixed_lcu: 1; 786 unsigned int reserved0: 4; 787 unsigned int qp_value: 8; 788 unsigned int enable_intra_early_exit: 1; 789 unsigned int brc_enable: 1; 790 unsigned int lcu_brc_enable: 1; 791 unsigned int roi_enable: 1; 792 unsigned int fast_surveillance_flag: 1; 793 unsigned int reserved1: 2; 794 unsigned int enable_debug_dump: 1; 795 } dw1; 796 797 struct { 798 unsigned int luma_lambda; 799 } dw2; 800 801 struct { 802 unsigned int chroma_lambda; 803 } dw3; 804 805 struct { 806 unsigned int harr_trans_form_flag: 2; 807 unsigned int simplified_flag_for_inter: 1; 808 unsigned int reserved: 29; 809 } dw4; 810 811 struct { 812 unsigned int widi_intra_refresh_mb_num: 16; 813 unsigned int widi_intra_refresh_unit_in_mb: 8; 814 unsigned int widi_intra_refresh_qp_delta: 8; 815 } dw5; 816 817 struct { 818 unsigned int reserved; 819 } dw6; 820 821 struct { 822 unsigned int reserved; 823 } dw7; 824 825 struct { 826 unsigned int bti_src_y; 827 } dw8; 828 829 struct { 830 unsigned int bti_slice_map; 831 } dw9; 832 833 struct { 834 unsigned int bti_vme_8x8_mode; 835 } dw10; 836 837 struct { 838 unsigned int bti_intra_mode; 839 } dw11; 840 841 struct { 842 unsigned int bti_brc_input; 843 } dw12; 844 845 struct { 846 unsigned int bti_simplest_intra; 847 } dw13; 848 849 struct { 850 unsigned int bti_lcu_qp_surface; 851 } dw14; 852 853 struct { 854 unsigned int bti_brc_data; 855 } dw15; 856 857 struct { 858 unsigned int bti_debug; 859 } dw16; 860 } gen9_hevc_mbenc_8x8_pu_curbe_data; 861 862 typedef struct _gen9_hevc_mbenc_8x8_pu_fmode_curbe_data { 863 struct { 864 unsigned int frame_width: 16; 865 unsigned int frame_height: 16; 866 } dw0; 867 868 struct { 869 unsigned int slice_type: 2; 870 unsigned int pu_type: 2; 871 unsigned int pak_reording_flag: 1; 872 unsigned int reserved0: 1; 873 unsigned int lcu_type: 1; 874 unsigned int screen_content_flag: 1; 875 unsigned int widi_intra_refresh_en: 2; 876 unsigned int enable_rolling_intra: 1; 877 unsigned int half_update_mixed_lcu: 1; 878 unsigned int reserved1: 12; 879 unsigned int enable_intra_early_exit: 1; 880 unsigned int brc_enable: 1; 881 unsigned int lcu_brc_enable: 1; 882 unsigned int roi_enable: 1; 883 unsigned int fast_surveillance_flag: 1; 884 unsigned int reserved2: 2; 885 unsigned int enable_debug_dump: 1; 886 } dw1; 887 888 struct { 889 unsigned int luma_lambda; 890 } dw2; 891 892 struct { 893 unsigned int lambda_for_dist_calculation; 894 } dw3; 895 896 struct { 897 unsigned int mode_cost_for_8x8_pu_tu8; 898 } dw4; 899 900 struct { 901 unsigned int mode_cost_for_8x8_pu_tu4; 902 } dw5; 903 904 struct { 905 unsigned int satd_16x16_pu_threshold: 16; 906 unsigned int bias_factor_toward_8x8: 16; 907 } dw6; 908 909 struct { 910 unsigned int qp: 16; 911 unsigned int qp_for_inter: 16; 912 } dw7; 913 914 struct { 915 unsigned int simplified_flag_for_inter: 1; 916 unsigned int reserved0: 7; 917 unsigned int kbl_control_flag: 1; 918 unsigned int reserved1: 23; 919 } dw8; 920 921 struct { 922 unsigned int widi_intra_refresh_mb_num: 16; 923 unsigned int widi_intra_refresh_unit_in_mb: 8; 924 unsigned int widi_intra_refresh_qp_delta: 8; 925 } dw9; 926 927 struct { 928 unsigned int reserved; 929 } dw10; 930 931 struct { 932 unsigned int reserved; 933 } dw11; 934 935 struct { 936 unsigned int reserved; 937 } dw12; 938 939 struct { 940 unsigned int reserved; 941 } dw13; 942 943 struct { 944 unsigned int reserved; 945 } dw14; 946 947 struct { 948 unsigned int reserved; 949 } dw15; 950 951 struct { 952 unsigned int bti_pak_object; 953 } dw16; 954 955 struct { 956 unsigned int bti_vme_8x8_mode; 957 } dw17; 958 959 struct { 960 unsigned int bti_intra_mode; 961 } dw18; 962 963 struct { 964 unsigned int bti_pak_command; 965 } dw19; 966 967 struct { 968 unsigned int bti_slice_map; 969 } dw20; 970 971 struct { 972 unsigned int bti_intra_dist; 973 } dw21; 974 975 struct { 976 unsigned int bti_brc_input; 977 } dw22; 978 979 struct { 980 unsigned int bti_simplest_intra; 981 } dw23; 982 983 struct { 984 unsigned int bti_lcu_qp_surface; 985 } dw24; 986 987 struct { 988 unsigned int bti_brc_data; 989 } dw25; 990 991 struct { 992 unsigned int bti_debug; 993 } dw26; 994 } gen9_hevc_mbenc_8x8_pu_fmode_curbe_data; 995 996 typedef struct _gen9_hevc_mbenc_b_32x32_pu_intra_curbe_data { 997 struct { 998 unsigned int frame_width: 16; 999 unsigned int frame_height: 16; 1000 } dw0; 1001 1002 struct { 1003 unsigned int slice_type: 2; 1004 unsigned int reserved0: 6; 1005 unsigned int log2_min_tu_size: 8; 1006 unsigned int flags: 8; 1007 unsigned int enable_intra_early_exit: 1; 1008 unsigned int hme_enable: 1; 1009 unsigned int fast_surveillance_flag: 1; 1010 unsigned int reserved1: 4; 1011 unsigned int enable_debug_dump: 1; 1012 } dw1; 1013 1014 struct { 1015 unsigned int qp_value: 16; 1016 unsigned int qp_multiplier: 16; 1017 } dw2; 1018 1019 struct { 1020 unsigned int reserved; 1021 } dw3; 1022 1023 struct { 1024 unsigned int reserved; 1025 } dw4; 1026 1027 struct { 1028 unsigned int reserved; 1029 } dw5; 1030 1031 struct { 1032 unsigned int reserved; 1033 } dw6; 1034 1035 struct { 1036 unsigned int reserved; 1037 } dw7; 1038 1039 struct { 1040 unsigned int bti_per_32x32_pu_intra_checck; 1041 } dw8; 1042 1043 struct { 1044 unsigned int bti_src_y; 1045 } dw9; 1046 1047 struct { 1048 unsigned int bti_src_y2x; 1049 } dw10; 1050 1051 struct { 1052 unsigned int bti_slice_map; 1053 } dw11; 1054 1055 struct { 1056 unsigned int bti_vme_y2x; 1057 } dw12; 1058 1059 struct { 1060 unsigned int bti_simplest_intra; 1061 } dw13; 1062 1063 struct { 1064 unsigned int bti_hme_mv_pred; 1065 1066 } dw14; 1067 1068 struct { 1069 unsigned int bti_hme_dist; 1070 } dw15; 1071 1072 struct { 1073 unsigned int bti_lcu_skip; 1074 } dw16; 1075 1076 struct { 1077 unsigned int bti_debug; 1078 } dw17; 1079 } gen9_hevc_mbenc_b_32x32_pu_intra_curbe_data; 1080 1081 typedef struct _gen9_hevc_mbenc_b_mb_enc_curbe_data { 1082 struct { 1083 unsigned int skip_mode_en: 1; 1084 unsigned int adaptive_en: 1; 1085 unsigned int bi_mix_dis: 1; 1086 unsigned int reserved0: 2; 1087 unsigned int early_ime_success_enable: 1; 1088 unsigned int reserved1: 1; 1089 unsigned int t_8x8_flag_for_inter_en: 1; 1090 unsigned int reserved2: 16; 1091 unsigned int early_ime_stop: 8; 1092 } dw0; 1093 1094 struct { 1095 unsigned int max_num_mvs: 6; 1096 unsigned int reserved0: 10; 1097 unsigned int bi_weight: 6; 1098 unsigned int reserved1: 6; 1099 unsigned int uni_mix_disable: 1; 1100 unsigned int reserved2: 3; 1101 } dw1; 1102 1103 struct { 1104 unsigned int len_sp: 8; 1105 unsigned int max_num_su: 8; 1106 unsigned int pic_width: 16; 1107 } dw2; 1108 1109 struct { 1110 unsigned int src_size: 2; 1111 unsigned int reserved0: 2; 1112 unsigned int mb_type_remap: 2; 1113 unsigned int src_access: 1; 1114 unsigned int ref_access: 1; 1115 unsigned int search_ctrl: 3; 1116 unsigned int dual_search_path_option: 1; 1117 unsigned int sub_pel_mode: 2; 1118 unsigned int skip_type: 1; 1119 unsigned int disable_field_cache_alloc: 1; 1120 unsigned int inter_chroma_mode: 1; 1121 unsigned int ft_enable: 1; 1122 unsigned int bme_disable_fbr: 1; 1123 unsigned int block_based_skip_enable: 1; 1124 unsigned int inter_sad: 2; 1125 unsigned int intra_sad: 2; 1126 unsigned int sub_mb_part_mask: 7; 1127 unsigned int reserved1: 1; 1128 } dw3; 1129 1130 struct { 1131 unsigned int pic_height_minus1: 16; 1132 unsigned int reserved0: 8; 1133 unsigned int enable_debug: 1; 1134 unsigned int reserved1: 3; 1135 unsigned int hme_enable: 1; 1136 unsigned int slice_type: 2; 1137 unsigned int use_actual_ref_qp_value: 1; 1138 } dw4; 1139 1140 struct { 1141 unsigned int reserved: 16; 1142 unsigned int ref_width: 8; 1143 unsigned int ref_height: 8; 1144 } dw5; 1145 1146 struct { 1147 unsigned int frame_width: 16; 1148 unsigned int frame_height: 16; 1149 } dw6; 1150 1151 struct { 1152 unsigned int intra_part_mask: 5; 1153 unsigned int non_skip_zmv_added: 1; 1154 unsigned int non_skip_mode_added: 1; 1155 unsigned int luma_intra_src_corner_swap: 1; 1156 unsigned int reserved0: 8; 1157 unsigned int mv_cost_scale_factor: 2; 1158 unsigned int bilinear_enable: 1; 1159 unsigned int reserved1: 1; 1160 unsigned int weighted_sad_haar: 1; 1161 unsigned int aconly_haar: 1; 1162 unsigned int refid_cost_mode: 1; 1163 unsigned int reserved2: 1; 1164 unsigned int skip_center_mask: 8; 1165 } dw7; 1166 1167 struct { 1168 unsigned int mode0_cost: 8; 1169 unsigned int mode1_cost: 8; 1170 unsigned int mode2_cost: 8; 1171 unsigned int mode3_cost: 8; 1172 } dw8; 1173 1174 struct { 1175 unsigned int mode4_cost: 8; 1176 unsigned int mode5_cost: 8; 1177 unsigned int mode6_cost: 8; 1178 unsigned int mode7_cost: 8; 1179 } dw9; 1180 1181 struct { 1182 unsigned int mode8_cost: 8; 1183 unsigned int mode9_cost: 8; 1184 unsigned int ref_id_cost: 8; 1185 unsigned int chroma_intra_mode_cost: 8; 1186 } dw10; 1187 1188 struct { 1189 unsigned int mv0_cost: 8; 1190 unsigned int mv1_cost: 8; 1191 unsigned int mv2_cost: 8; 1192 unsigned int mv3_cost: 8; 1193 } dw11; 1194 1195 struct { 1196 unsigned int mv4_cost: 8; 1197 unsigned int mv5_cost: 8; 1198 unsigned int mv6_cost: 8; 1199 unsigned int mv7_cost: 8; 1200 } dw12; 1201 1202 struct { 1203 unsigned int qp_prime_y: 8; 1204 unsigned int qp_prime_cb: 8; 1205 unsigned int qp_prime_cr: 8; 1206 unsigned int target_size_in_word: 8; 1207 } dw13; 1208 1209 struct { 1210 unsigned int sic_fwd_trans_coeff_thread_0: 16; 1211 unsigned int sic_fwd_trans_coeff_thread_1: 8; 1212 unsigned int sic_fwd_trans_coeff_thread_2: 8; 1213 } dw14; 1214 1215 struct { 1216 unsigned int sic_fwd_trans_coeff_thread_3: 8; 1217 unsigned int sic_fwd_trans_coeff_thread_4: 8; 1218 unsigned int sic_fwd_trans_coeff_thread_5: 8; 1219 unsigned int sic_fwd_trans_coeff_thread_6: 8; 1220 } dw15; 1221 1222 struct { 1223 struct gen9_search_path_delta sp_delta_0; 1224 struct gen9_search_path_delta sp_delta_1; 1225 struct gen9_search_path_delta sp_delta_2; 1226 struct gen9_search_path_delta sp_delta_3; 1227 } dw16; 1228 1229 struct { 1230 struct gen9_search_path_delta sp_delta_4; 1231 struct gen9_search_path_delta sp_delta_5; 1232 struct gen9_search_path_delta sp_delta_6; 1233 struct gen9_search_path_delta sp_delta_7; 1234 } dw17; 1235 1236 struct { 1237 struct gen9_search_path_delta sp_delta_8; 1238 struct gen9_search_path_delta sp_delta_9; 1239 struct gen9_search_path_delta sp_delta_10; 1240 struct gen9_search_path_delta sp_delta_11; 1241 } dw18; 1242 1243 struct { 1244 struct gen9_search_path_delta sp_delta_12; 1245 struct gen9_search_path_delta sp_delta_13; 1246 struct gen9_search_path_delta sp_delta_14; 1247 struct gen9_search_path_delta sp_delta_15; 1248 } dw19; 1249 1250 struct { 1251 struct gen9_search_path_delta sp_delta_16; 1252 struct gen9_search_path_delta sp_delta_17; 1253 struct gen9_search_path_delta sp_delta_18; 1254 struct gen9_search_path_delta sp_delta_19; 1255 } dw20; 1256 1257 struct { 1258 struct gen9_search_path_delta sp_delta_20; 1259 struct gen9_search_path_delta sp_delta_21; 1260 struct gen9_search_path_delta sp_delta_22; 1261 struct gen9_search_path_delta sp_delta_23; 1262 } dw21; 1263 1264 struct { 1265 struct gen9_search_path_delta sp_delta_24; 1266 struct gen9_search_path_delta sp_delta_25; 1267 struct gen9_search_path_delta sp_delta_26; 1268 struct gen9_search_path_delta sp_delta_27; 1269 } dw22; 1270 1271 struct { 1272 struct gen9_search_path_delta sp_delta_28; 1273 struct gen9_search_path_delta sp_delta_29; 1274 struct gen9_search_path_delta sp_delta_30; 1275 struct gen9_search_path_delta sp_delta_31; 1276 } dw23; 1277 1278 struct { 1279 struct gen9_search_path_delta sp_delta_32; 1280 struct gen9_search_path_delta sp_delta_33; 1281 struct gen9_search_path_delta sp_delta_34; 1282 struct gen9_search_path_delta sp_delta_35; 1283 } dw24; 1284 1285 struct { 1286 struct gen9_search_path_delta sp_delta_36; 1287 struct gen9_search_path_delta sp_delta_37; 1288 struct gen9_search_path_delta sp_delta_38; 1289 struct gen9_search_path_delta sp_delta_39; 1290 } dw25; 1291 1292 struct { 1293 struct gen9_search_path_delta sp_delta_40; 1294 struct gen9_search_path_delta sp_delta_41; 1295 struct gen9_search_path_delta sp_delta_42; 1296 struct gen9_search_path_delta sp_delta_43; 1297 } dw26; 1298 1299 struct { 1300 struct gen9_search_path_delta sp_delta_44; 1301 struct gen9_search_path_delta sp_delta_45; 1302 struct gen9_search_path_delta sp_delta_46; 1303 struct gen9_search_path_delta sp_delta_47; 1304 } dw27; 1305 1306 struct { 1307 struct gen9_search_path_delta sp_delta_48; 1308 struct gen9_search_path_delta sp_delta_49; 1309 struct gen9_search_path_delta sp_delta_50; 1310 struct gen9_search_path_delta sp_delta_51; 1311 } dw28; 1312 1313 struct { 1314 struct gen9_search_path_delta sp_delta_52; 1315 struct gen9_search_path_delta sp_delta_53; 1316 struct gen9_search_path_delta sp_delta_54; 1317 struct gen9_search_path_delta sp_delta_55; 1318 } dw29; 1319 1320 struct { 1321 unsigned int intra_4x4_mode_mask: 9; 1322 unsigned int reserved0: 7; 1323 unsigned int intra_8x8_mode_mask: 9; 1324 unsigned int reserved1: 7; 1325 } dw30; 1326 1327 struct { 1328 unsigned int intra_16x16_mode_mask: 4; 1329 unsigned int intra_chroma_mode_mask: 4; 1330 unsigned int intra_chmpute_type: 2; 1331 unsigned int reserved: 22; 1332 } dw31; 1333 1334 struct { 1335 unsigned int skip_val: 16; 1336 unsigned int multi_pred_l0_disable: 8; 1337 unsigned int multi_pred_l1_disable: 8; 1338 } dw32; 1339 1340 struct { 1341 unsigned int intra_16x16_nondc_pred_penalty: 8; 1342 unsigned int intra_8x8_nondc_pred_penalty: 8; 1343 unsigned int intra_4x4_nondc_pred_penalty: 8; 1344 unsigned int reserved: 8; 1345 } dw33; 1346 1347 struct { 1348 float lambda_me; 1349 } dw34; 1350 1351 struct { 1352 unsigned int simp_intra_inter_threashold: 16; 1353 unsigned int mode_cost_sp: 8; 1354 unsigned int widi_intra_refresh_en: 2; 1355 unsigned int widi_first_intra_refresh: 1; 1356 unsigned int enable_rolling_intra: 1; 1357 unsigned int half_update_mixed_lcu: 1; 1358 unsigned int reserved: 3; 1359 } dw35; 1360 1361 struct { 1362 unsigned int num_refidx_l0_minus_one: 8; 1363 unsigned int hme_combined_extra_sus: 8; 1364 unsigned int num_refidx_l1_minus_one: 8; 1365 unsigned int power_saving: 1; 1366 unsigned int brc_enable: 1; 1367 unsigned int lcu_brc_enable: 1; 1368 unsigned int roi_enable: 1; 1369 unsigned int fast_surveillance_flag: 1; 1370 unsigned int check_all_fractional_enable: 1; 1371 unsigned int hme_combined_over_lap: 2; 1372 } dw36; 1373 1374 struct { 1375 unsigned int actual_qp_refid0_list0: 8; 1376 unsigned int actual_qp_refid1_list0: 8; 1377 unsigned int actual_qp_refid2_list0: 8; 1378 unsigned int actual_qp_refid3_list0: 8; 1379 } dw37; 1380 1381 struct { 1382 unsigned int widi_num_intra_refresh_off_frames: 16; 1383 unsigned int widi_num_frame_in_gob: 16; 1384 } dw38; 1385 1386 struct { 1387 unsigned int actual_qp_refid0_list1: 8; 1388 unsigned int actual_qp_refid1_list1: 8; 1389 unsigned int ref_cost: 16; 1390 } dw39; 1391 1392 struct { 1393 unsigned int reserved; 1394 } dw40; 1395 1396 struct { 1397 unsigned int reserved; 1398 } dw41; 1399 1400 struct { 1401 unsigned int reserved; 1402 } dw42; 1403 1404 struct { 1405 unsigned int reserved; 1406 } dw43; 1407 1408 struct { 1409 unsigned int max_num_merge_candidates: 4; 1410 unsigned int max_num_ref_list0: 4; 1411 unsigned int max_num_ref_list1: 4; 1412 unsigned int reserved: 4; 1413 unsigned int max_vmvr: 16; 1414 } dw44; 1415 1416 struct { 1417 unsigned int temporal_mvp_enable_flag: 1; 1418 unsigned int reserved: 7; 1419 unsigned int log2_parallel_merge_level: 8; 1420 unsigned int hme_combine_len_pslice: 8; 1421 unsigned int hme_combine_len_bslice: 8; 1422 } dw45; 1423 1424 struct { 1425 unsigned int log2_min_tu_size: 8; 1426 unsigned int log2_max_tu_size: 8; 1427 unsigned int log2_min_cu_size: 8; 1428 unsigned int log2_max_cu_size: 8; 1429 } dw46; 1430 1431 struct { 1432 unsigned int num_regions_in_slice: 8; 1433 unsigned int type_of_walking_pattern: 4; 1434 unsigned int chroma_flatness_check_flag: 1; 1435 unsigned int enable_intra_early_exit: 1; 1436 unsigned int skip_intra_krn_flag: 1; 1437 unsigned int screen_content_flag: 1; 1438 unsigned int is_low_delay: 1; 1439 unsigned int collocated_from_l0_flag: 1; 1440 unsigned int arbitary_slice_flag: 1; 1441 unsigned int multi_slice_flag: 1; 1442 unsigned int reserved: 4; 1443 unsigned int is_curr_ref_l0_long_term: 1; 1444 unsigned int is_curr_ref_l1_long_term: 1; 1445 unsigned int num_region_minus1: 6; 1446 } dw47; 1447 1448 struct { 1449 unsigned int current_td_l0_0: 16; 1450 unsigned int current_td_l0_1: 16; 1451 } dw48; 1452 1453 struct { 1454 unsigned int current_td_l0_2: 16; 1455 unsigned int current_td_l0_3: 16; 1456 } dw49; 1457 1458 struct { 1459 unsigned int current_td_l1_0: 16; 1460 unsigned int current_td_l1_1: 16; 1461 } dw50; 1462 1463 struct { 1464 unsigned int widi_intra_refresh_mb_num: 16; 1465 unsigned int widi_intra_refresh_unit_in_mb: 8; 1466 unsigned int widi_intra_refresh_qp_delta: 8; 1467 } dw51; 1468 1469 struct { 1470 unsigned int num_of_units_in_region: 16; 1471 unsigned int max_height_in_region: 16; 1472 } dw52; 1473 1474 struct { 1475 unsigned int widi_intra_refresh_ref_width: 8; 1476 unsigned int widi_intra_refresh_ref_height: 8; 1477 unsigned int reserved: 16; 1478 } dw53; 1479 1480 struct { 1481 unsigned int reserved; 1482 } dw54; 1483 1484 struct { 1485 unsigned int reserved; 1486 } dw55; 1487 1488 struct { 1489 unsigned int bti_cu_record; 1490 } dw56; 1491 1492 struct { 1493 unsigned int bti_pak_cmd; 1494 } dw57; 1495 1496 struct { 1497 unsigned int bti_src_y; 1498 } dw58; 1499 1500 struct { 1501 unsigned int bti_intra_dist; 1502 } dw59; 1503 1504 struct { 1505 unsigned int bti_min_dist; 1506 } dw60; 1507 1508 struct { 1509 unsigned int bti_hme_mv_pred_fwd_bwd_surf_index; 1510 } dw61; 1511 1512 struct { 1513 unsigned int bti_hme_dist_surf_index; 1514 } dw62; 1515 1516 struct { 1517 unsigned int bti_slice_map; 1518 } dw63; 1519 1520 struct { 1521 unsigned int bti_vme_saved_uni_sic; 1522 } dw64; 1523 1524 struct { 1525 unsigned int bti_simplest_intra; 1526 } dw65; 1527 1528 struct { 1529 unsigned int bti_collocated_refframe; 1530 } dw66; 1531 1532 struct { 1533 unsigned int bti_reserved; 1534 } dw67; 1535 1536 struct { 1537 unsigned int bti_brc_input; 1538 } dw68; 1539 1540 struct { 1541 unsigned int bti_lcu_qp; 1542 } dw69; 1543 1544 struct { 1545 unsigned int bti_brc_data; 1546 } dw70; 1547 1548 struct { 1549 unsigned int bti_vme_inter_prediction_surf_index; 1550 } dw71; 1551 1552 union { 1553 unsigned int bti_vme_inter_prediction_b_surf_index; 1554 1555 unsigned int bti_concurrent_thread_map; 1556 } dw72; 1557 1558 union { 1559 unsigned int bti_concurrent_thread_map; 1560 1561 unsigned int bti_mb_data_cur_frame; 1562 } dw73; 1563 1564 union { 1565 unsigned int bti_mb_data_cur_frame; 1566 1567 unsigned int bti_mvp_cur_frame; 1568 } dw74; 1569 1570 union { 1571 unsigned int bti_mvp_cur_frame; 1572 1573 unsigned int bti_debug; 1574 } dw75; 1575 1576 struct { 1577 unsigned int bti_debug; 1578 } dw76; 1579 } gen9_hevc_mbenc_b_mb_enc_curbe_data; 1580 1581 typedef struct _gen9_hevc_mbenc_b_pak_curbe_data { 1582 struct { 1583 unsigned int frame_width: 16; 1584 unsigned int frame_height: 16; 1585 } dw0; 1586 1587 struct { 1588 unsigned int qp: 8; 1589 unsigned int reserved: 8; 1590 unsigned int max_vmvr: 16; 1591 } dw1; 1592 1593 struct { 1594 unsigned int slice_type: 2; 1595 unsigned int reserved0: 6; 1596 unsigned int simplest_intra_enable: 1; 1597 unsigned int brc_enable: 1; 1598 unsigned int lcu_brc_enable: 1; 1599 unsigned int roi_enable: 1; 1600 unsigned int fast_surveillance_flag: 1; 1601 unsigned int enable_rolling_intra: 1; 1602 unsigned int reserved1: 2; 1603 unsigned int kbl_control_flag: 1; 1604 unsigned int reserved2: 14; 1605 unsigned int screen_content: 1; 1606 } dw2; 1607 1608 struct { 1609 unsigned int widi_intra_refresh_mb_num: 16; 1610 unsigned int widi_intra_refresh_unit_in_mb: 8; 1611 unsigned int widi_intra_refresh_qp_delta: 8; 1612 } dw3; 1613 1614 struct { 1615 unsigned int reserved; 1616 } dw4_15[12]; 1617 1618 struct { 1619 unsigned int bti_cu_record; 1620 } dw16; 1621 1622 struct { 1623 unsigned int bti_pak_obj; 1624 } dw17; 1625 1626 struct { 1627 unsigned int bti_slice_map; 1628 } dw18; 1629 1630 struct { 1631 unsigned int bti_brc_input; 1632 } dw19; 1633 1634 struct { 1635 unsigned int bti_lcu_qp; 1636 } dw20; 1637 1638 struct { 1639 unsigned int bti_brc_data; 1640 } dw21; 1641 1642 struct { 1643 unsigned int bti_mb_data; 1644 } dw22; 1645 1646 struct { 1647 unsigned int bti_mvp_surface; 1648 } dw23; 1649 1650 struct { 1651 unsigned int bti_debug; 1652 } dw24; 1653 } gen9_hevc_mbenc_b_pak_curbe_data; 1654 1655 typedef enum _GEN9_HEVC_DOWNSCALE_STAGE { 1656 HEVC_ENC_DS_DISABLED = 0, 1657 HEVC_ENC_2xDS_STAGE = 1, 1658 HEVC_ENC_4xDS_STAGE = 2, 1659 HEVC_ENC16xDS_STAGE = 3, 1660 HEVC_ENC_2xDS_4xDS_STAGE = 4, 1661 HEVC_ENC_32xDS_STAGE = 5 1662 } GEN9_HEVC_DOWNSCALE_STAGE; 1663 1664 typedef struct _gen95_hevc_mbenc_ds_combined_curbe_data { 1665 struct { 1666 unsigned int pak_bitdepth_chroma: 8; 1667 unsigned int pak_bitdepth_luma: 8; 1668 unsigned int enc_bitdepth_chroma: 8; 1669 unsigned int enc_bitdepth_luma: 7; 1670 unsigned int rounding_value: 1; 1671 } dw0; 1672 1673 struct { 1674 unsigned int pic_format: 8; 1675 unsigned int pic_convert_flag: 1; 1676 unsigned int pic_down_scale: 3; 1677 unsigned int pic_mb_stat_output_cntrl: 1; 1678 unsigned int mbz: 19; 1679 } dw1; 1680 1681 struct { 1682 unsigned int orig_pic_width: 16; 1683 unsigned int orig_pic_height: 16; 1684 } dw2; 1685 1686 struct { 1687 unsigned int bti_surface_p010; 1688 } dw3; 1689 1690 struct { 1691 unsigned int bti_surface_nv12; 1692 } dw4; 1693 1694 struct { 1695 unsigned int bti_src_y_4xdownscaled; 1696 } dw5; 1697 1698 struct { 1699 unsigned int bti_surf_mbstate; 1700 } dw6; 1701 1702 struct { 1703 unsigned int bit_src_y_2xdownscaled; 1704 } dw7; 1705 } gen95_hevc_mbenc_ds_combined_curbe_data; 1706 1707 #define GEN9_HEVC_AVBR_ACCURACY 30 1708 #define GEN9_HEVC_AVBR_CONVERGENCE 150 1709 1710 typedef enum _GEN9_HEVC_BRC_INIT_FLAGS { 1711 HEVC_BRCINIT_ISCBR = 0x0010, 1712 HEVC_BRCINIT_ISVBR = 0x0020, 1713 HEVC_BRCINIT_ISAVBR = 0x0040, 1714 HEVC_BRCINIT_ISQVBR = 0x0080, 1715 HEVC_BRCINIT_FIELD_PIC = 0x0100, 1716 HEVC_BRCINIT_ISICQ = 0x0200, 1717 HEVC_BRCINIT_ISVCM = 0x0400, 1718 HEVC_BRCINIT_IGNORE_PICTURE_HEADER_SIZE = 0x2000, 1719 HEVC_BRCINIT_ISCQP = 0x4000, 1720 HEVC_BRCINIT_DISABLE_MBBRC = 0x8000 1721 } GEN9_HEVC_BRCINIT_FLAGS; 1722 1723 // BRC kernel paramerters 1724 typedef struct _gen9_hevc_brc_init_reset_curbe_data { 1725 struct { 1726 unsigned int profile_level_max_frame; 1727 } dw0; 1728 1729 struct { 1730 unsigned int init_buf_full; 1731 } dw1; 1732 1733 struct { 1734 unsigned int buf_size; 1735 } dw2; 1736 1737 struct { 1738 unsigned int targe_bit_rate; 1739 } dw3; 1740 1741 struct { 1742 unsigned int maximum_bit_rate; 1743 } dw4; 1744 1745 struct { 1746 unsigned int minimum_bit_rate; 1747 } dw5; 1748 1749 struct { 1750 unsigned int frame_rate_m; 1751 } dw6; 1752 1753 struct { 1754 unsigned int frame_rate_d; 1755 } dw7; 1756 1757 struct { 1758 unsigned int brc_flag: 16; 1759 unsigned int brc_param_a: 16; 1760 } dw8; 1761 1762 struct { 1763 unsigned int brc_param_b: 16; 1764 unsigned int frame_width: 16; 1765 } dw9; 1766 1767 struct { 1768 unsigned int frame_height: 16; 1769 unsigned int avbr_accuracy: 16; 1770 } dw10; 1771 1772 struct { 1773 unsigned int avbr_convergence: 16; 1774 unsigned int minimum_qp: 16; 1775 } dw11; 1776 1777 struct { 1778 unsigned int maximum_qp: 16; 1779 unsigned int number_slice: 16; 1780 } dw12; 1781 1782 struct { 1783 unsigned int reserved: 16; 1784 unsigned int brc_param_c: 16; 1785 } dw13; 1786 1787 struct { 1788 unsigned int brc_param_d: 16; 1789 unsigned int max_brc_level: 16; 1790 } dw14; 1791 1792 struct { 1793 unsigned int reserved; 1794 } dw15; 1795 1796 struct { 1797 unsigned int instant_rate_threshold0_pframe: 8; 1798 unsigned int instant_rate_threshold1_pframe: 8; 1799 unsigned int instant_rate_threshold2_pframe: 8; 1800 unsigned int instant_rate_threshold3_pframe: 8; 1801 } dw16; 1802 1803 struct { 1804 unsigned int instant_rate_threshold0_bframe: 8; 1805 unsigned int instant_rate_threshold1_bframe: 8; 1806 unsigned int instant_rate_threshold2_bframe: 8; 1807 unsigned int instant_rate_threshold3_bframe: 8; 1808 } dw17; 1809 1810 struct { 1811 unsigned int instant_rate_threshold0_iframe: 8; 1812 unsigned int instant_rate_threshold1_iframe: 8; 1813 unsigned int instant_rate_threshold2_iframe: 8; 1814 unsigned int instant_rate_threshold3_iframe: 8; 1815 } dw18; 1816 1817 struct { 1818 unsigned int deviation_threshold0_pbframe: 8; 1819 unsigned int deviation_threshold1_pbframe: 8; 1820 unsigned int deviation_threshold2_pbframe: 8; 1821 unsigned int deviation_threshold3_pbframe: 8; 1822 } dw19; 1823 1824 struct { 1825 unsigned int deviation_threshold4_pbframe: 8; 1826 unsigned int deviation_threshold5_pbframe: 8; 1827 unsigned int deviation_threshold6_pbframe: 8; 1828 unsigned int deviation_threshold7_pbframe: 8; 1829 } dw20; 1830 1831 struct { 1832 unsigned int deviation_threshold0_vbr_control: 8; 1833 unsigned int deviation_threshold1_vbr_control: 8; 1834 unsigned int deviation_threshold2_vbr_control: 8; 1835 unsigned int deviation_threshold3_vbr_control: 8; 1836 } dw21; 1837 1838 struct { 1839 unsigned int deviation_threshold4_vbr_control: 8; 1840 unsigned int deviation_threshold5_vbr_control: 8; 1841 unsigned int deviation_threshold6_vbr_control: 8; 1842 unsigned int deviation_threshold7_vbr_control: 8; 1843 } dw22; 1844 1845 struct { 1846 unsigned int deviation_threshold0_iframe: 8; 1847 unsigned int deviation_threshold1_iframe: 8; 1848 unsigned int deviation_threshold2_iframe: 8; 1849 unsigned int deviation_threshold3_iframe: 8; 1850 } dw23; 1851 1852 struct { 1853 unsigned int deviation_threshold4_iframe: 8; 1854 unsigned int deviation_threshold5_iframe: 8; 1855 unsigned int deviation_threshold6_iframe: 8; 1856 unsigned int deviation_threshold7_iframe: 8; 1857 } dw24; 1858 1859 struct { 1860 unsigned int acqp_buffer: 8; 1861 unsigned int intra_sad_transform: 8; 1862 unsigned int reserved: 16; 1863 } dw25; 1864 1865 struct { 1866 unsigned int reserved; 1867 } dw26; 1868 1869 struct { 1870 unsigned int reserved; 1871 } dw27; 1872 1873 struct { 1874 unsigned int reserved; 1875 } dw28; 1876 1877 struct { 1878 unsigned int reserved; 1879 } dw29; 1880 1881 struct { 1882 unsigned int reserved; 1883 } dw30; 1884 1885 struct { 1886 unsigned int reserved; 1887 } dw31; 1888 } gen9_hevc_brc_initreset_curbe_data; 1889 1890 // BRC Flag in BRC Update Kernel 1891 typedef enum _GEN9_HEVC_BRC_UPDATE_FLAG { 1892 HEVC_BRC_UPDATE_IS_FIELD = 0x01, 1893 HEVC_BRC_UPDATE_IS_MBAFF = (0x01 << 1), 1894 HEVC_BRC_UPDATE_IS_BOTTOM_FIELD = (0x01 << 2), 1895 HEVC_BRC_UPDATE_IS_ACTUALQP = (0x01 << 6), 1896 HEVC_BRC_UPDATE_IS_REFERENCE = (0x01 << 7) 1897 } GEN9_HEVC_BRC_UPDATE_FLAG; 1898 1899 typedef enum _GEN9_HEVC_BRC_UPDATE_FRAME_TYPE { 1900 HEVC_BRC_FTYPE_P_OR_LB = 0, 1901 HEVC_BRC_FTYPE_B = 1, 1902 HEVC_BRC_FTYPE_I = 2, 1903 HEVC_BRC_FTYPE_B1 = 3, 1904 HEVC_BRC_FTYPE_B2 = 4 1905 } GEN9_HEVC_BRC_UPDATE_FRAME_TYPE; 1906 1907 typedef struct _GEN9_HEVC_PAK_STATES { 1908 unsigned int HEVC_ENC_BYTECOUNT_FRAME; 1909 unsigned int HEVC_ENC_BYTECOUNT_FRAME_NOHEADER; 1910 unsigned int HEVC_ENC_IMAGE_STATUS_CONTROL; 1911 unsigned int reserved0; 1912 unsigned int HEVC_ENC_IMAGE_STATUS_CONTROL_FOR_LAST_PASS; 1913 unsigned int reserved1[3]; 1914 } GEN9_HEVC_PAK_STATES; 1915 1916 typedef struct _gen9_hevc_brc_udpate_curbe_data { 1917 struct { 1918 unsigned int target_size; 1919 } dw0; 1920 1921 struct { 1922 unsigned int frame_number; 1923 } dw1; 1924 1925 struct { 1926 unsigned int picture_header_size; 1927 } dw2; 1928 1929 struct { 1930 unsigned int start_gadj_frame0: 16; 1931 unsigned int start_gadj_frame1: 16; 1932 } dw3; 1933 1934 struct { 1935 unsigned int start_gadj_frame2: 16; 1936 unsigned int start_gadj_frame3: 16; 1937 } dw4; 1938 1939 struct { 1940 unsigned int target_size_flag: 8; 1941 unsigned int brc_flag: 8; 1942 unsigned int max_num_paks: 8; 1943 unsigned int curr_frame_type: 8; 1944 } dw5; 1945 1946 struct { 1947 unsigned int num_skipped_frames: 8; 1948 unsigned int cqp_value: 8; 1949 unsigned int roi_flag: 8; 1950 unsigned int roi_ratio: 8; 1951 } dw6; 1952 1953 struct { 1954 unsigned int frame_width_in_lcu: 8; 1955 unsigned int reserved: 24; 1956 } dw7; 1957 1958 struct { 1959 unsigned int start_global_adjust_mult0: 8; 1960 unsigned int start_global_adjust_mult1: 8; 1961 unsigned int start_global_adjust_mult2: 8; 1962 unsigned int start_global_adjust_mult3: 8; 1963 } dw8; 1964 1965 struct { 1966 unsigned int start_global_adjust_mult4: 8; 1967 unsigned int start_global_adjust_divd0: 8; 1968 unsigned int start_global_adjust_divd1: 8; 1969 unsigned int start_global_adjust_divd2: 8; 1970 } dw9; 1971 1972 struct { 1973 unsigned int start_global_adjust_divd3: 8; 1974 unsigned int start_global_adjust_divd4: 8; 1975 unsigned int qp_threshold0: 8; 1976 unsigned int qp_threshold1: 8; 1977 } dw10; 1978 1979 struct { 1980 unsigned int qp_threshold2: 8; 1981 unsigned int qp_threshold3: 8; 1982 unsigned int g_rate_ratio_threshold0: 8; 1983 unsigned int g_rate_ratio_threshold1: 8; 1984 } dw11; 1985 1986 struct { 1987 unsigned int g_rate_ratio_threshold2: 8; 1988 unsigned int g_rate_ratio_threshold3: 8; 1989 unsigned int g_rate_ratio_threshold4: 8; 1990 unsigned int g_rate_ratio_threshold5: 8; 1991 } dw12; 1992 1993 struct { 1994 unsigned int g_rate_ratio_threshold6: 8; 1995 unsigned int g_rate_ratio_threshold7: 8; 1996 unsigned int g_rate_ratio_threshold8: 8; 1997 unsigned int g_rate_ratio_threshold9: 8; 1998 } dw13; 1999 2000 struct { 2001 unsigned int g_rate_ratio_threshold10: 8; 2002 unsigned int g_rate_ratio_threshold11: 8; 2003 unsigned int g_rate_ratio_threshold12: 8; 2004 unsigned int parallel_mode: 8; 2005 } dw14; 2006 2007 struct { 2008 unsigned int size_of_skipped_frames; 2009 } dw15; 2010 } gen9_hevc_brc_udpate_curbe_data; 2011 2012 typedef struct _gen9_hevc_brc_coarse_intra_curbe_data { 2013 struct { 2014 unsigned int picture_width_in_luma_samples: 16; 2015 unsigned int picture_height_in_luma_samples: 16; 2016 } dw0; 2017 2018 struct { 2019 unsigned int src_size: 2; 2020 unsigned int reserved0: 12; 2021 unsigned int skip_type: 1; 2022 unsigned int reserved1: 1; 2023 unsigned int inter_chroma_mode: 1; 2024 unsigned int ft_enable: 1; 2025 unsigned int reserved2: 1; 2026 unsigned int blk_skip_enabled: 1; 2027 unsigned int inter_sad: 2; 2028 unsigned int intra_sad: 2; 2029 unsigned int reserved3: 8; 2030 } dw1; 2031 2032 struct { 2033 unsigned int intra_park_mask: 5; 2034 unsigned int non_skip_zmv_added: 1; 2035 unsigned int non_skip_mode_added: 1; 2036 unsigned int intra_corner_swap: 1; 2037 unsigned int reserved0: 8; 2038 unsigned int mv_cost_scale_factor: 2; 2039 unsigned int bilinear_enable: 1; 2040 unsigned int reserved1: 1; 2041 unsigned int weighted_sad_haar: 1; 2042 unsigned int aconly_haar: 1; 2043 unsigned int refid_cost_mode: 1; 2044 unsigned int reserved2: 1; 2045 unsigned int skip_center_mask: 8; 2046 } dw2; 2047 2048 struct { 2049 unsigned int reserved; 2050 } dw3; 2051 2052 struct { 2053 unsigned int reserved; 2054 } dw4; 2055 2056 struct { 2057 unsigned int reserved; 2058 } dw5; 2059 2060 struct { 2061 unsigned int reserved; 2062 } dw6; 2063 2064 struct { 2065 unsigned int reserved; 2066 } dw7; 2067 2068 struct { 2069 unsigned int bti_src_y4; 2070 } dw8; 2071 2072 struct { 2073 unsigned int bti_intra_dist; 2074 } dw9; 2075 2076 struct { 2077 unsigned int bti_vme_intra; 2078 } dw10; 2079 } gen9_hevc_brc_coarse_intra_curbe_data; 2080 2081 // gen9 kernel header strcutures 2082 typedef struct _gen9_hevc_enc_kernel_header { 2083 unsigned int reserved: 6; 2084 unsigned int kernel_start_pointer: 26; 2085 } gen9_hevc_enc_kernel_header; 2086 2087 typedef struct _gen9_hevc_enc_kernels_header { 2088 int kernel_count; 2089 gen9_hevc_enc_kernel_header HEVC_ENC_I_2xDownSampling_Kernel; 2090 gen9_hevc_enc_kernel_header HEVC_ENC_I_32x32_PU_ModeDecision_Kernel; 2091 gen9_hevc_enc_kernel_header HEVC_ENC_I_16x16_PU_SADComputation_Kernel; 2092 gen9_hevc_enc_kernel_header HEVC_ENC_I_16x16_PU_ModeDecision_Kernel; 2093 gen9_hevc_enc_kernel_header HEVC_ENC_I_8x8_PU_Kernel; 2094 gen9_hevc_enc_kernel_header HEVC_ENC_I_8x8_PU_FMode_Kernel; 2095 gen9_hevc_enc_kernel_header HEVC_ENC_PB_32x32_PU_IntraCheck; 2096 gen9_hevc_enc_kernel_header HEVC_ENC_PB_MB; 2097 gen9_hevc_enc_kernel_header HEVC_ENC_I_DS4HME; 2098 gen9_hevc_enc_kernel_header HEVC_ENC_P_HME; 2099 gen9_hevc_enc_kernel_header HEVC_ENC_B_HME; 2100 gen9_hevc_enc_kernel_header HEVC_ENC_I_COARSE; 2101 gen9_hevc_enc_kernel_header HEVC_ENC_BRC_Init; 2102 gen9_hevc_enc_kernel_header HEVC_ENC_BRC_Reset; 2103 gen9_hevc_enc_kernel_header HEVC_ENC_BRC_Update; 2104 gen9_hevc_enc_kernel_header HEVC_ENC_BRC_LCU_Update; 2105 gen9_hevc_enc_kernel_header HEVC_ENC_PB_Pak; 2106 gen9_hevc_enc_kernel_header HEVC_ENC_PB_Widi; 2107 gen9_hevc_enc_kernel_header HEVC_ENC_BRC_Blockcopy; 2108 gen9_hevc_enc_kernel_header HEVC_ENC_DS_Combined; 2109 } gen9_hevc_enc_kernels_header; 2110 2111 typedef struct _gen9_hevc_enc_kernels_header_bxt { 2112 int kernel_count; 2113 gen9_hevc_enc_kernel_header HEVC_ENC_I_2xDownSampling_Kernel; 2114 gen9_hevc_enc_kernel_header HEVC_ENC_I_32x32_PU_ModeDecision_Kernel; 2115 gen9_hevc_enc_kernel_header HEVC_ENC_I_16x16_PU_SADComputation_Kernel; 2116 gen9_hevc_enc_kernel_header HEVC_ENC_I_16x16_PU_ModeDecision_Kernel; 2117 gen9_hevc_enc_kernel_header HEVC_ENC_I_8x8_PU_Kernel; 2118 gen9_hevc_enc_kernel_header HEVC_ENC_I_8x8_PU_FMode_Kernel; 2119 gen9_hevc_enc_kernel_header HEVC_ENC_PB_32x32_PU_IntraCheck; 2120 gen9_hevc_enc_kernel_header HEVC_ENC_PB_MB; 2121 gen9_hevc_enc_kernel_header HEVC_ENC_I_DS4HME; 2122 gen9_hevc_enc_kernel_header HEVC_ENC_P_HME; 2123 gen9_hevc_enc_kernel_header HEVC_ENC_B_HME; 2124 gen9_hevc_enc_kernel_header HEVC_ENC_I_COARSE; 2125 gen9_hevc_enc_kernel_header HEVC_ENC_BRC_Init; 2126 gen9_hevc_enc_kernel_header HEVC_ENC_BRC_Reset; 2127 gen9_hevc_enc_kernel_header HEVC_ENC_BRC_Update; 2128 gen9_hevc_enc_kernel_header HEVC_ENC_BRC_LCU_Update; 2129 gen9_hevc_enc_kernel_header HEVC_ENC_PB_Pak; 2130 gen9_hevc_enc_kernel_header HEVC_ENC_PB_Widi; 2131 gen9_hevc_enc_kernel_header HEVC_ENC_BRC_Blockcopy; 2132 gen9_hevc_enc_kernel_header HEVC_ENC_DS_Combined; 2133 gen9_hevc_enc_kernel_header HEVC_ENC_P_MB; 2134 gen9_hevc_enc_kernel_header HEVC_ENC_P_Widi; 2135 } gen9_hevc_enc_kernels_header_bxt; 2136 2137 typedef enum _GEN9_HEVC_ENC_MBENC_KRNIDX { 2138 GEN9_HEVC_ENC_MBENC_2xSCALING = 0, 2139 GEN9_HEVC_ENC_MBENC_32x32MD, 2140 GEN9_HEVC_ENC_MBENC_16x16SAD, 2141 GEN9_HEVC_ENC_MBENC_16x16MD, 2142 GEN9_HEVC_ENC_MBENC_8x8PU, 2143 GEN9_HEVC_ENC_MBENC_8x8FMODE, 2144 GEN9_HEVC_ENC_MBENC_32x32INTRACHECK, 2145 GEN9_HEVC_ENC_MBENC_BENC, 2146 GEN9_HEVC_ENC_MBENC_BPAK, 2147 GEN9_HEVC_ENC_MBENC_WIDI, 2148 GEN9_HEVC_ENC_MBENC_NUM, 2149 GEN9_HEVC_ENC_MBENC_DS_COMBINED = GEN9_HEVC_ENC_MBENC_NUM, 2150 GEN95_HEVC_ENC_MBENC_NUM_KBL, 2151 GEN9_HEVC_MBENC_PENC = GEN95_HEVC_ENC_MBENC_NUM_KBL, 2152 GEN9_HEVC_MBENC_P_WIDI, 2153 GEN9_HEVC_MBENC_NUM_BXT, 2154 GEN8_HEVC_ENC_MBENC_TOTAL_NUM = GEN9_HEVC_MBENC_NUM_BXT 2155 } GEN9_HEVC_ENC_MBENC_KRNIDX; 2156 2157 typedef enum _GEN9_HEVC_ENC_BRC_KRNIDX { 2158 GEN9_HEVC_ENC_BRC_COARSE_INTRA = 0, 2159 GEN9_HEVC_ENC_BRC_INIT, 2160 GEN9_HEVC_ENC_BRC_RESET, 2161 GEN9_HEVC_ENC_BRC_FRAME_UPDATE, 2162 GEN9_HEVC_ENC_BRC_LCU_UPDATE, 2163 GEN9_HEVC_ENC_BRC_NUM 2164 } GEN9_HEVC_ENC_BRC_KRNIDX; 2165 2166 typedef enum _GEN9_ENC_ENC_OPERATION { 2167 GEN9_ENC_SCALING4X = 0, 2168 GEN9_ENC_SCALING2X, 2169 GEN9_ENC_ME, 2170 GEN9_ENC_BRC, 2171 GEN9_ENC_MBENC, 2172 GEN9_ENC_MBENC_WIDI, 2173 GEN9_ENC_RESETVLINESTRIDE, 2174 GEN9_ENC_MC, 2175 GEN9_ENC_MBPAK, 2176 GEN9_ENC_DEBLOCK, 2177 GEN9_ENC_PREPROC, 2178 GEN9_ENC_VDENC_ME, 2179 GEN9_ENC_WP, 2180 GEN9_ENC_SFD, 2181 GEN9_ENC_MBENC_I_LUMA, 2182 GEN9_ENC_MPU, 2183 GEN9_ENC_TPU, 2184 GEN9_ENC_SCALING_CONVERSION, 2185 GEN9_ENC_DYS 2186 } GEN9_ENC_OPERATION; 2187 2188 #endif 2189