1 /*
2 * Copyright © 2006-2019 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
25 #ifndef _INTEL_DISPLAY_H_
26 #define _INTEL_DISPLAY_H_
27
28 #include <drm/drm_util.h>
29
30 #define drm_i915_private inteldrm_softc
31
32 #include "i915_reg_defs.h"
33 #include "intel_display_limits.h"
34
35 enum drm_scaling_filter;
36 struct dpll;
37 struct drm_atomic_state;
38 struct drm_connector;
39 struct drm_device;
40 struct drm_display_mode;
41 struct drm_encoder;
42 struct drm_file;
43 struct drm_format_info;
44 struct drm_framebuffer;
45 struct drm_i915_gem_object;
46 struct drm_i915_private;
47 struct drm_mode_fb_cmd2;
48 struct drm_modeset_acquire_ctx;
49 struct drm_plane;
50 struct drm_plane_state;
51 struct i915_address_space;
52 struct i915_gtt_view;
53 struct intel_atomic_state;
54 struct intel_crtc;
55 struct intel_crtc_state;
56 struct intel_digital_port;
57 struct intel_dp;
58 struct intel_encoder;
59 struct intel_initial_plane_config;
60 struct intel_link_m_n;
61 struct intel_plane;
62 struct intel_plane_state;
63 struct intel_power_domain_mask;
64 struct intel_remapped_info;
65 struct intel_rotation_info;
66 struct pci_dev;
67 struct work_struct;
68
69
70 #define pipe_name(p) ((p) + 'A')
71
transcoder_name(enum transcoder transcoder)72 static inline const char *transcoder_name(enum transcoder transcoder)
73 {
74 switch (transcoder) {
75 case TRANSCODER_A:
76 return "A";
77 case TRANSCODER_B:
78 return "B";
79 case TRANSCODER_C:
80 return "C";
81 case TRANSCODER_D:
82 return "D";
83 case TRANSCODER_EDP:
84 return "EDP";
85 case TRANSCODER_DSI_A:
86 return "DSI A";
87 case TRANSCODER_DSI_C:
88 return "DSI C";
89 default:
90 return "<invalid>";
91 }
92 }
93
transcoder_is_dsi(enum transcoder transcoder)94 static inline bool transcoder_is_dsi(enum transcoder transcoder)
95 {
96 return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
97 }
98
99 /*
100 * Global legacy plane identifier. Valid only for primary/sprite
101 * planes on pre-g4x, and only for primary planes on g4x-bdw.
102 */
103 enum i9xx_plane_id {
104 PLANE_A,
105 PLANE_B,
106 PLANE_C,
107 };
108
109 #define plane_name(p) ((p) + 'A')
110 #define sprite_name(p, s) ((p) * DISPLAY_RUNTIME_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
111
112 #define for_each_plane_id_on_crtc(__crtc, __p) \
113 for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
114 for_each_if((__crtc)->plane_ids_mask & BIT(__p))
115
116 #define for_each_dbuf_slice(__dev_priv, __slice) \
117 for ((__slice) = DBUF_S1; (__slice) < I915_MAX_DBUF_SLICES; (__slice)++) \
118 for_each_if(DISPLAY_INFO(__dev_priv)->dbuf.slice_mask & BIT(__slice))
119
120 #define for_each_dbuf_slice_in_mask(__dev_priv, __slice, __mask) \
121 for_each_dbuf_slice((__dev_priv), (__slice)) \
122 for_each_if((__mask) & BIT(__slice))
123
124 #define port_name(p) ((p) + 'A')
125
126 /*
127 * Ports identifier referenced from other drivers.
128 * Expected to remain stable over time
129 */
port_identifier(enum port port)130 static inline const char *port_identifier(enum port port)
131 {
132 switch (port) {
133 case PORT_A:
134 return "Port A";
135 case PORT_B:
136 return "Port B";
137 case PORT_C:
138 return "Port C";
139 case PORT_D:
140 return "Port D";
141 case PORT_E:
142 return "Port E";
143 case PORT_F:
144 return "Port F";
145 case PORT_G:
146 return "Port G";
147 case PORT_H:
148 return "Port H";
149 case PORT_I:
150 return "Port I";
151 default:
152 return "<invalid>";
153 }
154 }
155
156 enum tc_port {
157 TC_PORT_NONE = -1,
158
159 TC_PORT_1 = 0,
160 TC_PORT_2,
161 TC_PORT_3,
162 TC_PORT_4,
163 TC_PORT_5,
164 TC_PORT_6,
165
166 I915_MAX_TC_PORTS
167 };
168
169 enum aux_ch {
170 AUX_CH_NONE = -1,
171
172 AUX_CH_A,
173 AUX_CH_B,
174 AUX_CH_C,
175 AUX_CH_D,
176 AUX_CH_E, /* ICL+ */
177 AUX_CH_F,
178 AUX_CH_G,
179 AUX_CH_H,
180 AUX_CH_I,
181
182 /* tgl+ */
183 AUX_CH_USBC1 = AUX_CH_D,
184 AUX_CH_USBC2,
185 AUX_CH_USBC3,
186 AUX_CH_USBC4,
187 AUX_CH_USBC5,
188 AUX_CH_USBC6,
189
190 /* XE_LPD repositions D/E offsets and bitfields */
191 AUX_CH_D_XELPD = AUX_CH_USBC5,
192 AUX_CH_E_XELPD,
193 };
194
195 #define aux_ch_name(a) ((a) + 'A')
196
197 enum phy {
198 PHY_NONE = -1,
199
200 PHY_A = 0,
201 PHY_B,
202 PHY_C,
203 PHY_D,
204 PHY_E,
205 PHY_F,
206 PHY_G,
207 PHY_H,
208 PHY_I,
209
210 I915_MAX_PHYS
211 };
212
213 #define phy_name(a) ((a) + 'A')
214
215 enum phy_fia {
216 FIA1,
217 FIA2,
218 FIA3,
219 };
220
221 #define for_each_hpd_pin(__pin) \
222 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
223
224 #define for_each_pipe(__dev_priv, __p) \
225 for ((__p) = 0; (__p) < I915_MAX_PIPES; (__p)++) \
226 for_each_if(DISPLAY_RUNTIME_INFO(__dev_priv)->pipe_mask & BIT(__p))
227
228 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
229 for_each_pipe(__dev_priv, __p) \
230 for_each_if((__mask) & BIT(__p))
231
232 #define for_each_cpu_transcoder(__dev_priv, __t) \
233 for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++) \
234 for_each_if (DISPLAY_RUNTIME_INFO(__dev_priv)->cpu_transcoder_mask & BIT(__t))
235
236 #define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \
237 for_each_cpu_transcoder(__dev_priv, __t) \
238 for_each_if ((__mask) & BIT(__t))
239
240 #define for_each_sprite(__dev_priv, __p, __s) \
241 for ((__s) = 0; \
242 (__s) < DISPLAY_RUNTIME_INFO(__dev_priv)->num_sprites[(__p)]; \
243 (__s)++)
244
245 #define for_each_port(__port) \
246 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)
247
248 #define for_each_port_masked(__port, __ports_mask) \
249 for_each_port(__port) \
250 for_each_if((__ports_mask) & BIT(__port))
251
252 #define for_each_phy_masked(__phy, __phys_mask) \
253 for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \
254 for_each_if((__phys_mask) & BIT(__phy))
255
256 #define for_each_crtc(dev, crtc) \
257 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
258
259 #define for_each_intel_plane(dev, intel_plane) \
260 list_for_each_entry(intel_plane, \
261 &(dev)->mode_config.plane_list, \
262 base.head)
263
264 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \
265 list_for_each_entry(intel_plane, \
266 &(dev)->mode_config.plane_list, \
267 base.head) \
268 for_each_if((plane_mask) & \
269 drm_plane_mask(&intel_plane->base))
270
271 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
272 list_for_each_entry(intel_plane, \
273 &(dev)->mode_config.plane_list, \
274 base.head) \
275 for_each_if((intel_plane)->pipe == (intel_crtc)->pipe)
276
277 #define for_each_intel_crtc(dev, intel_crtc) \
278 list_for_each_entry(intel_crtc, \
279 &(dev)->mode_config.crtc_list, \
280 base.head)
281
282 #define for_each_intel_crtc_in_pipe_mask(dev, intel_crtc, pipe_mask) \
283 list_for_each_entry(intel_crtc, \
284 &(dev)->mode_config.crtc_list, \
285 base.head) \
286 for_each_if((pipe_mask) & BIT(intel_crtc->pipe))
287
288 #define for_each_intel_encoder(dev, intel_encoder) \
289 list_for_each_entry(intel_encoder, \
290 &(dev)->mode_config.encoder_list, \
291 base.head)
292
293 #define for_each_intel_encoder_mask(dev, intel_encoder, encoder_mask) \
294 list_for_each_entry(intel_encoder, \
295 &(dev)->mode_config.encoder_list, \
296 base.head) \
297 for_each_if((encoder_mask) & \
298 drm_encoder_mask(&intel_encoder->base))
299
300 #define for_each_intel_encoder_mask_with_psr(dev, intel_encoder, encoder_mask) \
301 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
302 for_each_if(((encoder_mask) & drm_encoder_mask(&(intel_encoder)->base)) && \
303 intel_encoder_can_psr(intel_encoder))
304
305 #define for_each_intel_dp(dev, intel_encoder) \
306 for_each_intel_encoder(dev, intel_encoder) \
307 for_each_if(intel_encoder_is_dp(intel_encoder))
308
309 #define for_each_intel_encoder_with_psr(dev, intel_encoder) \
310 for_each_intel_encoder((dev), (intel_encoder)) \
311 for_each_if(intel_encoder_can_psr(intel_encoder))
312
313 #define for_each_intel_connector_iter(intel_connector, iter) \
314 while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter))))
315
316 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
317 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
318 for_each_if((intel_encoder)->base.crtc == (__crtc))
319
320 #define for_each_old_intel_plane_in_state(__state, plane, old_plane_state, __i) \
321 for ((__i) = 0; \
322 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
323 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
324 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), 1); \
325 (__i)++) \
326 for_each_if(plane)
327
328 #define for_each_old_intel_crtc_in_state(__state, crtc, old_crtc_state, __i) \
329 for ((__i) = 0; \
330 (__i) < (__state)->base.dev->mode_config.num_crtc && \
331 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
332 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), 1); \
333 (__i)++) \
334 for_each_if(crtc)
335
336 #define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \
337 for ((__i) = 0; \
338 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
339 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
340 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
341 (__i)++) \
342 for_each_if(plane)
343
344 #define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \
345 for ((__i) = 0; \
346 (__i) < (__state)->base.dev->mode_config.num_crtc && \
347 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
348 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
349 (__i)++) \
350 for_each_if(crtc)
351
352 #define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \
353 for ((__i) = 0; \
354 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
355 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
356 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \
357 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
358 (__i)++) \
359 for_each_if(plane)
360
361 #define for_each_oldnew_intel_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \
362 for ((__i) = 0; \
363 (__i) < (__state)->base.dev->mode_config.num_crtc && \
364 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
365 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
366 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
367 (__i)++) \
368 for_each_if(crtc)
369
370 #define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \
371 for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \
372 (__i) >= 0 && \
373 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
374 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
375 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
376 (__i)--) \
377 for_each_if(crtc)
378
379 #define intel_atomic_crtc_state_for_each_plane_state( \
380 plane, plane_state, \
381 crtc_state) \
382 for_each_intel_plane_mask(((crtc_state)->uapi.state->dev), (plane), \
383 ((crtc_state)->uapi.plane_mask)) \
384 for_each_if ((plane_state = \
385 to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state, &plane->base))))
386
387 #define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \
388 for ((__i) = 0; \
389 (__i) < (__state)->base.num_connector; \
390 (__i)++) \
391 for_each_if ((__state)->base.connectors[__i].ptr && \
392 ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \
393 (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))
394
395 int intel_atomic_check(struct drm_device *dev, struct drm_atomic_state *state);
396 int intel_atomic_add_affected_planes(struct intel_atomic_state *state,
397 struct intel_crtc *crtc);
398 u8 intel_calc_active_pipes(struct intel_atomic_state *state,
399 u8 active_pipes);
400 void intel_link_compute_m_n(u16 bpp, int nlanes,
401 int pixel_clock, int link_clock,
402 struct intel_link_m_n *m_n,
403 bool fec_enable);
404 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
405 u32 pixel_format, u64 modifier);
406 enum drm_mode_status
407 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
408 const struct drm_display_mode *mode,
409 bool bigjoiner);
410 enum drm_mode_status
411 intel_cpu_transcoder_mode_valid(struct drm_i915_private *i915,
412 const struct drm_display_mode *mode);
413 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
414 bool is_trans_port_sync_mode(const struct intel_crtc_state *state);
415 bool is_trans_port_sync_master(const struct intel_crtc_state *state);
416 bool intel_crtc_is_bigjoiner_slave(const struct intel_crtc_state *crtc_state);
417 bool intel_crtc_is_bigjoiner_master(const struct intel_crtc_state *crtc_state);
418 u8 intel_crtc_bigjoiner_slave_pipes(const struct intel_crtc_state *crtc_state);
419 struct intel_crtc *intel_master_crtc(const struct intel_crtc_state *crtc_state);
420 bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state);
421 bool intel_pipe_config_compare(const struct intel_crtc_state *current_config,
422 const struct intel_crtc_state *pipe_config,
423 bool fastset);
424
425 void intel_plane_destroy(struct drm_plane *plane);
426 void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
427 void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state);
428 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state);
429 void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state);
430 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
431 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
432 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
433 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
434 const char *name, u32 reg, int ref_freq);
435 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
436 const char *name, u32 reg);
437 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
438 unsigned int intel_fb_xy_to_linear(int x, int y,
439 const struct intel_plane_state *state,
440 int plane);
441 void intel_add_fb_offsets(int *x, int *y,
442 const struct intel_plane_state *state, int plane);
443 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
444 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info);
445 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
446 void intel_encoder_destroy(struct drm_encoder *encoder);
447 struct drm_display_mode *
448 intel_encoder_current_mode(struct intel_encoder *encoder);
449 void intel_encoder_get_config(struct intel_encoder *encoder,
450 struct intel_crtc_state *crtc_state);
451 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy);
452 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy);
453 bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy);
454 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
455 enum port port);
456 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
457 struct drm_file *file_priv);
458
459 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp);
460 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
461 struct intel_digital_port *dig_port,
462 unsigned int expected_mask);
463 struct drm_framebuffer *
464 intel_framebuffer_create(struct drm_i915_gem_object *obj,
465 struct drm_mode_fb_cmd2 *mode_cmd);
466
467 bool intel_fuzzy_clock_check(int clock1, int clock2);
468
469 void intel_zero_m_n(struct intel_link_m_n *m_n);
470 void intel_set_m_n(struct drm_i915_private *i915,
471 const struct intel_link_m_n *m_n,
472 i915_reg_t data_m_reg, i915_reg_t data_n_reg,
473 i915_reg_t link_m_reg, i915_reg_t link_n_reg);
474 void intel_get_m_n(struct drm_i915_private *i915,
475 struct intel_link_m_n *m_n,
476 i915_reg_t data_m_reg, i915_reg_t data_n_reg,
477 i915_reg_t link_m_reg, i915_reg_t link_n_reg);
478 bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
479 enum transcoder transcoder);
480 void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
481 enum transcoder cpu_transcoder,
482 const struct intel_link_m_n *m_n);
483 void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc,
484 enum transcoder cpu_transcoder,
485 const struct intel_link_m_n *m_n);
486 void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
487 enum transcoder cpu_transcoder,
488 struct intel_link_m_n *m_n);
489 void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
490 enum transcoder cpu_transcoder,
491 struct intel_link_m_n *m_n);
492 void i9xx_crtc_clock_get(struct intel_crtc *crtc,
493 struct intel_crtc_state *pipe_config);
494 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
495 int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config);
496 enum intel_display_power_domain intel_port_to_power_domain(struct intel_digital_port *dig_port);
497 enum intel_display_power_domain
498 intel_aux_power_domain(struct intel_digital_port *dig_port);
499 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
500 struct intel_crtc_state *crtc_state);
501 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state);
502
503 int bdw_get_pipe_misc_bpp(struct intel_crtc *crtc);
504 unsigned int intel_plane_fence_y_offset(const struct intel_plane_state *plane_state);
505
506 bool intel_plane_uses_fence(const struct intel_plane_state *plane_state);
507
508 struct intel_encoder *
509 intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
510 const struct intel_crtc_state *crtc_state);
511 void intel_plane_disable_noatomic(struct intel_crtc *crtc,
512 struct intel_plane *plane);
513 void intel_set_plane_visible(struct intel_crtc_state *crtc_state,
514 struct intel_plane_state *plane_state,
515 bool visible);
516 void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state);
517
518 void intel_update_watermarks(struct drm_i915_private *i915);
519
520 /* modesetting */
521 int intel_modeset_all_pipes(struct intel_atomic_state *state,
522 const char *reason);
523 void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state,
524 struct intel_power_domain_mask *old_domains);
525 void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc,
526 struct intel_power_domain_mask *domains);
527
528 /* interface for intel_display_driver.c */
529 void intel_setup_outputs(struct drm_i915_private *i915);
530 int intel_initial_commit(struct drm_device *dev);
531 void intel_panel_sanitize_ssc(struct drm_i915_private *i915);
532 void intel_update_czclk(struct drm_i915_private *i915);
533 void intel_atomic_helper_free_state_worker(struct work_struct *work);
534 enum drm_mode_status intel_mode_valid(struct drm_device *dev,
535 const struct drm_display_mode *mode);
536 int intel_atomic_commit(struct drm_device *dev, struct drm_atomic_state *_state,
537 bool nonblock);
538
539 void intel_hpd_poll_fini(struct drm_i915_private *i915);
540
541 /* modesetting asserts */
542 void assert_transcoder(struct drm_i915_private *dev_priv,
543 enum transcoder cpu_transcoder, bool state);
544 #define assert_transcoder_enabled(d, t) assert_transcoder(d, t, true)
545 #define assert_transcoder_disabled(d, t) assert_transcoder(d, t, false)
546
547 bool assert_port_valid(struct drm_i915_private *i915, enum port port);
548
549 /*
550 * Use I915_STATE_WARN(x) (rather than WARN() and WARN_ON()) for hw state sanity
551 * checks to check for unexpected conditions which may not necessarily be a user
552 * visible problem. This will either WARN() or DRM_ERROR() depending on the
553 * verbose_state_checks module param, to enable distros and users to tailor
554 * their preferred amount of i915 abrt spam.
555 */
556 #define I915_STATE_WARN(__i915, condition, format...) ({ \
557 struct drm_device *drm = &(__i915)->drm; \
558 int __ret_warn_on = !!(condition); \
559 if (unlikely(__ret_warn_on)) \
560 if (!drm_WARN(drm, i915_modparams.verbose_state_checks, format)) \
561 drm_err(drm, format); \
562 unlikely(__ret_warn_on); \
563 })
564
565 bool intel_scanout_needs_vtd_wa(struct drm_i915_private *i915);
566
567 #endif
568