1 /* $OpenBSD: fpu_explode.c,v 1.8 2024/03/29 21:08:10 miod Exp $ */
2 /* $NetBSD: fpu_explode.c,v 1.5 2000/08/03 18:32:08 eeh Exp $ */
3
4 /*
5 * Copyright (c) 1992, 1993
6 * The Regents of the University of California. All rights reserved.
7 *
8 * This software was developed by the Computer Systems Engineering group
9 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
10 * contributed to Berkeley.
11 *
12 * All advertising materials mentioning features or use of this software
13 * must display the following acknowledgement:
14 * This product includes software developed by the University of
15 * California, Lawrence Berkeley Laboratory.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
19 * are met:
20 * 1. Redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer.
22 * 2. Redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution.
25 * 3. Neither the name of the University nor the names of its contributors
26 * may be used to endorse or promote products derived from this software
27 * without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
30 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
31 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
32 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
33 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
35 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
37 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
38 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
39 * SUCH DAMAGE.
40 *
41 * @(#)fpu_explode.c 8.1 (Berkeley) 6/11/93
42 */
43
44 /*
45 * FPU subroutines: `explode' the machine's `packed binary' format numbers
46 * into our internal format.
47 */
48
49 #include <sys/types.h>
50 #include <sys/systm.h>
51
52 #include <machine/fsr.h>
53 #include <machine/ieee.h>
54 #include <machine/instr.h>
55 #include <machine/reg.h>
56
57 #include <sparc64/fpu/fpu_arith.h>
58 #include <sparc64/fpu/fpu_emu.h>
59 #include <sparc64/fpu/fpu_extern.h>
60
61 /*
62 * N.B.: in all of the following, we assume the FP format is
63 *
64 * ---------------------------
65 * | s | exponent | fraction |
66 * ---------------------------
67 *
68 * (which represents -1**s * 1.fraction * 2**exponent), so that the
69 * sign bit is way at the top (bit 31), the exponent is next, and
70 * then the remaining bits mark the fraction. A zero exponent means
71 * zero or denormalized (0.fraction rather than 1.fraction), and the
72 * maximum possible exponent, 2bias+1, signals inf (fraction==0) or NaN.
73 *
74 * Since the sign bit is always the topmost bit---this holds even for
75 * integers---we set that outside all the *tof functions. Each function
76 * returns the class code for the new number (but note that we use
77 * FPC_QNAN for all NaNs; fpu_explode will fix this if appropriate).
78 */
79
80 /*
81 * int -> fpn.
82 */
83 int
fpu_itof(struct fpn * fp,u_int i)84 fpu_itof(struct fpn *fp, u_int i)
85 {
86
87 if (i == 0)
88 return (FPC_ZERO);
89 /*
90 * The value FP_1 represents 2^FP_LG, so set the exponent
91 * there and let normalization fix it up. Convert negative
92 * numbers to sign-and-magnitude. Note that this relies on
93 * fpu_norm()'s handling of `supernormals'; see fpu_subr.c.
94 */
95 fp->fp_exp = FP_LG;
96 fp->fp_mant[0] = (fp->fp_sign && (int)i < 0) ? -i : i;
97 fp->fp_mant[1] = 0;
98 fp->fp_mant[2] = 0;
99 fp->fp_mant[3] = 0;
100 fpu_norm(fp);
101 return (FPC_NUM);
102 }
103
104 /*
105 * 64-bit int -> fpn.
106 */
107 int
fpu_xtof(struct fpn * fp,u_int64_t i)108 fpu_xtof(struct fpn *fp, u_int64_t i)
109 {
110 if (i == 0)
111 return (FPC_ZERO);
112
113 /*
114 * The value FP_1 represents 2^FP_LG, so set the exponent
115 * there and let normalization fix it up. Convert negative
116 * numbers to sign-and-magnitude. Note that this relies on
117 * fpu_norm()'s handling of `supernormals'; see fpu_subr.c.
118 */
119 fp->fp_exp = FP_LG2;
120 i = (fp->fp_sign && (int64_t)i < 0) ? -i : i;
121 fp->fp_mant[0] = (i >> 32) & 0xffffffff;
122 fp->fp_mant[1] = (i >> 0) & 0xffffffff;
123 fp->fp_mant[2] = 0;
124 fp->fp_mant[3] = 0;
125 fpu_norm(fp);
126 return (FPC_NUM);
127 }
128
129 #define mask(nbits) ((1L << (nbits)) - 1)
130
131 /*
132 * All external floating formats convert to internal in the same manner,
133 * as defined here. Note that only normals get an implied 1.0 inserted.
134 */
135 #define FP_TOF(exp, expbias, allfrac, f0, f1, f2, f3) \
136 if (exp == 0) { \
137 if (allfrac == 0) \
138 return (FPC_ZERO); \
139 fp->fp_exp = 1 - expbias; \
140 fp->fp_mant[0] = f0; \
141 fp->fp_mant[1] = f1; \
142 fp->fp_mant[2] = f2; \
143 fp->fp_mant[3] = f3; \
144 fpu_norm(fp); \
145 return (FPC_NUM); \
146 } \
147 if (exp == (2 * expbias + 1)) { \
148 if (allfrac == 0) \
149 return (FPC_INF); \
150 fp->fp_mant[0] = f0; \
151 fp->fp_mant[1] = f1; \
152 fp->fp_mant[2] = f2; \
153 fp->fp_mant[3] = f3; \
154 return (FPC_QNAN); \
155 } \
156 fp->fp_exp = exp - expbias; \
157 fp->fp_mant[0] = FP_1 | f0; \
158 fp->fp_mant[1] = f1; \
159 fp->fp_mant[2] = f2; \
160 fp->fp_mant[3] = f3; \
161 return (FPC_NUM)
162
163 /*
164 * 32-bit single precision -> fpn.
165 * We assume a single occupies at most (64-FP_LG) bits in the internal
166 * format: i.e., needs at most fp_mant[0] and fp_mant[1].
167 */
168 int
fpu_stof(struct fpn * fp,u_int i)169 fpu_stof(struct fpn *fp, u_int i)
170 {
171 int exp;
172 u_int frac, f0, f1;
173 #define SNG_SHIFT (SNG_FRACBITS - FP_LG)
174
175 exp = (i >> (32 - 1 - SNG_EXPBITS)) & mask(SNG_EXPBITS);
176 frac = i & mask(SNG_FRACBITS);
177 f0 = frac >> SNG_SHIFT;
178 f1 = frac << (32 - SNG_SHIFT);
179 FP_TOF(exp, SNG_EXP_BIAS, frac, f0, f1, 0, 0);
180 }
181
182 /*
183 * 64-bit double -> fpn.
184 * We assume this uses at most (96-FP_LG) bits.
185 */
186 int
fpu_dtof(struct fpn * fp,u_int i,u_int j)187 fpu_dtof(struct fpn *fp, u_int i, u_int j)
188 {
189 int exp;
190 u_int frac, f0, f1, f2;
191 #define DBL_SHIFT (DBL_FRACBITS - 32 - FP_LG)
192
193 exp = (i >> (32 - 1 - DBL_EXPBITS)) & mask(DBL_EXPBITS);
194 frac = i & mask(DBL_FRACBITS - 32);
195 f0 = frac >> DBL_SHIFT;
196 f1 = (frac << (32 - DBL_SHIFT)) | (j >> DBL_SHIFT);
197 f2 = j << (32 - DBL_SHIFT);
198 frac |= j;
199 FP_TOF(exp, DBL_EXP_BIAS, frac, f0, f1, f2, 0);
200 }
201
202 /*
203 * 128-bit extended -> fpn.
204 */
205 int
fpu_qtof(struct fpn * fp,u_int i,u_int j,u_int k,u_int l)206 fpu_qtof(struct fpn *fp, u_int i, u_int j, u_int k, u_int l)
207 {
208 int exp;
209 u_int frac, f0, f1, f2, f3;
210 #define EXT_SHIFT (-(EXT_FRACBITS - 3 * 32 - FP_LG)) /* left shift! */
211
212 /*
213 * Note that ext and fpn `line up', hence no shifting needed.
214 */
215 exp = (i >> (32 - 1 - EXT_EXPBITS)) & mask(EXT_EXPBITS);
216 frac = i & mask(EXT_FRACBITS - 3 * 32);
217 f0 = (frac << EXT_SHIFT) | (j >> (32 - EXT_SHIFT));
218 f1 = (j << EXT_SHIFT) | (k >> (32 - EXT_SHIFT));
219 f2 = (k << EXT_SHIFT) | (l >> (32 - EXT_SHIFT));
220 f3 = l << EXT_SHIFT;
221 frac |= j | k | l;
222 FP_TOF(exp, EXT_EXP_BIAS, frac, f0, f1, f2, f3);
223 }
224
225 /*
226 * Explode the contents of a register / regpair / regquad.
227 * If the input is a signalling NaN, an NV (invalid) exception
228 * will be set. (Note that nothing but NV can occur until ALU
229 * operations are performed.)
230 */
231 void
fpu_explode(struct fpemu * fe,struct fpn * fp,int type,int reg)232 fpu_explode(struct fpemu *fe, struct fpn *fp, int type, int reg)
233 {
234 u_int s, *space;
235 u_int64_t l, *xspace;
236
237 xspace = (u_int64_t *)&fe->fe_fpstate->fs_regs[reg & ~1];
238 l = xspace[0];
239 space = &fe->fe_fpstate->fs_regs[reg];
240 s = space[0];
241 fp->fp_sign = (type == FTYPE_LNG) ? l >> 63 : s >> 31;
242 fp->fp_sticky = 0;
243 DPRINTF(FPE_INSN, ("fpu_explode: "));
244 switch (type) {
245 case FTYPE_LNG:
246 DPRINTF(FPE_INSN, ("LNG: %llx", l));
247 s = fpu_xtof(fp, l);
248 break;
249
250 case FTYPE_INT:
251 DPRINTF(FPE_INSN, ("INT: %x", s));
252 s = fpu_itof(fp, s);
253 break;
254
255 case FTYPE_SNG:
256 DPRINTF(FPE_INSN, ("SNG: %x", s));
257 s = fpu_stof(fp, s);
258 break;
259
260 case FTYPE_DBL:
261 DPRINTF(FPE_INSN, ("DBL: %x %x", s, space[1]));
262 s = fpu_dtof(fp, s, space[1]);
263 break;
264
265 case FTYPE_EXT:
266 DPRINTF(FPE_INSN, ("EXT: %x %x %x %x", s, space[1],
267 space[2], space[3]));
268 s = fpu_qtof(fp, s, space[1], space[2], space[3]);
269 break;
270
271 default:
272 panic("fpu_explode");
273 }
274 DPRINTF(FPE_INSN, ("\n"));
275
276 if (s == FPC_QNAN && (fp->fp_mant[0] & FP_QUIETBIT) == 0) {
277 /*
278 * Input is a signalling NaN. All operations that return
279 * an input NaN operand put it through a ``NaN conversion'',
280 * which basically just means ``turn on the quiet bit''.
281 * We do this here so that all NaNs internally look quiet
282 * (we can tell signalling ones by their class).
283 */
284 fp->fp_mant[0] |= FP_QUIETBIT;
285 fe->fe_cx = FSR_NV; /* assert invalid operand */
286 s = FPC_SNAN;
287 }
288 fp->fp_class = s;
289 DPRINTF(FPE_REG, ("fpu_explode: %%%c%d => ", (type == FTYPE_LNG) ? 'x' :
290 ((type == FTYPE_INT) ? 'i' :
291 ((type == FTYPE_SNG) ? 's' :
292 ((type == FTYPE_DBL) ? 'd' :
293 ((type == FTYPE_EXT) ? 'q' : '?')))),
294 reg));
295 DUMPFPN(FPE_REG, fp);
296 DPRINTF(FPE_REG, ("\n"));
297 }
298