1 /*
2 * Copyright � 2011 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24 #ifdef HAVE_CONFIG_H
25 #include "config.h"
26 #endif
27
28 #include <string.h>
29
30 #include "intel.h"
31 #include "intel_uxa.h"
32 #include "i965_reg.h"
33 #include "brw_defines.h"
34
35 void
gen6_upload_invariant_states(intel_screen_private * intel)36 gen6_upload_invariant_states(intel_screen_private *intel)
37 {
38 Bool ivb = INTEL_INFO(intel)->gen >= 070;
39
40 OUT_BATCH(BRW_PIPE_CONTROL | (4 - 2));
41 OUT_BATCH(BRW_PIPE_CONTROL_IS_FLUSH |
42 BRW_PIPE_CONTROL_WC_FLUSH |
43 BRW_PIPE_CONTROL_DEPTH_CACHE_FLUSH |
44 BRW_PIPE_CONTROL_NOWRITE);
45 OUT_BATCH(0); /* write address */
46 OUT_BATCH(0); /* write data */
47
48 OUT_BATCH(NEW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
49
50 OUT_BATCH(GEN6_3DSTATE_MULTISAMPLE | ((ivb ? 4 : 3) - 2));
51 OUT_BATCH(GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_CENTER |
52 GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_1); /* 1 sample/pixel */
53 OUT_BATCH(0);
54 if (ivb)
55 OUT_BATCH(0);
56
57 OUT_BATCH(GEN6_3DSTATE_SAMPLE_MASK | (2 - 2));
58 OUT_BATCH(1);
59
60 /* Set system instruction pointer */
61 OUT_BATCH(BRW_STATE_SIP | 0);
62 OUT_BATCH(0);
63 }
64
65 void
gen6_upload_viewport_state_pointers(intel_screen_private * intel,drm_intel_bo * cc_vp_bo)66 gen6_upload_viewport_state_pointers(intel_screen_private *intel,
67 drm_intel_bo *cc_vp_bo)
68 {
69 OUT_BATCH(GEN6_3DSTATE_VIEWPORT_STATE_POINTERS |
70 GEN6_3DSTATE_VIEWPORT_STATE_MODIFY_CC |
71 (4 - 2));
72 OUT_BATCH(0);
73 OUT_BATCH(0);
74 OUT_RELOC(cc_vp_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
75 }
76
77 void
gen7_upload_viewport_state_pointers(intel_screen_private * intel,drm_intel_bo * cc_vp_bo)78 gen7_upload_viewport_state_pointers(intel_screen_private *intel,
79 drm_intel_bo *cc_vp_bo)
80 {
81 OUT_BATCH(GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC | (2 - 2));
82 OUT_RELOC(cc_vp_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
83
84 OUT_BATCH(GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CL | (2 - 2));
85 OUT_BATCH(0);
86 }
87
88 void
gen6_upload_urb(intel_screen_private * intel)89 gen6_upload_urb(intel_screen_private *intel)
90 {
91 OUT_BATCH(GEN6_3DSTATE_URB | (3 - 2));
92 OUT_BATCH(((1 - 1) << GEN6_3DSTATE_URB_VS_SIZE_SHIFT) |
93 (24 << GEN6_3DSTATE_URB_VS_ENTRIES_SHIFT)); /* at least 24 on GEN6 */
94 OUT_BATCH((0 << GEN6_3DSTATE_URB_GS_SIZE_SHIFT) |
95 (0 << GEN6_3DSTATE_URB_GS_ENTRIES_SHIFT)); /* no GS thread */
96 }
97
98 /*
99 * URB layout on GEN7
100 * ----------------------------------------
101 * | PS Push Constants (8KB) | VS entries |
102 * ----------------------------------------
103 */
104 void
gen7_upload_urb(intel_screen_private * intel)105 gen7_upload_urb(intel_screen_private *intel)
106 {
107 unsigned int num_urb_entries = 32;
108
109 if (IS_HSW(intel))
110 num_urb_entries = 64;
111
112 OUT_BATCH(GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS | (2 - 2));
113 OUT_BATCH(8); /* in 1KBs */
114
115 OUT_BATCH(GEN7_3DSTATE_URB_VS | (2 - 2));
116 OUT_BATCH(
117 (num_urb_entries << GEN7_URB_ENTRY_NUMBER_SHIFT) |
118 (2 - 1) << GEN7_URB_ENTRY_SIZE_SHIFT |
119 (1 << GEN7_URB_STARTING_ADDRESS_SHIFT));
120
121 OUT_BATCH(GEN7_3DSTATE_URB_GS | (2 - 2));
122 OUT_BATCH((0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
123 (1 << GEN7_URB_STARTING_ADDRESS_SHIFT));
124
125 OUT_BATCH(GEN7_3DSTATE_URB_HS | (2 - 2));
126 OUT_BATCH((0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
127 (2 << GEN7_URB_STARTING_ADDRESS_SHIFT));
128
129 OUT_BATCH(GEN7_3DSTATE_URB_DS | (2 - 2));
130 OUT_BATCH((0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
131 (2 << GEN7_URB_STARTING_ADDRESS_SHIFT));
132 }
133
134 void
gen6_upload_cc_state_pointers(intel_screen_private * intel,drm_intel_bo * blend_bo,drm_intel_bo * cc_bo,drm_intel_bo * depth_stencil_bo,uint32_t blend_offset)135 gen6_upload_cc_state_pointers(intel_screen_private *intel,
136 drm_intel_bo *blend_bo,
137 drm_intel_bo *cc_bo,
138 drm_intel_bo *depth_stencil_bo,
139 uint32_t blend_offset)
140 {
141 OUT_BATCH(GEN6_3DSTATE_CC_STATE_POINTERS | (4 - 2));
142 if (blend_bo)
143 OUT_RELOC(blend_bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
144 blend_offset | 1);
145 else
146 OUT_BATCH(0);
147
148 if (depth_stencil_bo)
149 OUT_RELOC(depth_stencil_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
150 else
151 OUT_BATCH(0);
152
153 if (cc_bo)
154 OUT_RELOC(cc_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
155 else
156 OUT_BATCH(0);
157 }
158
159 void
gen7_upload_cc_state_pointers(intel_screen_private * intel,drm_intel_bo * blend_bo,drm_intel_bo * cc_bo,drm_intel_bo * depth_stencil_bo,uint32_t blend_offset)160 gen7_upload_cc_state_pointers(intel_screen_private *intel,
161 drm_intel_bo *blend_bo,
162 drm_intel_bo *cc_bo,
163 drm_intel_bo *depth_stencil_bo,
164 uint32_t blend_offset)
165 {
166 OUT_BATCH(GEN7_3DSTATE_BLEND_STATE_POINTERS | (2 - 2));
167 if (blend_bo)
168 OUT_RELOC(blend_bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
169 blend_offset | 1);
170 else
171 OUT_BATCH(0);
172
173 OUT_BATCH(GEN6_3DSTATE_CC_STATE_POINTERS | (2 - 2));
174 if (cc_bo)
175 OUT_RELOC(cc_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
176 else
177 OUT_BATCH(0);
178
179 OUT_BATCH(GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS | (2 - 2));
180 if (depth_stencil_bo)
181 OUT_RELOC(depth_stencil_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
182 else
183 OUT_BATCH(0);
184 }
185
186 void
gen6_upload_sampler_state_pointers(intel_screen_private * intel,drm_intel_bo * sampler_bo)187 gen6_upload_sampler_state_pointers(intel_screen_private *intel,
188 drm_intel_bo *sampler_bo)
189 {
190 OUT_BATCH(GEN6_3DSTATE_SAMPLER_STATE_POINTERS |
191 GEN6_3DSTATE_SAMPLER_STATE_MODIFY_PS |
192 (4 - 2));
193 OUT_BATCH(0); /* VS */
194 OUT_BATCH(0); /* GS */
195 OUT_RELOC(sampler_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
196 }
197
198 void
gen7_upload_sampler_state_pointers(intel_screen_private * intel,drm_intel_bo * sampler_bo)199 gen7_upload_sampler_state_pointers(intel_screen_private *intel,
200 drm_intel_bo *sampler_bo)
201 {
202 OUT_BATCH(GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS | (2 - 2));
203 OUT_RELOC(sampler_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
204 }
205
206 void
gen7_upload_bypass_states(intel_screen_private * intel)207 gen7_upload_bypass_states(intel_screen_private *intel)
208 {
209 /* bypass GS */
210 OUT_BATCH(GEN6_3DSTATE_CONSTANT_GS | (7 - 2));
211 OUT_BATCH(0);
212 OUT_BATCH(0);
213 OUT_BATCH(0);
214 OUT_BATCH(0);
215 OUT_BATCH(0);
216 OUT_BATCH(0);
217
218 OUT_BATCH(GEN6_3DSTATE_GS | (7 - 2));
219 OUT_BATCH(0); /* without GS kernel */
220 OUT_BATCH(0);
221 OUT_BATCH(0);
222 OUT_BATCH(0);
223 OUT_BATCH(0);
224 OUT_BATCH(0); /* pass-through */
225
226 OUT_BATCH(GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS | (2 - 2));
227 OUT_BATCH(0);
228
229 /* disable HS */
230 OUT_BATCH(GEN7_3DSTATE_CONSTANT_HS | (7 - 2));
231 OUT_BATCH(0);
232 OUT_BATCH(0);
233 OUT_BATCH(0);
234 OUT_BATCH(0);
235 OUT_BATCH(0);
236 OUT_BATCH(0);
237
238 OUT_BATCH(GEN7_3DSTATE_HS | (7 - 2));
239 OUT_BATCH(0);
240 OUT_BATCH(0);
241 OUT_BATCH(0);
242 OUT_BATCH(0);
243 OUT_BATCH(0);
244 OUT_BATCH(0);
245
246 OUT_BATCH(GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS | (2 - 2));
247 OUT_BATCH(0);
248
249 /* Disable TE */
250 OUT_BATCH(GEN7_3DSTATE_TE | (4 - 2));
251 OUT_BATCH(0);
252 OUT_BATCH(0);
253 OUT_BATCH(0);
254
255 /* Disable DS */
256 OUT_BATCH(GEN7_3DSTATE_CONSTANT_DS | (7 - 2));
257 OUT_BATCH(0);
258 OUT_BATCH(0);
259 OUT_BATCH(0);
260 OUT_BATCH(0);
261 OUT_BATCH(0);
262 OUT_BATCH(0);
263
264 OUT_BATCH(GEN7_3DSTATE_DS | (6 - 2));
265 OUT_BATCH(0);
266 OUT_BATCH(0);
267 OUT_BATCH(0);
268 OUT_BATCH(0);
269 OUT_BATCH(0);
270
271 OUT_BATCH(GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS | (2 - 2));
272 OUT_BATCH(0);
273
274 /* Disable STREAMOUT */
275 OUT_BATCH(GEN7_3DSTATE_STREAMOUT | (3 - 2));
276 OUT_BATCH(0);
277 OUT_BATCH(0);
278 }
279
280 void
gen6_upload_vs_state(intel_screen_private * intel)281 gen6_upload_vs_state(intel_screen_private *intel)
282 {
283 Bool ivb = INTEL_INFO(intel)->gen >= 070;
284 /* disable VS constant buffer */
285 OUT_BATCH(GEN6_3DSTATE_CONSTANT_VS | ((ivb ? 7 : 5) - 2));
286 OUT_BATCH(0);
287 OUT_BATCH(0);
288 OUT_BATCH(0);
289 OUT_BATCH(0);
290 if (ivb) {
291 OUT_BATCH(0);
292 OUT_BATCH(0);
293 }
294
295 OUT_BATCH(GEN6_3DSTATE_VS | (6 - 2));
296 OUT_BATCH(0); /* without VS kernel */
297 OUT_BATCH(0);
298 OUT_BATCH(0);
299 OUT_BATCH(0);
300 OUT_BATCH(0); /* pass-through */
301 }
302
303 void
gen6_upload_gs_state(intel_screen_private * intel)304 gen6_upload_gs_state(intel_screen_private *intel)
305 {
306 /* disable GS constant buffer */
307 OUT_BATCH(GEN6_3DSTATE_CONSTANT_GS | (5 - 2));
308 OUT_BATCH(0);
309 OUT_BATCH(0);
310 OUT_BATCH(0);
311 OUT_BATCH(0);
312
313 OUT_BATCH(GEN6_3DSTATE_GS | (7 - 2));
314 OUT_BATCH(0); /* without GS kernel */
315 OUT_BATCH(0);
316 OUT_BATCH(0);
317 OUT_BATCH(0);
318 OUT_BATCH(0);
319 OUT_BATCH(0); /* pass-through */
320 }
321
322 void
gen6_upload_clip_state(intel_screen_private * intel)323 gen6_upload_clip_state(intel_screen_private *intel)
324 {
325 OUT_BATCH(GEN6_3DSTATE_CLIP | (4 - 2));
326 OUT_BATCH(0);
327 OUT_BATCH(0); /* pass-through */
328 OUT_BATCH(0);
329 }
330
331 void
gen6_upload_sf_state(intel_screen_private * intel,int num_sf_outputs,int read_offset)332 gen6_upload_sf_state(intel_screen_private *intel,
333 int num_sf_outputs,
334 int read_offset)
335 {
336 OUT_BATCH(GEN6_3DSTATE_SF | (20 - 2));
337 OUT_BATCH((num_sf_outputs << GEN6_3DSTATE_SF_NUM_OUTPUTS_SHIFT) |
338 (1 << GEN6_3DSTATE_SF_URB_ENTRY_READ_LENGTH_SHIFT) |
339 (read_offset << GEN6_3DSTATE_SF_URB_ENTRY_READ_OFFSET_SHIFT));
340 OUT_BATCH(0);
341 OUT_BATCH(GEN6_3DSTATE_SF_CULL_NONE);
342 OUT_BATCH(2 << GEN6_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT); /* DW4 */
343 OUT_BATCH(0);
344 OUT_BATCH(0);
345 OUT_BATCH(0);
346 OUT_BATCH(0);
347 OUT_BATCH(0); /* DW9 */
348 OUT_BATCH(0);
349 OUT_BATCH(0);
350 OUT_BATCH(0);
351 OUT_BATCH(0);
352 OUT_BATCH(0); /* DW14 */
353 OUT_BATCH(0);
354 OUT_BATCH(0);
355 OUT_BATCH(0);
356 OUT_BATCH(0);
357 OUT_BATCH(0); /* DW19 */
358 }
359
360 void
gen7_upload_sf_state(intel_screen_private * intel,int num_sf_outputs,int read_offset)361 gen7_upload_sf_state(intel_screen_private *intel,
362 int num_sf_outputs,
363 int read_offset)
364 {
365 OUT_BATCH(GEN7_3DSTATE_SBE | (14 - 2));
366 OUT_BATCH((num_sf_outputs << GEN7_SBE_NUM_OUTPUTS_SHIFT) |
367 (1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT) |
368 (read_offset << GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT));
369 OUT_BATCH(0);
370 OUT_BATCH(0);
371 OUT_BATCH(0); /* DW4 */
372 OUT_BATCH(0);
373 OUT_BATCH(0);
374 OUT_BATCH(0);
375 OUT_BATCH(0);
376 OUT_BATCH(0); /* DW9 */
377 OUT_BATCH(0);
378 OUT_BATCH(0);
379 OUT_BATCH(0);
380 OUT_BATCH(0);
381
382 OUT_BATCH(GEN6_3DSTATE_SF | (7 - 2));
383 OUT_BATCH(0);
384 OUT_BATCH(GEN6_3DSTATE_SF_CULL_NONE);
385 OUT_BATCH(2 << GEN6_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT);
386 OUT_BATCH(0);
387 OUT_BATCH(0);
388 OUT_BATCH(0);
389 }
390
391 void
gen6_upload_binding_table(intel_screen_private * intel,uint32_t ps_binding_table_offset)392 gen6_upload_binding_table(intel_screen_private *intel,
393 uint32_t ps_binding_table_offset)
394 {
395 /* Binding table pointers */
396 OUT_BATCH(BRW_3DSTATE_BINDING_TABLE_POINTERS |
397 GEN6_3DSTATE_BINDING_TABLE_MODIFY_PS |
398 (4 - 2));
399 OUT_BATCH(0); /* VS */
400 OUT_BATCH(0); /* GS */
401 /* Only the PS uses the binding table */
402 OUT_BATCH(ps_binding_table_offset);
403 }
404
405 void
gen7_upload_binding_table(intel_screen_private * intel,uint32_t ps_binding_table_offset)406 gen7_upload_binding_table(intel_screen_private *intel,
407 uint32_t ps_binding_table_offset)
408 {
409 OUT_BATCH(GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS | (2 - 2));
410 OUT_BATCH(ps_binding_table_offset);
411 }
412
413 void
gen6_upload_depth_buffer_state(intel_screen_private * intel)414 gen6_upload_depth_buffer_state(intel_screen_private *intel)
415 {
416 OUT_BATCH(BRW_3DSTATE_DEPTH_BUFFER | (7 - 2));
417 OUT_BATCH((BRW_SURFACE_NULL << BRW_3DSTATE_DEPTH_BUFFER_TYPE_SHIFT) |
418 (BRW_DEPTHFORMAT_D32_FLOAT << BRW_3DSTATE_DEPTH_BUFFER_FORMAT_SHIFT));
419 OUT_BATCH(0);
420 OUT_BATCH(0);
421 OUT_BATCH(0);
422 OUT_BATCH(0);
423 OUT_BATCH(0);
424
425 OUT_BATCH(BRW_3DSTATE_CLEAR_PARAMS | (2 - 2));
426 OUT_BATCH(0);
427 }
428
429 void
gen7_upload_depth_buffer_state(intel_screen_private * intel)430 gen7_upload_depth_buffer_state(intel_screen_private *intel)
431 {
432 OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER | (7 - 2));
433 OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT << 18) | (BRW_SURFACE_NULL << 29));
434 OUT_BATCH(0);
435 OUT_BATCH(0);
436 OUT_BATCH(0);
437 OUT_BATCH(0);
438 OUT_BATCH(0);
439
440 OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS | (3 - 2));
441 OUT_BATCH(0);
442 OUT_BATCH(0);
443 }
444