1{ 2 "copyright": [ 3 "============================ begin_copyright_notice ============================", 4 "", 5 "Copyright (C) 2019-2021 Intel Corporation", 6 "", 7 "SPDX-License-Identifier: MIT", 8 "", 9 "============================= end_copyright_notice =============================" 10 ], 11 "DESCRIPTION": "See cisa_gen_intrinsics.py for description of this document", 12 "INTRINSICS": { 13 "genx_fptosi_sat": { 14 "opc": "ISA_MOV", 15 "exec_size": [ "EXECSIZE" ], 16 "pred": [ "IMPLICITPRED" ], 17 "dst": [ "GENERAL", "SIGNED", "SATURATION_SATURATE", 0 ], 18 "src0": [ "GENERAL", "MODIFIER_ARITH", 1 ] 19 }, 20 "genx_fptoui_sat": { 21 "opc": "ISA_MOV", 22 "exec_size": [ "EXECSIZE" ], 23 "pred": [ "IMPLICITPRED" ], 24 "dst": [ "GENERAL", "UNSIGNED", "SATURATION_SATURATE", 0 ], 25 "src0": [ "GENERAL", "MODIFIER_ARITH", 1 ] 26 }, 27 "genx_sat": { 28 "opc": "ISA_MOV", 29 "exec_size": [ "EXECSIZE" ], 30 "pred": [ "IMPLICITPRED" ], 31 "dst": [ "GENERAL", "SATURATION_SATURATE", 0 ], 32 "src0": [ "GENERAL", "MODIFIER_ARITH", 1 ] 33 }, 34 "genx_uutrunc_sat": { 35 "opc": "ISA_MOV", 36 "exec_size": [ "EXECSIZE" ], 37 "pred": [ "IMPLICITPRED" ], 38 "dst": [ "GENERAL", "UNSIGNED", "SATURATION_SATURATE", 0 ], 39 "src0": [ "GENERAL", "UNSIGNED", "MODIFIER_ARITH", 1 ] 40 }, 41 "genx_ustrunc_sat": { 42 "opc": "ISA_MOV", 43 "exec_size": [ "EXECSIZE" ], 44 "pred": [ "IMPLICITPRED" ], 45 "dst": [ "GENERAL", "UNSIGNED", "SATURATION_SATURATE", 0 ], 46 "src0": [ "GENERAL", "SIGNED", "MODIFIER_ARITH", 1 ] 47 }, 48 "genx_sutrunc_sat": { 49 "opc": "ISA_MOV", 50 "exec_size": [ "EXECSIZE" ], 51 "pred": [ "IMPLICITPRED" ], 52 "dst": [ "GENERAL", "SIGNED", "SATURATION_SATURATE", 0 ], 53 "src0": [ "GENERAL", "UNSIGNED", "MODIFIER_ARITH", 1 ] 54 }, 55 "genx_sstrunc_sat": { 56 "opc": "ISA_MOV", 57 "exec_size": [ "EXECSIZE" ], 58 "pred": [ "IMPLICITPRED" ], 59 "dst": [ "GENERAL", "SIGNED", "SATURATION_SATURATE", 0 ], 60 "src0": [ "GENERAL", "SIGNED", "MODIFIER_ARITH", 1 ] 61 }, 62 "genx_thread_x": { 63 "opc": "ISA_MOV", 64 "exec_size": [ "EXECSIZE" ], 65 "pred": [ "IMPLICITPRED" ], 66 "dst": [ "GENERAL", 0 ], 67 "src0": "CreateOpndPredefinedSrc(PREDEFINED_X, 0, 0, 0, 1, 0)" 68 }, 69 "genx_thread_y": { 70 "opc": "ISA_MOV", 71 "exec_size": [ "EXECSIZE" ], 72 "pred": [ "IMPLICITPRED" ], 73 "dst": [ "GENERAL", 0 ], 74 "src0": "CreateOpndPredefinedSrc(PREDEFINED_Y, 0, 0, 0, 1, 0)" 75 }, 76 "genx_group_id_x": { 77 "opc": "ISA_MOV", 78 "exec_size": [ "EXECSIZE" ], 79 "pred": [ "IMPLICITPRED" ], 80 "dst": [ "GENERAL", 0 ], 81 "src0": "CreateOpndPredefinedSrc(PREDEFINED_GROUP_ID_X, 0, 0, 0, 1, 0)" 82 }, 83 "genx_group_id_y": { 84 "opc": "ISA_MOV", 85 "exec_size": [ "EXECSIZE" ], 86 "pred": [ "IMPLICITPRED" ], 87 "dst": [ "GENERAL", 0 ], 88 "src0": "CreateOpndPredefinedSrc(PREDEFINED_GROUP_ID_Y, 0, 0, 0, 1, 0)" 89 }, 90 "genx_group_id_z": { 91 "opc": "ISA_MOV", 92 "exec_size": [ "EXECSIZE" ], 93 "pred": [ "IMPLICITPRED" ], 94 "dst": [ "GENERAL", 0 ], 95 "src0": "CreateOpndPredefinedSrc(PREDEFINED_GROUP_ID_Z, 0, 0, 0, 1, 0)" 96 }, 97 "genx_timestamp": { 98 "opc": "ISA_MOV", 99 "exec_size": [ "EXECSIZE" ], 100 "pred": [ "IMPLICITPRED" ], 101 "dst": [ "GENERAL", 0 ], 102 "src0": "CreateOpndPredefinedSrc(PREDEFINED_TSC, 0, 0, 1, 1, 0)" 103 }, 104 "genx_r0": { 105 "opc": "ISA_MOV", 106 "exec_size": [ "EXECSIZE" ], 107 "pred": [ "IMPLICITPRED" ], 108 "dst": [ "GENERAL", 0 ], 109 "src0": "CreateOpndPredefinedSrc(PREDEFINED_R0, 0, 0, 1, 1, 0)" 110 }, 111 "genx_ce0": { 112 "opc": "ISA_MOV", 113 "exec_size": [ "EXECSIZE_NOMASK" ], 114 "pred": [ "IMPLICITPRED" ], 115 "dst": [ "GENERAL", 0 ], 116 "src0": "CreateOpndPredefinedSrc(PREDEFINED_CE0, 0, 0, 0, 1, 0)" 117 }, 118 "genx_sr0": { 119 "opc": "ISA_MOV", 120 "exec_size": [ "EXECSIZE" ], 121 "pred": [ "IMPLICITPRED" ], 122 "dst": [ "GENERAL", 0 ], 123 "src0": "CreateOpndPredefinedSrc(PREDEFINED_SR0, 0, 0, 1, 1, 0)" 124 }, 125 "genx_set_sr0_2": { 126 "opc": "ISA_MOV", 127 "exec_size": [ "EXECSIZE_NOMASK" ], 128 "pred": [ "IMPLICITPRED" ], 129 "dst": "CreateOpndPredefinedDst(PREDEFINED_SR0, 0, 2, 1)", 130 "src0": [ "GENERAL", 1 ] 131 }, 132 "genx_get_color": { 133 "opc": "ISA_MOV", 134 "exec_size": [ "EXECSIZE" ], 135 "pred": [ "IMPLICITPRED" ], 136 "dst": [ "GENERAL", 0 ], 137 "src0": "CreateOpndPredefinedSrc(PREDEFINED_COLOR, 0, 0, 1, 1, 0)" 138 }, 139 "genx_set_pause": { 140 "opc": "ISA_MOV", 141 "exec_size": [ "EXECSIZE" ], 142 "pred": [ "IMPLICITPRED" ], 143 "dst": "CreateOpndPredefinedDst(PREDEFINED_TSC, 0, 4, 1)", 144 "src0": [ "GENERAL", 1 ] 145 }, 146 "genx_dummy_mov": { 147 "opc": "ISA_MOV", 148 "exec_size": [ "EXECSIZE" ], 149 "pred": [ "IMPLICITPRED" ], 150 "dst": "CreateOpndPredefinedDst(PREDEFINED_NULL, 0, 0, 1)", 151 "src0": [ "GENERAL", 1 ] 152 }, 153 "genx_constanti": { 154 "opc": "ISA_MOV", 155 "exec_size": [ "EXECSIZE" ], 156 "pred": [ "IMPLICITPRED" ], 157 "dst": [ "GENERAL", 0 ], 158 "src0": [ "GENERAL", 1 ] 159 }, 160 "genx_constantf": { 161 "opc": "ISA_MOV", 162 "exec_size": [ "EXECSIZE" ], 163 "pred": [ "IMPLICITPRED" ], 164 "dst": [ "GENERAL", 0 ], 165 "src0": [ "GENERAL", 1 ] 166 }, 167 "genx_media_ld": { 168 "opc": "ISA_MEDIA_LD", 169 "modifiers": [ "BYTE", 1 ], 170 "surface": [ "SURFACE", 2 ], 171 "plane": [ "BYTE", 3 ], 172 "block_width": [ "BYTE", 4 ], 173 "block_height": [ "MEDIAHEIGHT", 4 ], 174 "x_offset": [ "GENERAL", "UNSIGNED", 5 ], 175 "y_offset": [ "GENERAL", "UNSIGNED", 6 ], 176 "dst": [ "RAW", 0 ] 177 }, 178 "genx_media_st": { 179 "opc": "ISA_MEDIA_ST", 180 "modifiers": [ "BYTE", 1 ], 181 "surface": [ "SURFACE", 2 ], 182 "plane": [ "BYTE", 3 ], 183 "block_width": [ "BYTE", 4 ], 184 "block_height": [ "MEDIAHEIGHT", 4 ], 185 "x_offset": [ "GENERAL", "UNSIGNED", 5 ], 186 "y_offset": [ "GENERAL", "UNSIGNED", 6 ], 187 "src": [ "RAW", 7 ] 188 }, 189 "genx_oword_ld": { 190 "opc": "ISA_OWORD_LD", 191 "log2_owords": [ "LOG2OWORDS", 0 ], 192 "is_modified": [ "BYTE", 1 ], 193 "surface": [ "SURFACE", 2 ], 194 "offset": [ "GENERAL", "UNSIGNED", 3 ], 195 "dst": [ "RAW", 0 ] 196 }, 197 "genx_oword_ld_unaligned": { 198 "opc": "ISA_OWORD_LD_UNALIGNED", 199 "gen_opc": "ISA_OWORD_LD", 200 "log2_owords": [ "LOG2OWORDS", 0 ], 201 "is_modified": [ "BYTE", 1 ], 202 "surface": [ "SURFACE", 2 ], 203 "offset": [ "GENERAL", "UNSIGNED", 3 ], 204 "dst": [ "RAW", 0 ] 205 }, 206 "genx_oword_ld_predef_surface": { 207 "opc": "ISA_OWORD_LD", 208 "log2_owords": [ "LOG2OWORDS", 0 ], 209 "is_modified": [ "BYTE", 1 ], 210 "surface": [ "PREDEF_SURFACE", 2 ], 211 "offset": [ "GENERAL", "UNSIGNED", 3 ], 212 "dst": [ "RAW", 0 ] 213 }, 214 "genx_oword_ld_unaligned_predef_surface": { 215 "opc": "ISA_OWORD_LD_UNALIGNED", 216 "gen_opc": "ISA_OWORD_LD", 217 "log2_owords": [ "LOG2OWORDS", 0 ], 218 "is_modified": [ "BYTE", 1 ], 219 "surface": [ "PREDEF_SURFACE", 2 ], 220 "offset": [ "GENERAL", "UNSIGNED", 3 ], 221 "dst": [ "RAW", 0 ] 222 }, 223 "genx_oword_st": { 224 "opc": "ISA_OWORD_ST", 225 "log2_owords": [ "LOG2OWORDS", 3 ], 226 "surface": [ "SURFACE", 1 ], 227 "offset": [ "GENERAL", "UNSIGNED", 2 ], 228 "src": [ "RAW", 3 ] 229 }, 230 "genx_oword_st_predef_surface": { 231 "opc": "ISA_OWORD_ST", 232 "log2_owords": [ "LOG2OWORDS", 3 ], 233 "surface": [ "PREDEF_SURFACE", 1 ], 234 "offset": [ "GENERAL", "UNSIGNED", 2 ], 235 "src": [ "RAW", 3 ] 236 }, 237 "genx_dword_atomic_add": { 238 "opc": "ISA_DWORD_ATOMIC", 239 "sub_opc": [ "LITERAL", "ATOMIC_ADD" ], 240 "exec_size": [ "EXECSIZE_FROM_ARG", 1 ], 241 "pred": [ "PREDICATION", 1 ], 242 "surface": [ "SURFACE", 2 ], 243 "offset": [ "URAW", 3 ], 244 "src": [ "URAW", 4 ], 245 "src1": [ "NULLRAW" ], 246 "twoaddr": [ "TWOADDR", 5 ], 247 "dst": [ "URAW", "RAW_NULLALLOWED", 0 ] 248 }, 249 "genx_dword_atomic_sub": { 250 "opc": "ISA_DWORD_ATOMIC", 251 "sub_opc": [ "LITERAL", "ATOMIC_SUB" ], 252 "exec_size": [ "EXECSIZE_FROM_ARG", 1 ], 253 "pred": [ "PREDICATION", 1 ], 254 "surface": [ "SURFACE", 2 ], 255 "offset": [ "URAW", 3 ], 256 "src": [ "URAW", 4 ], 257 "src1": [ "NULLRAW" ], 258 "twoaddr": [ "TWOADDR", 5 ], 259 "dst": [ "URAW", "RAW_NULLALLOWED", 0 ] 260 }, 261 "genx_dword_atomic_inc": { 262 "opc": "ISA_DWORD_ATOMIC", 263 "sub_opc": [ "LITERAL", "ATOMIC_INC" ], 264 "exec_size": [ "EXECSIZE_FROM_ARG", 1 ], 265 "pred": [ "PREDICATION", 1 ], 266 "surface": [ "SURFACE", 2 ], 267 "offset": [ "URAW", 3 ], 268 "src": [ "NULLRAW" ], 269 "src1": [ "NULLRAW" ], 270 "twoaddr": [ "TWOADDR", 4 ], 271 "dst": [ "URAW", "RAW_NULLALLOWED", 0 ] 272 }, 273 "genx_dword_atomic_dec": { 274 "opc": "ISA_DWORD_ATOMIC", 275 "sub_opc": [ "LITERAL", "ATOMIC_DEC" ], 276 "exec_size": [ "EXECSIZE_FROM_ARG", 1 ], 277 "pred": [ "PREDICATION", 1 ], 278 "surface": [ "SURFACE", 2 ], 279 "offset": [ "URAW", 3 ], 280 "src": [ "NULLRAW" ], 281 "src1": [ "NULLRAW" ], 282 "twoaddr": [ "TWOADDR", 4 ], 283 "dst": [ "URAW", "RAW_NULLALLOWED", 0 ] 284 }, 285 "genx_dword_atomic_min": { 286 "opc": "ISA_DWORD_ATOMIC", 287 "sub_opc": [ "LITERAL", "ATOMIC_MIN" ], 288 "exec_size": [ "EXECSIZE_FROM_ARG", 1 ], 289 "pred": [ "PREDICATION", 1 ], 290 "surface": [ "SURFACE", 2 ], 291 "offset": [ "URAW", 3 ], 292 "src": [ "URAW", 4 ], 293 "src1": [ "NULLRAW" ], 294 "twoaddr": [ "TWOADDR", 5 ], 295 "dst": [ "URAW", "RAW_NULLALLOWED", 0 ] 296 }, 297 "genx_dword_atomic_max": { 298 "opc": "ISA_DWORD_ATOMIC", 299 "sub_opc": [ "LITERAL", "ATOMIC_MAX" ], 300 "exec_size": [ "EXECSIZE_FROM_ARG", 1 ], 301 "pred": [ "PREDICATION", 1 ], 302 "surface": [ "SURFACE", 2 ], 303 "offset": [ "URAW", 3 ], 304 "src": [ "URAW", 4 ], 305 "src1": [ "NULLRAW" ], 306 "twoaddr": [ "TWOADDR", 5 ], 307 "dst": [ "URAW", "RAW_NULLALLOWED", 0 ] 308 }, 309 "genx_dword_atomic_xchg": { 310 "opc": "ISA_DWORD_ATOMIC", 311 "sub_opc": [ "LITERAL", "ATOMIC_XCHG" ], 312 "exec_size": [ "EXECSIZE_FROM_ARG", 1 ], 313 "pred": [ "PREDICATION", 1 ], 314 "surface": [ "SURFACE", 2 ], 315 "offset": [ "URAW", 3 ], 316 "src": [ "URAW", 4 ], 317 "src1": [ "NULLRAW" ], 318 "twoaddr": [ "TWOADDR", 5 ], 319 "dst": [ "URAW", "RAW_NULLALLOWED", 0 ] 320 }, 321 "genx_dword_atomic_cmpxchg": { 322 "opc": "ISA_DWORD_ATOMIC", 323 "sub_opc": [ "LITERAL", "ATOMIC_CMPXCHG" ], 324 "exec_size": [ "EXECSIZE_FROM_ARG", 1 ], 325 "pred": [ "PREDICATION", 1 ], 326 "surface": [ "SURFACE", 2 ], 327 "offset": [ "URAW", 3 ], 328 "src": [ "URAW", 4 ], 329 "src1": [ "URAW", 5 ], 330 "twoaddr": [ "TWOADDR", 6 ], 331 "dst": [ "URAW", "RAW_NULLALLOWED", 0 ] 332 }, 333 "genx_dword_atomic_and": { 334 "opc": "ISA_DWORD_ATOMIC", 335 "sub_opc": [ "LITERAL", "ATOMIC_AND" ], 336 "exec_size": [ "EXECSIZE_FROM_ARG", 1 ], 337 "pred": [ "PREDICATION", 1 ], 338 "surface": [ "SURFACE", 2 ], 339 "offset": [ "URAW", 3 ], 340 "src": [ "URAW", 4 ], 341 "src1": [ "NULLRAW" ], 342 "twoaddr": [ "TWOADDR", 5 ], 343 "dst": [ "URAW", "RAW_NULLALLOWED", 0 ] 344 }, 345 "genx_dword_atomic_or": { 346 "opc": "ISA_DWORD_ATOMIC", 347 "sub_opc": [ "LITERAL", "ATOMIC_OR" ], 348 "exec_size": [ "EXECSIZE_FROM_ARG", 1 ], 349 "pred": [ "PREDICATION", 1 ], 350 "surface": [ "SURFACE", 2 ], 351 "offset": [ "URAW", 3 ], 352 "src": [ "URAW", 4 ], 353 "src1": [ "NULLRAW" ], 354 "twoaddr": [ "TWOADDR", 5 ], 355 "dst": [ "URAW", "RAW_NULLALLOWED", 0 ] 356 }, 357 "genx_dword_atomic_xor": { 358 "opc": "ISA_DWORD_ATOMIC", 359 "sub_opc": [ "LITERAL", "ATOMIC_XOR" ], 360 "exec_size": [ "EXECSIZE_FROM_ARG", 1 ], 361 "pred": [ "PREDICATION", 1 ], 362 "surface": [ "SURFACE", 2 ], 363 "offset": [ "URAW", 3 ], 364 "src": [ "URAW", 4 ], 365 "src1": [ "NULLRAW" ], 366 "twoaddr": [ "TWOADDR", 5 ], 367 "dst": [ "URAW", "RAW_NULLALLOWED", 0 ] 368 }, 369 "genx_dword_atomic_imin": { 370 "opc": "ISA_DWORD_ATOMIC", 371 "sub_opc": [ "LITERAL", "ATOMIC_IMIN" ], 372 "exec_size": [ "EXECSIZE_FROM_ARG", 1 ], 373 "pred": [ "PREDICATION", 1 ], 374 "surface": [ "SURFACE", 2 ], 375 "offset": [ "URAW", 3 ], 376 "src": [ "SRAW", 4 ], 377 "src1": [ "NULLRAW" ], 378 "twoaddr": [ "TWOADDR", 5 ], 379 "dst": [ "SRAW", "RAW_NULLALLOWED", 0 ] 380 }, 381 "genx_dword_atomic_imax": { 382 "opc": "ISA_DWORD_ATOMIC", 383 "sub_opc": [ "LITERAL", "ATOMIC_IMAX" ], 384 "exec_size": [ "EXECSIZE_FROM_ARG", 1 ], 385 "pred": [ "PREDICATION", 1 ], 386 "surface": [ "SURFACE", 2 ], 387 "offset": [ "URAW", 3 ], 388 "src": [ "SRAW", 4 ], 389 "src1": [ "NULLRAW" ], 390 "twoaddr": [ "TWOADDR", 5 ], 391 "dst": [ "SRAW", "RAW_NULLALLOWED", 0 ] 392 }, 393 "genx_dword_atomic_fmax": { 394 "opc": "ISA_DWORD_ATOMIC", 395 "sub_opc": [ "LITERAL", "ATOMIC_FMAX" ], 396 "exec_size": [ "EXECSIZE_FROM_ARG", 1 ], 397 "pred": [ "PREDICATION", 1 ], 398 "surface": [ "SURFACE", 2 ], 399 "offset": [ "URAW", 3 ], 400 "src": [ "RAW", 4 ], 401 "src1": [ "NULLRAW" ], 402 "twoaddr": [ "TWOADDR", 5 ], 403 "dst": [ "RAW", "RAW_NULLALLOWED", 0 ] 404 }, 405 "genx_dword_atomic_fmin": { 406 "opc": "ISA_DWORD_ATOMIC", 407 "sub_opc": [ "LITERAL", "ATOMIC_FMIN" ], 408 "exec_size": [ "EXECSIZE_FROM_ARG", 1 ], 409 "pred": [ "PREDICATION", 1 ], 410 "surface": [ "SURFACE", 2 ], 411 "offset": [ "URAW", 3 ], 412 "src": [ "RAW", 4 ], 413 "src1": [ "NULLRAW" ], 414 "twoaddr": [ "TWOADDR", 5 ], 415 "dst": [ "RAW", "RAW_NULLALLOWED", 0 ] 416 }, 417 "genx_dword_atomic_fcmpwr": { 418 "opc": "ISA_DWORD_ATOMIC", 419 "sub_opc": [ "LITERAL", "ATOMIC_FCMPWR" ], 420 "exec_size": [ "EXECSIZE_FROM_ARG", 1 ], 421 "pred": [ "PREDICATION", 1 ], 422 "surface": [ "SURFACE", 2 ], 423 "offset": [ "URAW", 3 ], 424 "src": [ "RAW", 5 ], 425 "src1": [ "RAW", 4 ], 426 "twoaddr": [ "TWOADDR", 6 ], 427 "dst": [ "RAW", "RAW_NULLALLOWED", 0 ] 428 }, 429 "genx_dword_atomic2_add": { 430 "opc": "ISA_DWORD_ATOMIC", 431 "sub_opc": [ "LITERAL", "ATOMIC_ADD" ], 432 "exec_size": [ "EXECSIZE_FROM_ARG", 1 ], 433 "pred": [ "PREDICATION", 1 ], 434 "surface": [ "SURFACE", 2 ], 435 "offset": [ "URAW", 3 ], 436 "src": [ "URAW", 4 ], 437 "src1": [ "NULLRAW" ], 438 "dst": [ "URAW", "RAW_NULLALLOWED", 0 ] 439 }, 440 "genx_dword_atomic2_sub": { 441 "opc": "ISA_DWORD_ATOMIC", 442 "sub_opc": [ "LITERAL", "ATOMIC_SUB" ], 443 "exec_size": [ "EXECSIZE_FROM_ARG", 1 ], 444 "pred": [ "PREDICATION", 1 ], 445 "surface": [ "SURFACE", 2 ], 446 "offset": [ "URAW", 3 ], 447 "src": [ "URAW", 4 ], 448 "src1": [ "NULLRAW" ], 449 "dst": [ "URAW", "RAW_NULLALLOWED", 0 ] 450 }, 451 "genx_dword_atomic2_inc": { 452 "opc": "ISA_DWORD_ATOMIC", 453 "sub_opc": [ "LITERAL", "ATOMIC_INC" ], 454 "exec_size": [ "EXECSIZE_FROM_ARG", 1 ], 455 "pred": [ "PREDICATION", 1 ], 456 "surface": [ "SURFACE", 2 ], 457 "offset": [ "URAW", 3 ], 458 "src": [ "NULLRAW" ], 459 "src1": [ "NULLRAW" ], 460 "dst": [ "URAW", "RAW_NULLALLOWED", 0 ] 461 }, 462 "genx_dword_atomic2_dec": { 463 "opc": "ISA_DWORD_ATOMIC", 464 "sub_opc": [ "LITERAL", "ATOMIC_DEC" ], 465 "exec_size": [ "EXECSIZE_FROM_ARG", 1 ], 466 "pred": [ "PREDICATION", 1 ], 467 "surface": [ "SURFACE", 2 ], 468 "offset": [ "URAW", 3 ], 469 "src": [ "NULLRAW" ], 470 "src1": [ "NULLRAW" ], 471 "dst": [ "URAW", "RAW_NULLALLOWED", 0 ] 472 }, 473 "genx_dword_atomic2_min": { 474 "opc": "ISA_DWORD_ATOMIC", 475 "sub_opc": [ "LITERAL", "ATOMIC_MIN" ], 476 "exec_size": [ "EXECSIZE_FROM_ARG", 1 ], 477 "pred": [ "PREDICATION", 1 ], 478 "surface": [ "SURFACE", 2 ], 479 "offset": [ "URAW", 3 ], 480 "src": [ "URAW", 4 ], 481 "src1": [ "NULLRAW" ], 482 "dst": [ "URAW", "RAW_NULLALLOWED", 0 ] 483 }, 484 "genx_dword_atomic2_max": { 485 "opc": "ISA_DWORD_ATOMIC", 486 "sub_opc": [ "LITERAL", "ATOMIC_MAX" ], 487 "exec_size": [ "EXECSIZE_FROM_ARG", 1 ], 488 "pred": [ "PREDICATION", 1 ], 489 "surface": [ "SURFACE", 2 ], 490 "offset": [ "URAW", 3 ], 491 "src": [ "URAW", 4 ], 492 "src1": [ "NULLRAW" ], 493 "dst": [ "URAW", "RAW_NULLALLOWED", 0 ] 494 }, 495 "genx_dword_atomic2_xchg": { 496 "opc": "ISA_DWORD_ATOMIC", 497 "sub_opc": [ "LITERAL", "ATOMIC_XCHG" ], 498 "exec_size": [ "EXECSIZE_FROM_ARG", 1 ], 499 "pred": [ "PREDICATION", 1 ], 500 "surface": [ "SURFACE", 2 ], 501 "offset": [ "URAW", 3 ], 502 "src": [ "URAW", 4 ], 503 "src1": [ "NULLRAW" ], 504 "dst": [ "URAW", "RAW_NULLALLOWED", 0 ] 505 }, 506 "genx_dword_atomic2_cmpxchg": { 507 "opc": "ISA_DWORD_ATOMIC", 508 "sub_opc": [ "LITERAL", "ATOMIC_CMPXCHG" ], 509 "exec_size": [ "EXECSIZE_FROM_ARG", 1 ], 510 "pred": [ "PREDICATION", 1 ], 511 "surface": [ "SURFACE", 2 ], 512 "offset": [ "URAW", 3 ], 513 "src": [ "URAW", 4 ], 514 "src1": [ "URAW", 5 ], 515 "dst": [ "URAW", "RAW_NULLALLOWED", 0 ] 516 }, 517 "genx_dword_atomic2_and": { 518 "opc": "ISA_DWORD_ATOMIC", 519 "sub_opc": [ "LITERAL", "ATOMIC_AND" ], 520 "exec_size": [ "EXECSIZE_FROM_ARG", 1 ], 521 "pred": [ "PREDICATION", 1 ], 522 "surface": [ "SURFACE", 2 ], 523 "offset": [ "URAW", 3 ], 524 "src": [ "URAW", 4 ], 525 "src1": [ "NULLRAW" ], 526 "dst": [ "URAW", "RAW_NULLALLOWED", 0 ] 527 }, 528 "genx_dword_atomic2_or": { 529 "opc": "ISA_DWORD_ATOMIC", 530 "sub_opc": [ "LITERAL", "ATOMIC_OR" ], 531 "exec_size": [ "EXECSIZE_FROM_ARG", 1 ], 532 "pred": [ "PREDICATION", 1 ], 533 "surface": [ "SURFACE", 2 ], 534 "offset": [ "URAW", 3 ], 535 "src": [ "URAW", 4 ], 536 "src1": [ "NULLRAW" ], 537 "dst": [ "URAW", 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0 ] 2755 }, 2756 "genx_svm_block_ld_unaligned": { 2757 "opc": "ISA_SVM", 2758 "gen_opc": "ISA_SVM_SVM_BLOCK_LD", 2759 "sub_opc": [ "LITERAL", "SVM_BLOCK_LD" ], 2760 "log2_owords": [ "LOG2OWORDS_PLUS_8", 0 ], 2761 "address": [ "GENERAL", "UNSIGNED", 1 ], 2762 "dst": [ "RAW", 0 ] 2763 }, 2764 "genx_svm_block_st": { 2765 "opc": "ISA_SVM", 2766 "gen_opc": "ISA_SVM_SVM_BLOCK_ST", 2767 "sub_opc": [ "LITERAL", "SVM_BLOCK_ST" ], 2768 "log2_owords": [ "LOG2OWORDS", 2 ], 2769 "address": [ "GENERAL", "UNSIGNED", 1 ], 2770 "src": [ "RAW", 2 ] 2771 }, 2772 "genx_svm_gather": { 2773 "opc": "ISA_SVM", 2774 "gen_opc": "ISA_SVM_SVM_GATHER", 2775 "sub_opc": [ "LITERAL", "SVM_GATHER" ], 2776 "exec_size": [ "EXECSIZE_FROM_ARG", 1 ], 2777 "pred": [ "PREDICATION", 1 ], 2778 "log2_num_blocks": [ "BYTE", 2 ], 2779 "address": [ "URAW", 3 ], 2780 "twoaddr": [ "TWOADDR", 4 ], 2781 "dst": [ "RAW", 0 ] 2782 }, 2783 "genx_svm_gather4_scaled": { 2784 "opc": "ISA_SVM", 2785 "gen_opc": "ISA_SVM_SVM_GATHER4SCALED", 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& MODIFIER_SAT", 3056 "exec_mask", 3057 "exec_size", 3058 "dst", 3059 "src0", 3060 "src1", 3061 "src2" 3062 ] 3063 ] 3064 ], 3065 "ISA_SETP": [ 3066 [ "CISA_CALL", 3067 [ "Kernel->AppendVISASetP", 3068 "exec_mask", 3069 "exec_size", 3070 "dst", 3071 "src0" 3072 ] 3073 ] 3074 ], 3075 "ISA_FMINMAX": [ 3076 [ "CISA_CALL", 3077 [ "Kernel->AppendVISAMinMaxInst", 3078 "(CISA_MIN_MAX_SUB_OPCODE)flag_for_max", 3079 "Mod & MODIFIER_SAT", 3080 "exec_mask", 3081 "exec_size", 3082 "dst", 3083 "src0", 3084 "src1" 3085 ] 3086 ] 3087 ], 3088 "ISA_POW": [ 3089 [ "CISA_CALL", 3090 [ "Kernel->AppendVISAArithmeticInst", 3091 "opc", 3092 "pred", 3093 "Mod & MODIFIER_SAT", 3094 "exec_mask", 3095 "exec_size", 3096 "dst", 3097 "src0", 3098 "src1", 3099 "nullptr" 3100 ] 3101 ] 3102 ], 3103 "ISA_ADDR_ADD": [ 3104 [ "CISA_CALL", 3105 [ "Kernel->AppendVISAAddrAddInst", 3106 "exec_mask", 3107 "exec_size", 3108 "dst", 3109 "src0", 3110 "src1" 3111 ] 3112 ] 3113 ], 3114 "ISA_3D_SAMPLE": [ 3115 [ "CISA_CALL", 3116 [ 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"dst1", 3502 "src0", 3503 "src1" 3504 ] 3505 ] 3506 ], 3507 "ISA_SUBB": [ 3508 [ "CISA_CALL", 3509 [ "Kernel->AppendVISATwoDstArithmeticInst", 3510 "opc", 3511 "pred", 3512 "exec_mask", 3513 "exec_size", 3514 "dst0", 3515 "dst1", 3516 "src0", 3517 "src1" 3518 ] 3519 ] 3520 ], 3521 "ISA_ADD3": [ 3522 "/* ctsign */", 3523 [ "CISA_CALL", 3524 [ "Kernel->AppendVISAArithmeticInst", 3525 "opc", 3526 "pred", 3527 "Mod & MODIFIER_SAT", 3528 "exec_mask", 3529 "exec_size", 3530 "dst", 3531 "src0", 3532 "src1", 3533 "src2" 3534 ] 3535 ] 3536 ], 3537 "ISA_RAW_SEND": [ 3538 [ "CISA_CALL", 3539 [ "Kernel->AppendVISAMiscRawSend", 3540 "pred", 3541 "exec_mask", 3542 "exec_size", 3543 "modifier_sendc", 3544 "extended_message_descriptor", 3545 "numsrc", 3546 "numdst", 3547 "desc", 3548 "src", 3549 "dst" 3550 ] 3551 ] 3552 ], 3553 "ISA_RAW_SENDS": [ 3554 [ "CISA_CALL", 3555 [ "Kernel->AppendVISAMiscRawSends", 3556 "pred", 3557 "exec_mask", 3558 "exec_size", 3559 "modifier_sendc", 3560 "FFID", 3561 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"Min_Max_Enable", 3794 "Destination" 3795 ] 3796 ] 3797 ], 3798 "ISA_VA_Centroid_FOPCODE": [ 3799 [ "CISA_CALL", 3800 [ "Kernel->AppendVISAVACentroid", 3801 "surface", 3802 "normalized_x_co_ordinate", 3803 "normalized_y_co_ordinate", 3804 "vSize", 3805 "Destination" 3806 ] 3807 ] 3808 ], 3809 "ISA_VA_BoolCentroid_FOPCODE": [ 3810 [ "CISA_CALL", 3811 [ "Kernel->AppendVISAVABooleanCentroid", 3812 "surface", 3813 "normalized_x_co_ordinate", 3814 "normalized_y_co_ordinate", 3815 "vSize", 3816 "hSize", 3817 "Destination" 3818 ] 3819 ] 3820 ], 3821 "ISA_VA_SKL_PLUS_ISA_HDC_1PIXELCONV": [ 3822 [ "CISA_CALL", 3823 [ "Kernel->AppendVISAVAHDCConvolve1Pixel", 3824 "sampler", 3825 "surface", 3826 "normalized_x_co_ordinate", 3827 "normalized_y_co_ordinate", 3828 "(HDCReturnFormat)pixel_size", 3829 "offsets", 3830 "destination_surface", 3831 "destination_x_offset", 3832 "destination_y_offset" 3833 ] 3834 ] 3835 ], 3836 "ISA_VA_SKL_PLUS_ISA_HDC_CONV": [ 3837 [ "CISA_CALL", 3838 [ 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"number_of_additional_operands", 3955 "raw_operands" 3956 ] 3957 ] 3958 ], 3959 "ISA_FRC": [ 3960 [ "CISA_CALL", 3961 [ "Kernel->AppendVISALogicOrShiftInst", 3962 "opc", 3963 "pred", 3964 "Mod & MODIFIER_SAT", 3965 "exec_mask", 3966 "exec_size", 3967 "dst", 3968 "src0", 3969 "nullptr", 3970 "nullptr", 3971 "nullptr" 3972 ] 3973 ] 3974 ], 3975 "ISA_VA_Convolve_FOPCODE": [ 3976 [ "CISA_CALL", 3977 [ "Kernel->AppendVISAVAConvolve", 3978 "sampler", 3979 "surface", 3980 "normalized_x_co_ordinate", 3981 "normalized_y_co_ordinate", 3982 "(CONVExecMode)(properties & 0x3)", 3983 "((properties >> 4) & 0x1)", 3984 "dst" 3985 ] 3986 ] 3987 ], 3988 "ISA_VA_ERODE_FOPCODE": [ 3989 [ "CISA_CALL", 3990 [ "Kernel->AppendVISAVAErodeDilate", 3991 "VA_DILATE", 3992 "sampler", 3993 "surface", 3994 "normalized_x_co_ordinate", 3995 "normalized_y_co_ordinate", 3996 "(EDExecMode)properties", 3997 "dst" 3998 ] 3999 ] 4000 ], 4001 "ISA_VA_SKL_PLUS_ISA_HDC_ERODE": [ 4002 [ "CISA_CALL", 4003 [ "Kernel->AppendVISAVAHDCErodeDilate", 4004 "VA_ERODE", 4005 "sampler", 4006 "surface", 4007 "normalized_x_co_ordinate", 4008 "normalized_y_co_ordinate", 4009 "dstSurface", 4010 "xOffset", 4011 "yOffset" 4012 ] 4013 ] 4014 ], 4015 "ISA_VA_SKL_PLUS_ISA_HDC_DILATE": [ 4016 [ "CISA_CALL", 4017 [ "Kernel->AppendVISAVAHDCErodeDilate", 4018 "VA_DILATE", 4019 "sampler", 4020 "surface", 4021 "normalized_x_co_ordinate", 4022 "normalized_y_co_ordinate", 4023 "dstSurface", 4024 "xOffset", 4025 "yOffset" 4026 ] 4027 ] 4028 ], 4029 "ISA_BARRIER": [ 4030 [ "CISA_CALL", 4031 [ "Kernel->AppendVISASyncInst", 4032 "opc", 4033 "0" 4034 ] 4035 ] 4036 ], 4037 "ISA_YIELD": [ 4038 [ "CISA_CALL", 4039 [ "Kernel->AppendVISASyncInst", 4040 "opc", 4041 "0" 4042 ] 4043 ] 4044 ], 4045 "ISA_SAMPLR_CACHE_FLUSH": [ 4046 [ "CISA_CALL", 4047 [ "Kernel->AppendVISASyncInst", 4048 "opc", 4049 "0" 4050 ] 4051 ] 4052 ], 4053 "ISA_SBARRIER": [ 4054 [ "CISA_CALL", 4055 [ "Kernel->AppendVISASplitBarrierInst", 4056 "signal_flag != 0" 4057 ] 4058 ] 4059 ], 4060 "ISA_BF_CVT": [ 4061 [ "CISA_CALL", 4062 [ "Kernel->AppendVISADataMovementInst", 4063 "opc", 4064 "nullptr", 4065 "Mod & MODIFIER_SAT", 4066 "exec_mask", 4067 "exec_size", 4068 "dst", 4069 "src0", 4070 "nullptr" 4071 ] 4072 ] 4073 ], 4074 "ISA_BFREV": [ 4075 [ "CISA_CALL", 4076 [ "Kernel->AppendVISALogicOrShiftInst", 4077 "opc", 4078 "pred", 4079 "Mod & MODIFIER_SAT", 4080 "exec_mask", 4081 "exec_size", 4082 "dst", 4083 "src0", 4084 "nullptr", 4085 "nullptr", 4086 "nullptr" 4087 ] 4088 ] 4089 ], 4090 "ISA_CBIT": [ 4091 [ "CISA_CALL", 4092 [ "Kernel->AppendVISALogicOrShiftInst", 4093 "opc", 4094 "pred", 4095 "Mod & MODIFIER_SAT", 4096 "exec_mask", 4097 "exec_size", 4098 "dst", 4099 "src0", 4100 "nullptr", 4101 "nullptr", 4102 "nullptr" 4103 ] 4104 ] 4105 ], 4106 "ISA_DIVM": [ 4107 [ "CISA_CALL", 4108 [ "Kernel->AppendVISAArithmeticInst", 4109 "opc", 4110 "pred", 4111 "Mod & MODIFIER_SAT", 4112 "exec_mask", 4113 "exec_size", 4114 "dst", 4115 "src0", 4116 "src1", 4117 "nullptr" 4118 ] 4119 ] 4120 ], 4121 "ISA_DP2": [ 4122 [ "CISA_CALL", 4123 [ "Kernel->AppendVISAArithmeticInst", 4124 "opc", 4125 "pred", 4126 "Mod & MODIFIER_SAT", 4127 "exec_mask", 4128 "exec_size", 4129 "dst", 4130 "src0", 4131 "src1", 4132 "nullptr" 4133 ] 4134 ] 4135 ], 4136 "ISA_DP3": [ 4137 [ "CISA_CALL", 4138 [ "Kernel->AppendVISAArithmeticInst", 4139 "opc", 4140 "pred", 4141 "Mod & MODIFIER_SAT", 4142 "exec_mask", 4143 "exec_size", 4144 "dst", 4145 "src0", 4146 "src1", 4147 "nullptr" 4148 ] 4149 ] 4150 ], 4151 "ISA_DP4": [ 4152 [ "CISA_CALL", 4153 [ "Kernel->AppendVISAArithmeticInst", 4154 "opc", 4155 "pred", 4156 "Mod & MODIFIER_SAT", 4157 "exec_mask", 4158 "exec_size", 4159 "dst", 4160 "src0", 4161 "src1", 4162 "nullptr" 4163 ] 4164 ] 4165 ], 4166 "ISA_DP4A": [ 4167 [ "CISA_CALL", 4168 [ "Kernel->AppendVISAArithmeticInst", 4169 "opc", 4170 "pred", 4171 "Mod & MODIFIER_SAT", 4172 "exec_mask", 4173 "exec_size", 4174 "dst", 4175 "src0", 4176 "src1", 4177 "src2" 4178 ] 4179 ] 4180 ], 4181 "ISA_DPH": [ 4182 [ "CISA_CALL", 4183 [ "Kernel->AppendVISAArithmeticInst", 4184 "opc", 4185 "pred", 4186 "Mod & MODIFIER_SAT", 4187 "exec_mask", 4188 "exec_size", 4189 "dst", 4190 "src0", 4191 "src1", 4192 "nullptr" 4193 ] 4194 ] 4195 ], 4196 "ISA_DPAS": [ 4197 "(void)src3", 4198 "(void)dstSign", 4199 "(void)src0Sign", 4200 [ "CISA_CALL", 4201 [ "Kernel->AppendVISADpasInst", 4202 "opc", 4203 "exec_mask", 4204 "exec_size", 4205 "dst", 4206 "src0", 4207 "src1", 4208 "src2", 4209 "(GenPrecision)src2Precision", 4210 "(GenPrecision)src1Precision", 4211 "systolicDepth", 4212 "RepeatCount" 4213 ] 4214 ] 4215 ], 4216 "ISA_DPASW": [ 4217 [ "CISA_CALL", 4218 [ "Kernel->AppendVISADpasInst", 4219 "opc", 4220 "exec_mask", 4221 "exec_size", 4222 "dst", 4223 "src0", 4224 "src1", 4225 "src2", 4226 "(GenPrecision)((src3 >> 8) & 0xff)", 4227 "(GenPrecision)(src3 & 0xff)", 4228 "(src3 >> 16) & 0xff", 4229 "(src3 >> 24) & 0xff" 4230 ] 4231 ] 4232 ], 4233 "ISA_FBH": [ 4234 [ "CISA_CALL", 4235 [ "Kernel->AppendVISALogicOrShiftInst", 4236 "opc", 4237 "pred", 4238 "Mod & MODIFIER_SAT", 4239 "exec_mask", 4240 "exec_size", 4241 "dst", 4242 "src0", 4243 "nullptr", 4244 "nullptr", 4245 "nullptr" 4246 ] 4247 ] 4248 ], 4249 "ISA_FBL": [ 4250 [ "CISA_CALL", 4251 [ "Kernel->AppendVISALogicOrShiftInst", 4252 "opc", 4253 "pred", 4254 "Mod & MODIFIER_SAT", 4255 "exec_mask", 4256 "exec_size", 4257 "dst", 4258 "src0", 4259 "nullptr", 4260 "nullptr", 4261 "nullptr" 4262 ] 4263 ] 4264 ], 4265 "ISA_LINE": [ 4266 [ "CISA_CALL", 4267 [ "Kernel->AppendVISAArithmeticInst", 4268 "opc", 4269 "pred", 4270 "Mod & MODIFIER_SAT", 4271 "exec_mask", 4272 "exec_size", 4273 "dst", 4274 "src0", 4275 "src1", 4276 "nullptr" 4277 ] 4278 ] 4279 ], 4280 "ISA_LOAD": [ 4281 [ "CISA_CALL", 4282 [ "Kernel->AppendVISASILoad", 4283 "surface", 4284 "convertChannelMaskToVisaType(channel_mask & 0xf)", 4285 "(channel_mask >> 4) & 0x3", 4286 "U_pixel_address", 4287 "V_pixel_address", 4288 "R_pixel_address", 4289 "dst" 4290 ] 4291 ] 4292 ], 4293 "ISA_SAMPLE": [ 4294 [ "CISA_CALL", 4295 [ "Kernel->AppendVISASISample", 4296 "vISA_EMASK_M1", 4297 "surface", 4298 "sampler", 4299 "convertChannelMaskToVisaType(channel_mask)", 4300 "(channel_mask >> 4) & 0x3", 4301 "U_pixel_address", 4302 "V_pixel_address", 4303 "R_pixel_address", 4304 "dst" 4305 ] 4306 ] 4307 ], 4308 "ISA_LRP": [ 4309 [ "CISA_CALL", 4310 [ "Kernel->AppendVISAArithmeticInst", 4311 "opc", 4312 "pred", 4313 "Mod & MODIFIER_SAT", 4314 "exec_mask", 4315 "exec_size", 4316 "dst", 4317 "src0", 4318 "src1", 4319 "src2" 4320 ] 4321 ] 4322 ], 4323 "ISA_PLANE": [ 4324 [ "CISA_CALL", 4325 [ "Kernel->AppendVISAArithmeticInst", 4326 "opc", 4327 "pred", 4328 "Mod & MODIFIER_SAT", 4329 "exec_mask", 4330 "exec_size", 4331 "dst", 4332 "src0", 4333 "src1", 4334 "nullptr" 4335 ] 4336 ] 4337 ], 4338 "ISA_SVM_SVM_ATOMIC": [ 4339 [ "CISA_CALL", 4340 [ "Kernel->AppendVISASvmAtomicInst", 4341 "pred", 4342 "exec_mask", 4343 "exec_size", 4344 "sub_opc", 4345 "bit_width", 4346 "address", 4347 "src0", 4348 "src1", 4349 "dst" 4350 ] 4351 ] 4352 ], 4353 "ISA_SVM_SVM_BLOCK_LD": [ 4354 [ "CISA_CALL", 4355 [ "Kernel->AppendVISASvmBlockLoadInst", 4356 "VISA_Oword_Num(log2_owords & 0x7)", 4357 "(log2_owords & 8)", 4358 "address", 4359 "dst" 4360 ] 4361 ] 4362 ], 4363 "ISA_SVM_SVM_BLOCK_ST": [ 4364 [ "CISA_CALL", 4365 [ "Kernel->AppendVISASvmBlockStoreInst", 4366 "VISA_Oword_Num(log2_owords)", 4367 "(log2_owords & 8)", 4368 "address", 4369 "src" 4370 ] 4371 ] 4372 ], 4373 "ISA_SVM_SVM_GATHER": [ 4374 "unsigned BlockType, BlockNum", 4375 "std::tie(BlockType, BlockNum) = GetSvmBlockSizeNum(II::ArgInfo(II::GENERAL | 0), II::ArgInfo(II::GENERAL | 2))", 4376 [ "CISA_CALL", 4377 [ "Kernel->AppendVISASvmGatherInst", 4378 "pred", 4379 "exec_mask", 4380 "exec_size", 4381 "(VISA_SVM_Block_Type)BlockType", 4382 "(VISA_SVM_Block_Num)BlockNum", 4383 "address", 4384 "dst" 4385 ] 4386 ] 4387 ], 4388 "ISA_SVM_SVM_GATHER4SCALED": [ 4389 [ "CISA_CALL", 4390 [ "Kernel->AppendVISASvmGather4ScaledInst", 4391 "pred", 4392 "exec_mask", 4393 "exec_size", 4394 "convertChannelMaskToVisaType(channel_mask)", 4395 "address", 4396 "offset", 4397 "dst" 4398 ] 4399 ] 4400 ], 4401 "ISA_SVM_SVM_SCATTER": [ 4402 "unsigned BlockType, BlockNum", 4403 "std::tie(BlockType, BlockNum) = GetSvmBlockSizeNum(II::ArgInfo(II::GENERAL | 4), II::ArgInfo(II::GENERAL | 2))", 4404 [ "CISA_CALL", 4405 [ "Kernel->AppendVISASvmScatterInst", 4406 "pred", 4407 "exec_mask", 4408 "exec_size", 4409 "(VISA_SVM_Block_Type)BlockType", 4410 "(VISA_SVM_Block_Num)BlockNum", 4411 "address", 4412 "src" 4413 ] 4414 ] 4415 ], 4416 "ISA_SVM_SVM_SCATTER4SCALED": [ 4417 [ "CISA_CALL", 4418 [ "Kernel->AppendVISASvmScatter4ScaledInst", 4419 "pred", 4420 "exec_mask", 4421 "exec_size", 4422 "convertChannelMaskToVisaType(channel_mask)", 4423 "address", 4424 "offset", 4425 "src" 4426 ] 4427 ] 4428 ], 4429 "ISA_CMP_E": [ 4430 [ "CISA_CALL", 4431 [ "Kernel->AppendVISAComparisonInst", 4432 "opc", 4433 "exec_mask", 4434 "exec_size", 4435 "dst", 4436 "src0", 4437 "src1" 4438 ] 4439 ] 4440 ] 4441 }, 4442 "ARGUMENTS_GEN": { 4443 "EXECSIZE": "GetExecSize(II::ArgInfo({args}), &exec_mask)", 4444 "EXECSIZE_GE2": "GetExecSize(II::ArgInfo({args}), &exec_mask)", 4445 "EXECSIZE_GE4": "GetExecSize(II::ArgInfo({args}), &exec_mask)", 4446 "EXECSIZE_GE8": "GetExecSize(II::ArgInfo({args}), &exec_mask)", 4447 "EXECSIZE_NOT2": "GetExecSize(II::ArgInfo({args}), &exec_mask)", 4448 "EXECSIZE_NOMASK": "GetExecSize(II::ArgInfo({args}), &exec_mask)", 4449 "EXECSIZE_FROM_ARG": "GetExecSizeFromArg(II::ArgInfo({args}), &exec_mask)", 4450 "EXECSIZE_FROM_BYTE": "GetExecSizeFromByte(II::ArgInfo({args}), &exec_mask)", 4451 "NULLRAW": "CreateNullRawOperand(II::ArgInfo({args}))", 4452 "MEDIAHEIGHT": "GetMediaHeght(II::ArgInfo({args}))", 4453 "IMPLICITPRED": "CreateImplicitPredication(II::ArgInfo({args}))", 4454 "GENERAL": "CreateOperand(II::ArgInfo({args}))", 4455 "GENERAL_CTSIGN": "CreateOperand(II::ArgInfo({args}), ctsign)", 4456 "ADDRESS": "CreateAddressOperand(II::ArgInfo({args}))", 4457 "RAW": "CreateRawOperand(II::ArgInfo({args}))", 4458 "URAW": "CreateRawOperand(II::ArgInfo({args} | II::RAW_UNSIGNED))", 4459 "SRAW": "CreateRawOperand(II::ArgInfo({args} | II::RAW_SIGNED))", 4460 "SURFACE": "CreateSurfaceOperand(II::ArgInfo({args}))", 4461 "SAMPLER": "CreateSamplerOperand(II::ArgInfo({args}))", 4462 "PREDICATION": "CreatePredication(II::ArgInfo({args}))", 4463 "PREDICATE": "GetPredicateVar(II::ArgInfo({args}))", 4464 "Z_PREDICATE": "GetZeroedPredicateVar(II::ArgInfo({args}))", 4465 "BYTE": "GetUnsignedValue(II::ArgInfo({args}))", 4466 "SHORT": "GetUnsignedValue(II::ArgInfo({args}))", 4467 "INT": "GetUnsignedValue(II::ArgInfo({args}))", 4468 "LOG2OWORDS": "GetOwords(II::ArgInfo({args}))", 4469 "LOG2OWORDS_PLUS_8": "GetOwords(II::ArgInfo({args})) + 8", 4470 "TWOADDR": "ProcessTwoAddr(II::ArgInfo({args}))", 4471 "CONSTVI1ASI32": "ConstVi1Asi32(II::ArgInfo({args}))", 4472 "ARGCOUNT": "GetArgCount(II::ArgInfo({args}))", 4473 "NUMGRFS": "GetNumGrfs(II::ArgInfo({args}))", 4474 "SAMPLECHMASK": "GetSampleChMask(II::ArgInfo({args}))", 4475 "RAW_OPERANDS": ["VISA_RawOpnd* {dst}[16]", "CreateRawOperands(II::ArgInfo({args}), {dst})"], 4476 "LITERAL": "{value1}", 4477 "ISBARRIER": "HasBarrier = true", 4478 "BITWIDTH": "GetBitWidth(II::ArgInfo({args}))", 4479 "PREDEF_SURFACE": "CreatePredefSurfaceOperand(II::ArgInfo({args}))", 4480 "SKIP": null 4481 } 4482} 4483