1 //===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes the target machine instruction set to the code generator. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_TARGET_TARGETINSTRINFO_H 15 #define LLVM_TARGET_TARGETINSTRINFO_H 16 17 #include "llvm/ADT/DenseMap.h" 18 #include "llvm/ADT/SmallSet.h" 19 #include "llvm/CodeGen/MachineCombinerPattern.h" 20 #include "llvm/CodeGen/MachineFunction.h" 21 #include "llvm/MC/MCInstrInfo.h" 22 #include "llvm/Target/TargetRegisterInfo.h" 23 24 namespace llvm { 25 26 class InstrItineraryData; 27 class LiveVariables; 28 class MCAsmInfo; 29 class MachineMemOperand; 30 class MachineRegisterInfo; 31 class MDNode; 32 class MCInst; 33 struct MCSchedModel; 34 class MCSymbolRefExpr; 35 class SDNode; 36 class ScheduleHazardRecognizer; 37 class SelectionDAG; 38 class ScheduleDAG; 39 class TargetRegisterClass; 40 class TargetRegisterInfo; 41 class BranchProbability; 42 class TargetSubtargetInfo; 43 class DFAPacketizer; 44 45 template<class T> class SmallVectorImpl; 46 47 48 //--------------------------------------------------------------------------- 49 /// 50 /// TargetInstrInfo - Interface to description of machine instruction set 51 /// 52 class TargetInstrInfo : public MCInstrInfo { 53 TargetInstrInfo(const TargetInstrInfo &) LLVM_DELETED_FUNCTION; 54 void operator=(const TargetInstrInfo &) LLVM_DELETED_FUNCTION; 55 public: 56 TargetInstrInfo(int CFSetupOpcode = -1, int CFDestroyOpcode = -1) CallFrameSetupOpcode(CFSetupOpcode)57 : CallFrameSetupOpcode(CFSetupOpcode), 58 CallFrameDestroyOpcode(CFDestroyOpcode) { 59 } 60 61 virtual ~TargetInstrInfo(); 62 63 /// getRegClass - Givem a machine instruction descriptor, returns the register 64 /// class constraint for OpNum, or NULL. 65 const TargetRegisterClass *getRegClass(const MCInstrDesc &TID, 66 unsigned OpNum, 67 const TargetRegisterInfo *TRI, 68 const MachineFunction &MF) const; 69 70 /// isTriviallyReMaterializable - Return true if the instruction is trivially 71 /// rematerializable, meaning it has no side effects and requires no operands 72 /// that aren't always available. 73 bool isTriviallyReMaterializable(const MachineInstr *MI, 74 AliasAnalysis *AA = nullptr) const { 75 return MI->getOpcode() == TargetOpcode::IMPLICIT_DEF || 76 (MI->getDesc().isRematerializable() && 77 (isReallyTriviallyReMaterializable(MI, AA) || 78 isReallyTriviallyReMaterializableGeneric(MI, AA))); 79 } 80 81 protected: 82 /// isReallyTriviallyReMaterializable - For instructions with opcodes for 83 /// which the M_REMATERIALIZABLE flag is set, this hook lets the target 84 /// specify whether the instruction is actually trivially rematerializable, 85 /// taking into consideration its operands. This predicate must return false 86 /// if the instruction has any side effects other than producing a value, or 87 /// if it requres any address registers that are not always available. isReallyTriviallyReMaterializable(const MachineInstr * MI,AliasAnalysis * AA)88 virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI, 89 AliasAnalysis *AA) const { 90 return false; 91 } 92 93 private: 94 /// isReallyTriviallyReMaterializableGeneric - For instructions with opcodes 95 /// for which the M_REMATERIALIZABLE flag is set and the target hook 96 /// isReallyTriviallyReMaterializable returns false, this function does 97 /// target-independent tests to determine if the instruction is really 98 /// trivially rematerializable. 99 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI, 100 AliasAnalysis *AA) const; 101 102 public: 103 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the 104 /// frame setup/destroy instructions if they exist (-1 otherwise). Some 105 /// targets use pseudo instructions in order to abstract away the difference 106 /// between operating with a frame pointer and operating without, through the 107 /// use of these two instructions. 108 /// getCallFrameSetupOpcode()109 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; } getCallFrameDestroyOpcode()110 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; } 111 112 /// Returns the actual stack pointer adjustment made by an instruction 113 /// as part of a call sequence. By default, only call frame setup/destroy 114 /// instructions adjust the stack, but targets may want to override this 115 /// to enable more fine-grained adjustment, or adjust by a different value. 116 virtual int getSPAdjust(const MachineInstr *MI) const; 117 118 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable" 119 /// extension instruction. That is, it's like a copy where it's legal for the 120 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns 121 /// true, then it's expected the pre-extension value is available as a subreg 122 /// of the result register. This also returns the sub-register index in 123 /// SubIdx. isCoalescableExtInstr(const MachineInstr & MI,unsigned & SrcReg,unsigned & DstReg,unsigned & SubIdx)124 virtual bool isCoalescableExtInstr(const MachineInstr &MI, 125 unsigned &SrcReg, unsigned &DstReg, 126 unsigned &SubIdx) const { 127 return false; 128 } 129 130 /// isLoadFromStackSlot - If the specified machine instruction is a direct 131 /// load from a stack slot, return the virtual or physical register number of 132 /// the destination along with the FrameIndex of the loaded stack slot. If 133 /// not, return 0. This predicate must return 0 if the instruction has 134 /// any side effects other than loading from the stack slot. isLoadFromStackSlot(const MachineInstr * MI,int & FrameIndex)135 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, 136 int &FrameIndex) const { 137 return 0; 138 } 139 140 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination 141 /// stack locations as well. This uses a heuristic so it isn't 142 /// reliable for correctness. isLoadFromStackSlotPostFE(const MachineInstr * MI,int & FrameIndex)143 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, 144 int &FrameIndex) const { 145 return 0; 146 } 147 148 /// hasLoadFromStackSlot - If the specified machine instruction has 149 /// a load from a stack slot, return true along with the FrameIndex 150 /// of the loaded stack slot and the machine mem operand containing 151 /// the reference. If not, return false. Unlike 152 /// isLoadFromStackSlot, this returns true for any instructions that 153 /// loads from the stack. This is just a hint, as some cases may be 154 /// missed. 155 virtual bool hasLoadFromStackSlot(const MachineInstr *MI, 156 const MachineMemOperand *&MMO, 157 int &FrameIndex) const; 158 159 /// isStoreToStackSlot - If the specified machine instruction is a direct 160 /// store to a stack slot, return the virtual or physical register number of 161 /// the source reg along with the FrameIndex of the loaded stack slot. If 162 /// not, return 0. This predicate must return 0 if the instruction has 163 /// any side effects other than storing to the stack slot. isStoreToStackSlot(const MachineInstr * MI,int & FrameIndex)164 virtual unsigned isStoreToStackSlot(const MachineInstr *MI, 165 int &FrameIndex) const { 166 return 0; 167 } 168 169 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination 170 /// stack locations as well. This uses a heuristic so it isn't 171 /// reliable for correctness. isStoreToStackSlotPostFE(const MachineInstr * MI,int & FrameIndex)172 virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI, 173 int &FrameIndex) const { 174 return 0; 175 } 176 177 /// hasStoreToStackSlot - If the specified machine instruction has a 178 /// store to a stack slot, return true along with the FrameIndex of 179 /// the loaded stack slot and the machine mem operand containing the 180 /// reference. If not, return false. Unlike isStoreToStackSlot, 181 /// this returns true for any instructions that stores to the 182 /// stack. This is just a hint, as some cases may be missed. 183 virtual bool hasStoreToStackSlot(const MachineInstr *MI, 184 const MachineMemOperand *&MMO, 185 int &FrameIndex) const; 186 187 /// isStackSlotCopy - Return true if the specified machine instruction 188 /// is a copy of one stack slot to another and has no other effect. 189 /// Provide the identity of the two frame indices. isStackSlotCopy(const MachineInstr * MI,int & DestFrameIndex,int & SrcFrameIndex)190 virtual bool isStackSlotCopy(const MachineInstr *MI, int &DestFrameIndex, 191 int &SrcFrameIndex) const { 192 return false; 193 } 194 195 /// Compute the size in bytes and offset within a stack slot of a spilled 196 /// register or subregister. 197 /// 198 /// \param [out] Size in bytes of the spilled value. 199 /// \param [out] Offset in bytes within the stack slot. 200 /// \returns true if both Size and Offset are successfully computed. 201 /// 202 /// Not all subregisters have computable spill slots. For example, 203 /// subregisters registers may not be byte-sized, and a pair of discontiguous 204 /// subregisters has no single offset. 205 /// 206 /// Targets with nontrivial bigendian implementations may need to override 207 /// this, particularly to support spilled vector registers. 208 virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx, 209 unsigned &Size, unsigned &Offset, 210 const TargetMachine *TM) const; 211 212 /// isAsCheapAsAMove - Return true if the instruction is as cheap as a move 213 /// instruction. 214 /// 215 /// Targets for different archs need to override this, and different 216 /// micro-architectures can also be finely tuned inside. isAsCheapAsAMove(const MachineInstr * MI)217 virtual bool isAsCheapAsAMove(const MachineInstr *MI) const { 218 return MI->isAsCheapAsAMove(); 219 } 220 221 /// reMaterialize - Re-issue the specified 'original' instruction at the 222 /// specific location targeting a new destination register. 223 /// The register in Orig->getOperand(0).getReg() will be substituted by 224 /// DestReg:SubIdx. Any existing subreg index is preserved or composed with 225 /// SubIdx. 226 virtual void reMaterialize(MachineBasicBlock &MBB, 227 MachineBasicBlock::iterator MI, 228 unsigned DestReg, unsigned SubIdx, 229 const MachineInstr *Orig, 230 const TargetRegisterInfo &TRI) const; 231 232 /// duplicate - Create a duplicate of the Orig instruction in MF. This is like 233 /// MachineFunction::CloneMachineInstr(), but the target may update operands 234 /// that are required to be unique. 235 /// 236 /// The instruction must be duplicable as indicated by isNotDuplicable(). 237 virtual MachineInstr *duplicate(MachineInstr *Orig, 238 MachineFunction &MF) const; 239 240 /// convertToThreeAddress - This method must be implemented by targets that 241 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 242 /// may be able to convert a two-address instruction into one or more true 243 /// three-address instructions on demand. This allows the X86 target (for 244 /// example) to convert ADD and SHL instructions into LEA instructions if they 245 /// would require register copies due to two-addressness. 246 /// 247 /// This method returns a null pointer if the transformation cannot be 248 /// performed, otherwise it returns the last new instruction. 249 /// 250 virtual MachineInstr * convertToThreeAddress(MachineFunction::iterator & MFI,MachineBasicBlock::iterator & MBBI,LiveVariables * LV)251 convertToThreeAddress(MachineFunction::iterator &MFI, 252 MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const { 253 return nullptr; 254 } 255 256 /// commuteInstruction - If a target has any instructions that are 257 /// commutable but require converting to different instructions or making 258 /// non-trivial changes to commute them, this method can overloaded to do 259 /// that. The default implementation simply swaps the commutable operands. 260 /// If NewMI is false, MI is modified in place and returned; otherwise, a 261 /// new machine instruction is created and returned. Do not call this 262 /// method for a non-commutable instruction, but there may be some cases 263 /// where this method fails and returns null. 264 virtual MachineInstr *commuteInstruction(MachineInstr *MI, 265 bool NewMI = false) const; 266 267 /// findCommutedOpIndices - If specified MI is commutable, return the two 268 /// operand indices that would swap value. Return false if the instruction 269 /// is not in a form which this routine understands. 270 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, 271 unsigned &SrcOpIdx2) const; 272 273 /// A pair composed of a register and a sub-register index. 274 /// Used to give some type checking when modeling Reg:SubReg. 275 struct RegSubRegPair { 276 unsigned Reg; 277 unsigned SubReg; 278 RegSubRegPair(unsigned Reg = 0, unsigned SubReg = 0) RegRegSubRegPair279 : Reg(Reg), SubReg(SubReg) {} 280 }; 281 /// A pair composed of a pair of a register and a sub-register index, 282 /// and another sub-register index. 283 /// Used to give some type checking when modeling Reg:SubReg1, SubReg2. 284 struct RegSubRegPairAndIdx : RegSubRegPair { 285 unsigned SubIdx; 286 RegSubRegPairAndIdx(unsigned Reg = 0, unsigned SubReg = 0, 287 unsigned SubIdx = 0) RegSubRegPairRegSubRegPairAndIdx288 : RegSubRegPair(Reg, SubReg), SubIdx(SubIdx) {} 289 }; 290 291 /// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI 292 /// and \p DefIdx. 293 /// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of 294 /// the list is modeled as <Reg:SubReg, SubIdx>. 295 /// E.g., REG_SEQUENCE vreg1:sub1, sub0, vreg2, sub1 would produce 296 /// two elements: 297 /// - vreg1:sub1, sub0 298 /// - vreg2<:0>, sub1 299 /// 300 /// \returns true if it is possible to build such an input sequence 301 /// with the pair \p MI, \p DefIdx. False otherwise. 302 /// 303 /// \pre MI.isRegSequence() or MI.isRegSequenceLike(). 304 /// 305 /// \note The generic implementation does not provide any support for 306 /// MI.isRegSequenceLike(). In other words, one has to override 307 /// getRegSequenceLikeInputs for target specific instructions. 308 bool 309 getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx, 310 SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const; 311 312 /// Build the equivalent inputs of a EXTRACT_SUBREG for the given \p MI 313 /// and \p DefIdx. 314 /// \p [out] InputReg of the equivalent EXTRACT_SUBREG. 315 /// E.g., EXTRACT_SUBREG vreg1:sub1, sub0, sub1 would produce: 316 /// - vreg1:sub1, sub0 317 /// 318 /// \returns true if it is possible to build such an input sequence 319 /// with the pair \p MI, \p DefIdx. False otherwise. 320 /// 321 /// \pre MI.isExtractSubreg() or MI.isExtractSubregLike(). 322 /// 323 /// \note The generic implementation does not provide any support for 324 /// MI.isExtractSubregLike(). In other words, one has to override 325 /// getExtractSubregLikeInputs for target specific instructions. 326 bool 327 getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx, 328 RegSubRegPairAndIdx &InputReg) const; 329 330 /// Build the equivalent inputs of a INSERT_SUBREG for the given \p MI 331 /// and \p DefIdx. 332 /// \p [out] BaseReg and \p [out] InsertedReg contain 333 /// the equivalent inputs of INSERT_SUBREG. 334 /// E.g., INSERT_SUBREG vreg0:sub0, vreg1:sub1, sub3 would produce: 335 /// - BaseReg: vreg0:sub0 336 /// - InsertedReg: vreg1:sub1, sub3 337 /// 338 /// \returns true if it is possible to build such an input sequence 339 /// with the pair \p MI, \p DefIdx. False otherwise. 340 /// 341 /// \pre MI.isInsertSubreg() or MI.isInsertSubregLike(). 342 /// 343 /// \note The generic implementation does not provide any support for 344 /// MI.isInsertSubregLike(). In other words, one has to override 345 /// getInsertSubregLikeInputs for target specific instructions. 346 bool 347 getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx, 348 RegSubRegPair &BaseReg, 349 RegSubRegPairAndIdx &InsertedReg) const; 350 351 352 /// produceSameValue - Return true if two machine instructions would produce 353 /// identical values. By default, this is only true when the two instructions 354 /// are deemed identical except for defs. If this function is called when the 355 /// IR is still in SSA form, the caller can pass the MachineRegisterInfo for 356 /// aggressive checks. 357 virtual bool produceSameValue(const MachineInstr *MI0, 358 const MachineInstr *MI1, 359 const MachineRegisterInfo *MRI = nullptr) const; 360 361 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning 362 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't 363 /// implemented for a target). Upon success, this returns false and returns 364 /// with the following information in various cases: 365 /// 366 /// 1. If this block ends with no branches (it just falls through to its succ) 367 /// just return false, leaving TBB/FBB null. 368 /// 2. If this block ends with only an unconditional branch, it sets TBB to be 369 /// the destination block. 370 /// 3. If this block ends with a conditional branch and it falls through to a 371 /// successor block, it sets TBB to be the branch destination block and a 372 /// list of operands that evaluate the condition. These operands can be 373 /// passed to other TargetInstrInfo methods to create new branches. 374 /// 4. If this block ends with a conditional branch followed by an 375 /// unconditional branch, it returns the 'true' destination in TBB, the 376 /// 'false' destination in FBB, and a list of operands that evaluate the 377 /// condition. These operands can be passed to other TargetInstrInfo 378 /// methods to create new branches. 379 /// 380 /// Note that RemoveBranch and InsertBranch must be implemented to support 381 /// cases where this method returns success. 382 /// 383 /// If AllowModify is true, then this routine is allowed to modify the basic 384 /// block (e.g. delete instructions after the unconditional branch). 385 /// 386 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 387 MachineBasicBlock *&FBB, 388 SmallVectorImpl<MachineOperand> &Cond, 389 bool AllowModify = false) const { 390 return true; 391 } 392 393 /// RemoveBranch - Remove the branching code at the end of the specific MBB. 394 /// This is only invoked in cases where AnalyzeBranch returns success. It 395 /// returns the number of instructions that were removed. RemoveBranch(MachineBasicBlock & MBB)396 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const { 397 llvm_unreachable("Target didn't implement TargetInstrInfo::RemoveBranch!"); 398 } 399 400 /// InsertBranch - Insert branch code into the end of the specified 401 /// MachineBasicBlock. The operands to this method are the same as those 402 /// returned by AnalyzeBranch. This is only invoked in cases where 403 /// AnalyzeBranch returns success. It returns the number of instructions 404 /// inserted. 405 /// 406 /// It is also invoked by tail merging to add unconditional branches in 407 /// cases where AnalyzeBranch doesn't apply because there was no original 408 /// branch to analyze. At least this much must be implemented, else tail 409 /// merging needs to be disabled. InsertBranch(MachineBasicBlock & MBB,MachineBasicBlock * TBB,MachineBasicBlock * FBB,const SmallVectorImpl<MachineOperand> & Cond,DebugLoc DL)410 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 411 MachineBasicBlock *FBB, 412 const SmallVectorImpl<MachineOperand> &Cond, 413 DebugLoc DL) const { 414 llvm_unreachable("Target didn't implement TargetInstrInfo::InsertBranch!"); 415 } 416 417 /// ReplaceTailWithBranchTo - Delete the instruction OldInst and everything 418 /// after it, replacing it with an unconditional branch to NewDest. This is 419 /// used by the tail merging pass. 420 virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, 421 MachineBasicBlock *NewDest) const; 422 423 /// getUnconditionalBranch - Get an instruction that performs an unconditional 424 /// branch to the given symbol. 425 virtual void getUnconditionalBranch(MCInst & MI,const MCSymbolRefExpr * BranchTarget)426 getUnconditionalBranch(MCInst &MI, 427 const MCSymbolRefExpr *BranchTarget) const { 428 llvm_unreachable("Target didn't implement " 429 "TargetInstrInfo::getUnconditionalBranch!"); 430 } 431 432 /// getTrap - Get a machine trap instruction getTrap(MCInst & MI)433 virtual void getTrap(MCInst &MI) const { 434 llvm_unreachable("Target didn't implement TargetInstrInfo::getTrap!"); 435 } 436 437 /// getJumpInstrTableEntryBound - Get a number of bytes that suffices to hold 438 /// either the instruction returned by getUnconditionalBranch or the 439 /// instruction returned by getTrap. This only makes sense because 440 /// getUnconditionalBranch returns a single, specific instruction. This 441 /// information is needed by the jumptable construction code, since it must 442 /// decide how many bytes to use for a jumptable entry so it can generate the 443 /// right mask. 444 /// 445 /// Note that if the jumptable instruction requires alignment, then that 446 /// alignment should be factored into this required bound so that the 447 /// resulting bound gives the right alignment for the instruction. getJumpInstrTableEntryBound()448 virtual unsigned getJumpInstrTableEntryBound() const { 449 // This method gets called by LLVMTargetMachine always, so it can't fail 450 // just because there happens to be no implementation for this target. 451 // Any code that tries to use a jumptable annotation without defining 452 // getUnconditionalBranch on the appropriate Target will fail anyway, and 453 // the value returned here won't matter in that case. 454 return 0; 455 } 456 457 /// isLegalToSplitMBBAt - Return true if it's legal to split the given basic 458 /// block at the specified instruction (i.e. instruction would be the start 459 /// of a new basic block). isLegalToSplitMBBAt(MachineBasicBlock & MBB,MachineBasicBlock::iterator MBBI)460 virtual bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, 461 MachineBasicBlock::iterator MBBI) const { 462 return true; 463 } 464 465 /// isProfitableToIfCvt - Return true if it's profitable to predicate 466 /// instructions with accumulated instruction latency of "NumCycles" 467 /// of the specified basic block, where the probability of the instructions 468 /// being executed is given by Probability, and Confidence is a measure 469 /// of our confidence that it will be properly predicted. 470 virtual isProfitableToIfCvt(MachineBasicBlock & MBB,unsigned NumCycles,unsigned ExtraPredCycles,const BranchProbability & Probability)471 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, 472 unsigned ExtraPredCycles, 473 const BranchProbability &Probability) const { 474 return false; 475 } 476 477 /// isProfitableToIfCvt - Second variant of isProfitableToIfCvt, this one 478 /// checks for the case where two basic blocks from true and false path 479 /// of a if-then-else (diamond) are predicated on mutally exclusive 480 /// predicates, where the probability of the true path being taken is given 481 /// by Probability, and Confidence is a measure of our confidence that it 482 /// will be properly predicted. 483 virtual bool isProfitableToIfCvt(MachineBasicBlock & TMBB,unsigned NumTCycles,unsigned ExtraTCycles,MachineBasicBlock & FMBB,unsigned NumFCycles,unsigned ExtraFCycles,const BranchProbability & Probability)484 isProfitableToIfCvt(MachineBasicBlock &TMBB, 485 unsigned NumTCycles, unsigned ExtraTCycles, 486 MachineBasicBlock &FMBB, 487 unsigned NumFCycles, unsigned ExtraFCycles, 488 const BranchProbability &Probability) const { 489 return false; 490 } 491 492 /// isProfitableToDupForIfCvt - Return true if it's profitable for 493 /// if-converter to duplicate instructions of specified accumulated 494 /// instruction latencies in the specified MBB to enable if-conversion. 495 /// The probability of the instructions being executed is given by 496 /// Probability, and Confidence is a measure of our confidence that it 497 /// will be properly predicted. 498 virtual bool isProfitableToDupForIfCvt(MachineBasicBlock & MBB,unsigned NumCycles,const BranchProbability & Probability)499 isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, 500 const BranchProbability &Probability) const { 501 return false; 502 } 503 504 /// isProfitableToUnpredicate - Return true if it's profitable to unpredicate 505 /// one side of a 'diamond', i.e. two sides of if-else predicated on mutually 506 /// exclusive predicates. 507 /// e.g. 508 /// subeq r0, r1, #1 509 /// addne r0, r1, #1 510 /// => 511 /// sub r0, r1, #1 512 /// addne r0, r1, #1 513 /// 514 /// This may be profitable is conditional instructions are always executed. isProfitableToUnpredicate(MachineBasicBlock & TMBB,MachineBasicBlock & FMBB)515 virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, 516 MachineBasicBlock &FMBB) const { 517 return false; 518 } 519 520 /// canInsertSelect - Return true if it is possible to insert a select 521 /// instruction that chooses between TrueReg and FalseReg based on the 522 /// condition code in Cond. 523 /// 524 /// When successful, also return the latency in cycles from TrueReg, 525 /// FalseReg, and Cond to the destination register. In most cases, a select 526 /// instruction will be 1 cycle, so CondCycles = TrueCycles = FalseCycles = 1 527 /// 528 /// Some x86 implementations have 2-cycle cmov instructions. 529 /// 530 /// @param MBB Block where select instruction would be inserted. 531 /// @param Cond Condition returned by AnalyzeBranch. 532 /// @param TrueReg Virtual register to select when Cond is true. 533 /// @param FalseReg Virtual register to select when Cond is false. 534 /// @param CondCycles Latency from Cond+Branch to select output. 535 /// @param TrueCycles Latency from TrueReg to select output. 536 /// @param FalseCycles Latency from FalseReg to select output. canInsertSelect(const MachineBasicBlock & MBB,const SmallVectorImpl<MachineOperand> & Cond,unsigned TrueReg,unsigned FalseReg,int & CondCycles,int & TrueCycles,int & FalseCycles)537 virtual bool canInsertSelect(const MachineBasicBlock &MBB, 538 const SmallVectorImpl<MachineOperand> &Cond, 539 unsigned TrueReg, unsigned FalseReg, 540 int &CondCycles, 541 int &TrueCycles, int &FalseCycles) const { 542 return false; 543 } 544 545 /// insertSelect - Insert a select instruction into MBB before I that will 546 /// copy TrueReg to DstReg when Cond is true, and FalseReg to DstReg when 547 /// Cond is false. 548 /// 549 /// This function can only be called after canInsertSelect() returned true. 550 /// The condition in Cond comes from AnalyzeBranch, and it can be assumed 551 /// that the same flags or registers required by Cond are available at the 552 /// insertion point. 553 /// 554 /// @param MBB Block where select instruction should be inserted. 555 /// @param I Insertion point. 556 /// @param DL Source location for debugging. 557 /// @param DstReg Virtual register to be defined by select instruction. 558 /// @param Cond Condition as computed by AnalyzeBranch. 559 /// @param TrueReg Virtual register to copy when Cond is true. 560 /// @param FalseReg Virtual register to copy when Cons is false. insertSelect(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,DebugLoc DL,unsigned DstReg,const SmallVectorImpl<MachineOperand> & Cond,unsigned TrueReg,unsigned FalseReg)561 virtual void insertSelect(MachineBasicBlock &MBB, 562 MachineBasicBlock::iterator I, DebugLoc DL, 563 unsigned DstReg, 564 const SmallVectorImpl<MachineOperand> &Cond, 565 unsigned TrueReg, unsigned FalseReg) const { 566 llvm_unreachable("Target didn't implement TargetInstrInfo::insertSelect!"); 567 } 568 569 /// analyzeSelect - Analyze the given select instruction, returning true if 570 /// it cannot be understood. It is assumed that MI->isSelect() is true. 571 /// 572 /// When successful, return the controlling condition and the operands that 573 /// determine the true and false result values. 574 /// 575 /// Result = SELECT Cond, TrueOp, FalseOp 576 /// 577 /// Some targets can optimize select instructions, for example by predicating 578 /// the instruction defining one of the operands. Such targets should set 579 /// Optimizable. 580 /// 581 /// @param MI Select instruction to analyze. 582 /// @param Cond Condition controlling the select. 583 /// @param TrueOp Operand number of the value selected when Cond is true. 584 /// @param FalseOp Operand number of the value selected when Cond is false. 585 /// @param Optimizable Returned as true if MI is optimizable. 586 /// @returns False on success. analyzeSelect(const MachineInstr * MI,SmallVectorImpl<MachineOperand> & Cond,unsigned & TrueOp,unsigned & FalseOp,bool & Optimizable)587 virtual bool analyzeSelect(const MachineInstr *MI, 588 SmallVectorImpl<MachineOperand> &Cond, 589 unsigned &TrueOp, unsigned &FalseOp, 590 bool &Optimizable) const { 591 assert(MI && MI->getDesc().isSelect() && "MI must be a select instruction"); 592 return true; 593 } 594 595 /// optimizeSelect - Given a select instruction that was understood by 596 /// analyzeSelect and returned Optimizable = true, attempt to optimize MI by 597 /// merging it with one of its operands. Returns NULL on failure. 598 /// 599 /// When successful, returns the new select instruction. The client is 600 /// responsible for deleting MI. 601 /// 602 /// If both sides of the select can be optimized, PreferFalse is used to pick 603 /// a side. 604 /// 605 /// @param MI Optimizable select instruction. 606 /// @param NewMIs Set that record all MIs in the basic block up to \p 607 /// MI. Has to be updated with any newly created MI or deleted ones. 608 /// @param PreferFalse Try to optimize FalseOp instead of TrueOp. 609 /// @returns Optimized instruction or NULL. 610 virtual MachineInstr *optimizeSelect(MachineInstr *MI, 611 SmallPtrSetImpl<MachineInstr *> &NewMIs, 612 bool PreferFalse = false) const { 613 // This function must be implemented if Optimizable is ever set. 614 llvm_unreachable("Target must implement TargetInstrInfo::optimizeSelect!"); 615 } 616 617 /// copyPhysReg - Emit instructions to copy a pair of physical registers. 618 /// 619 /// This function should support copies within any legal register class as 620 /// well as any cross-class copies created during instruction selection. 621 /// 622 /// The source and destination registers may overlap, which may require a 623 /// careful implementation when multiple copy instructions are required for 624 /// large registers. See for example the ARM target. copyPhysReg(MachineBasicBlock & MBB,MachineBasicBlock::iterator MI,DebugLoc DL,unsigned DestReg,unsigned SrcReg,bool KillSrc)625 virtual void copyPhysReg(MachineBasicBlock &MBB, 626 MachineBasicBlock::iterator MI, DebugLoc DL, 627 unsigned DestReg, unsigned SrcReg, 628 bool KillSrc) const { 629 llvm_unreachable("Target didn't implement TargetInstrInfo::copyPhysReg!"); 630 } 631 632 /// storeRegToStackSlot - Store the specified register of the given register 633 /// class to the specified stack frame index. The store instruction is to be 634 /// added to the given machine basic block before the specified machine 635 /// instruction. If isKill is true, the register operand is the last use and 636 /// must be marked kill. storeRegToStackSlot(MachineBasicBlock & MBB,MachineBasicBlock::iterator MI,unsigned SrcReg,bool isKill,int FrameIndex,const TargetRegisterClass * RC,const TargetRegisterInfo * TRI)637 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 638 MachineBasicBlock::iterator MI, 639 unsigned SrcReg, bool isKill, int FrameIndex, 640 const TargetRegisterClass *RC, 641 const TargetRegisterInfo *TRI) const { 642 llvm_unreachable("Target didn't implement " 643 "TargetInstrInfo::storeRegToStackSlot!"); 644 } 645 646 /// loadRegFromStackSlot - Load the specified register of the given register 647 /// class from the specified stack frame index. The load instruction is to be 648 /// added to the given machine basic block before the specified machine 649 /// instruction. loadRegFromStackSlot(MachineBasicBlock & MBB,MachineBasicBlock::iterator MI,unsigned DestReg,int FrameIndex,const TargetRegisterClass * RC,const TargetRegisterInfo * TRI)650 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 651 MachineBasicBlock::iterator MI, 652 unsigned DestReg, int FrameIndex, 653 const TargetRegisterClass *RC, 654 const TargetRegisterInfo *TRI) const { 655 llvm_unreachable("Target didn't implement " 656 "TargetInstrInfo::loadRegFromStackSlot!"); 657 } 658 659 /// expandPostRAPseudo - This function is called for all pseudo instructions 660 /// that remain after register allocation. Many pseudo instructions are 661 /// created to help register allocation. This is the place to convert them 662 /// into real instructions. The target can edit MI in place, or it can insert 663 /// new instructions and erase MI. The function should return true if 664 /// anything was changed. expandPostRAPseudo(MachineBasicBlock::iterator MI)665 virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const { 666 return false; 667 } 668 669 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack 670 /// slot into the specified machine instruction for the specified operand(s). 671 /// If this is possible, a new instruction is returned with the specified 672 /// operand folded, otherwise NULL is returned. 673 /// The new instruction is inserted before MI, and the client is responsible 674 /// for removing the old instruction. 675 MachineInstr* foldMemoryOperand(MachineBasicBlock::iterator MI, 676 const SmallVectorImpl<unsigned> &Ops, 677 int FrameIndex) const; 678 679 /// foldMemoryOperand - Same as the previous version except it allows folding 680 /// of any load and store from / to any address, not just from a specific 681 /// stack slot. 682 MachineInstr* foldMemoryOperand(MachineBasicBlock::iterator MI, 683 const SmallVectorImpl<unsigned> &Ops, 684 MachineInstr* LoadMI) const; 685 686 /// hasPattern - return true when there is potentially a faster code sequence 687 /// for an instruction chain ending in \p Root. All potential pattern are 688 /// returned in the \p Pattern vector. Pattern should be sorted in priority 689 /// order since the pattern evaluator stops checking as soon as it finds a 690 /// faster sequence. 691 /// \param Root - Instruction that could be combined with one of its operands 692 /// \param Pattern - Vector of possible combination pattern 693 hasPattern(MachineInstr & Root,SmallVectorImpl<MachineCombinerPattern::MC_PATTERN> & Pattern)694 virtual bool hasPattern( 695 MachineInstr &Root, 696 SmallVectorImpl<MachineCombinerPattern::MC_PATTERN> &Pattern) const { 697 return false; 698 } 699 700 /// genAlternativeCodeSequence - when hasPattern() finds a pattern this 701 /// function generates the instructions that could replace the original code 702 /// sequence. The client has to decide whether the actual replacementment is 703 /// beneficial or not. 704 /// \param Root - Instruction that could be combined with one of its operands 705 /// \param P - Combination pattern for Root 706 /// \param InsInstrs - Vector of new instructions that implement P 707 /// \param DelInstrs - Old instructions, including Root, that could be replaced 708 /// by InsInstr 709 /// \param InstrIdxForVirtReg - map of virtual register to instruction in 710 /// InsInstr that defines it genAlternativeCodeSequence(MachineInstr & Root,MachineCombinerPattern::MC_PATTERN P,SmallVectorImpl<MachineInstr * > & InsInstrs,SmallVectorImpl<MachineInstr * > & DelInstrs,DenseMap<unsigned,unsigned> & InstrIdxForVirtReg)711 virtual void genAlternativeCodeSequence( 712 MachineInstr &Root, MachineCombinerPattern::MC_PATTERN P, 713 SmallVectorImpl<MachineInstr *> &InsInstrs, 714 SmallVectorImpl<MachineInstr *> &DelInstrs, 715 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const { 716 return; 717 } 718 719 /// useMachineCombiner - return true when a target supports MachineCombiner useMachineCombiner()720 virtual bool useMachineCombiner() const { return false; } 721 722 protected: 723 /// foldMemoryOperandImpl - Target-dependent implementation for 724 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 725 /// take care of adding a MachineMemOperand to the newly created instruction. foldMemoryOperandImpl(MachineFunction & MF,MachineInstr * MI,const SmallVectorImpl<unsigned> & Ops,int FrameIndex)726 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 727 MachineInstr* MI, 728 const SmallVectorImpl<unsigned> &Ops, 729 int FrameIndex) const { 730 return nullptr; 731 } 732 733 /// foldMemoryOperandImpl - Target-dependent implementation for 734 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 735 /// take care of adding a MachineMemOperand to the newly created instruction. foldMemoryOperandImpl(MachineFunction & MF,MachineInstr * MI,const SmallVectorImpl<unsigned> & Ops,MachineInstr * LoadMI)736 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 737 MachineInstr* MI, 738 const SmallVectorImpl<unsigned> &Ops, 739 MachineInstr* LoadMI) const { 740 return nullptr; 741 } 742 743 /// \brief Target-dependent implementation of getRegSequenceInputs. 744 /// 745 /// \returns true if it is possible to build the equivalent 746 /// REG_SEQUENCE inputs with the pair \p MI, \p DefIdx. False otherwise. 747 /// 748 /// \pre MI.isRegSequenceLike(). 749 /// 750 /// \see TargetInstrInfo::getRegSequenceInputs. getRegSequenceLikeInputs(const MachineInstr & MI,unsigned DefIdx,SmallVectorImpl<RegSubRegPairAndIdx> & InputRegs)751 virtual bool getRegSequenceLikeInputs( 752 const MachineInstr &MI, unsigned DefIdx, 753 SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const { 754 return false; 755 } 756 757 /// \brief Target-dependent implementation of getExtractSubregInputs. 758 /// 759 /// \returns true if it is possible to build the equivalent 760 /// EXTRACT_SUBREG inputs with the pair \p MI, \p DefIdx. False otherwise. 761 /// 762 /// \pre MI.isExtractSubregLike(). 763 /// 764 /// \see TargetInstrInfo::getExtractSubregInputs. getExtractSubregLikeInputs(const MachineInstr & MI,unsigned DefIdx,RegSubRegPairAndIdx & InputReg)765 virtual bool getExtractSubregLikeInputs( 766 const MachineInstr &MI, unsigned DefIdx, 767 RegSubRegPairAndIdx &InputReg) const { 768 return false; 769 } 770 771 /// \brief Target-dependent implementation of getInsertSubregInputs. 772 /// 773 /// \returns true if it is possible to build the equivalent 774 /// INSERT_SUBREG inputs with the pair \p MI, \p DefIdx. False otherwise. 775 /// 776 /// \pre MI.isInsertSubregLike(). 777 /// 778 /// \see TargetInstrInfo::getInsertSubregInputs. 779 virtual bool getInsertSubregLikeInputs(const MachineInstr & MI,unsigned DefIdx,RegSubRegPair & BaseReg,RegSubRegPairAndIdx & InsertedReg)780 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, 781 RegSubRegPair &BaseReg, 782 RegSubRegPairAndIdx &InsertedReg) const { 783 return false; 784 } 785 786 public: 787 /// canFoldMemoryOperand - Returns true for the specified load / store if 788 /// folding is possible. 789 virtual 790 bool canFoldMemoryOperand(const MachineInstr *MI, 791 const SmallVectorImpl<unsigned> &Ops) const; 792 793 /// unfoldMemoryOperand - Separate a single instruction which folded a load or 794 /// a store or a load and a store into two or more instruction. If this is 795 /// possible, returns true as well as the new instructions by reference. unfoldMemoryOperand(MachineFunction & MF,MachineInstr * MI,unsigned Reg,bool UnfoldLoad,bool UnfoldStore,SmallVectorImpl<MachineInstr * > & NewMIs)796 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 797 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 798 SmallVectorImpl<MachineInstr*> &NewMIs) const{ 799 return false; 800 } 801 unfoldMemoryOperand(SelectionDAG & DAG,SDNode * N,SmallVectorImpl<SDNode * > & NewNodes)802 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 803 SmallVectorImpl<SDNode*> &NewNodes) const { 804 return false; 805 } 806 807 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 808 /// instruction after load / store are unfolded from an instruction of the 809 /// specified opcode. It returns zero if the specified unfolding is not 810 /// possible. If LoadRegIndex is non-null, it is filled in with the operand 811 /// index of the operand which will hold the register holding the loaded 812 /// value. 813 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 814 bool UnfoldLoad, bool UnfoldStore, 815 unsigned *LoadRegIndex = nullptr) const { 816 return 0; 817 } 818 819 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler 820 /// to determine if two loads are loading from the same base address. It 821 /// should only return true if the base pointers are the same and the 822 /// only differences between the two addresses are the offset. It also returns 823 /// the offsets by reference. areLoadsFromSameBasePtr(SDNode * Load1,SDNode * Load2,int64_t & Offset1,int64_t & Offset2)824 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 825 int64_t &Offset1, int64_t &Offset2) const { 826 return false; 827 } 828 829 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 830 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should 831 /// be scheduled togther. On some targets if two loads are loading from 832 /// addresses in the same cache line, it's better if they are scheduled 833 /// together. This function takes two integers that represent the load offsets 834 /// from the common base address. It returns true if it decides it's desirable 835 /// to schedule the two loads together. "NumLoads" is the number of loads that 836 /// have already been scheduled after Load1. shouldScheduleLoadsNear(SDNode * Load1,SDNode * Load2,int64_t Offset1,int64_t Offset2,unsigned NumLoads)837 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 838 int64_t Offset1, int64_t Offset2, 839 unsigned NumLoads) const { 840 return false; 841 } 842 843 /// \brief Get the base register and byte offset of a load/store instr. getLdStBaseRegImmOfs(MachineInstr * LdSt,unsigned & BaseReg,unsigned & Offset,const TargetRegisterInfo * TRI)844 virtual bool getLdStBaseRegImmOfs(MachineInstr *LdSt, 845 unsigned &BaseReg, unsigned &Offset, 846 const TargetRegisterInfo *TRI) const { 847 return false; 848 } 849 enableClusterLoads()850 virtual bool enableClusterLoads() const { return false; } 851 shouldClusterLoads(MachineInstr * FirstLdSt,MachineInstr * SecondLdSt,unsigned NumLoads)852 virtual bool shouldClusterLoads(MachineInstr *FirstLdSt, 853 MachineInstr *SecondLdSt, 854 unsigned NumLoads) const { 855 return false; 856 } 857 858 /// \brief Can this target fuse the given instructions if they are scheduled 859 /// adjacent. shouldScheduleAdjacent(MachineInstr * First,MachineInstr * Second)860 virtual bool shouldScheduleAdjacent(MachineInstr* First, 861 MachineInstr *Second) const { 862 return false; 863 } 864 865 /// ReverseBranchCondition - Reverses the branch condition of the specified 866 /// condition list, returning false on success and true if it cannot be 867 /// reversed. 868 virtual ReverseBranchCondition(SmallVectorImpl<MachineOperand> & Cond)869 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 870 return true; 871 } 872 873 /// insertNoop - Insert a noop into the instruction stream at the specified 874 /// point. 875 virtual void insertNoop(MachineBasicBlock &MBB, 876 MachineBasicBlock::iterator MI) const; 877 878 879 /// Return the noop instruction to use for a noop. 880 virtual void getNoopForMachoTarget(MCInst &NopInst) const; 881 882 883 /// isPredicated - Returns true if the instruction is already predicated. 884 /// isPredicated(const MachineInstr * MI)885 virtual bool isPredicated(const MachineInstr *MI) const { 886 return false; 887 } 888 889 /// isUnpredicatedTerminator - Returns true if the instruction is a 890 /// terminator instruction that has not been predicated. 891 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const; 892 893 /// PredicateInstruction - Convert the instruction into a predicated 894 /// instruction. It returns true if the operation was successful. 895 virtual 896 bool PredicateInstruction(MachineInstr *MI, 897 const SmallVectorImpl<MachineOperand> &Pred) const; 898 899 /// SubsumesPredicate - Returns true if the first specified predicate 900 /// subsumes the second, e.g. GE subsumes GT. 901 virtual SubsumesPredicate(const SmallVectorImpl<MachineOperand> & Pred1,const SmallVectorImpl<MachineOperand> & Pred2)902 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 903 const SmallVectorImpl<MachineOperand> &Pred2) const { 904 return false; 905 } 906 907 /// DefinesPredicate - If the specified instruction defines any predicate 908 /// or condition code register(s) used for predication, returns true as well 909 /// as the definition predicate(s) by reference. DefinesPredicate(MachineInstr * MI,std::vector<MachineOperand> & Pred)910 virtual bool DefinesPredicate(MachineInstr *MI, 911 std::vector<MachineOperand> &Pred) const { 912 return false; 913 } 914 915 /// isPredicable - Return true if the specified instruction can be predicated. 916 /// By default, this returns true for every instruction with a 917 /// PredicateOperand. isPredicable(MachineInstr * MI)918 virtual bool isPredicable(MachineInstr *MI) const { 919 return MI->getDesc().isPredicable(); 920 } 921 922 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine 923 /// instruction that defines the specified register class. isSafeToMoveRegClassDefs(const TargetRegisterClass * RC)924 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { 925 return true; 926 } 927 928 /// isSchedulingBoundary - Test if the given instruction should be 929 /// considered a scheduling boundary. This primarily includes labels and 930 /// terminators. 931 virtual bool isSchedulingBoundary(const MachineInstr *MI, 932 const MachineBasicBlock *MBB, 933 const MachineFunction &MF) const; 934 935 /// Measure the specified inline asm to determine an approximation of its 936 /// length. 937 virtual unsigned getInlineAsmLength(const char *Str, 938 const MCAsmInfo &MAI) const; 939 940 /// CreateTargetHazardRecognizer - Allocate and return a hazard recognizer to 941 /// use for this target when scheduling the machine instructions before 942 /// register allocation. 943 virtual ScheduleHazardRecognizer* 944 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, 945 const ScheduleDAG *DAG) const; 946 947 /// CreateTargetMIHazardRecognizer - Allocate and return a hazard recognizer 948 /// to use for this target when scheduling the machine instructions before 949 /// register allocation. 950 virtual ScheduleHazardRecognizer* 951 CreateTargetMIHazardRecognizer(const InstrItineraryData*, 952 const ScheduleDAG *DAG) const; 953 954 /// CreateTargetPostRAHazardRecognizer - Allocate and return a hazard 955 /// recognizer to use for this target when scheduling the machine instructions 956 /// after register allocation. 957 virtual ScheduleHazardRecognizer* 958 CreateTargetPostRAHazardRecognizer(const InstrItineraryData*, 959 const ScheduleDAG *DAG) const; 960 961 /// Provide a global flag for disabling the PreRA hazard recognizer that 962 /// targets may choose to honor. 963 bool usePreRAHazardRecognizer() const; 964 965 /// analyzeCompare - For a comparison instruction, return the source registers 966 /// in SrcReg and SrcReg2 if having two register operands, and the value it 967 /// compares against in CmpValue. Return true if the comparison instruction 968 /// can be analyzed. analyzeCompare(const MachineInstr * MI,unsigned & SrcReg,unsigned & SrcReg2,int & Mask,int & Value)969 virtual bool analyzeCompare(const MachineInstr *MI, 970 unsigned &SrcReg, unsigned &SrcReg2, 971 int &Mask, int &Value) const { 972 return false; 973 } 974 975 /// optimizeCompareInstr - See if the comparison instruction can be converted 976 /// into something more efficient. E.g., on ARM most instructions can set the 977 /// flags register, obviating the need for a separate CMP. optimizeCompareInstr(MachineInstr * CmpInstr,unsigned SrcReg,unsigned SrcReg2,int Mask,int Value,const MachineRegisterInfo * MRI)978 virtual bool optimizeCompareInstr(MachineInstr *CmpInstr, 979 unsigned SrcReg, unsigned SrcReg2, 980 int Mask, int Value, 981 const MachineRegisterInfo *MRI) const { 982 return false; 983 } optimizeCondBranch(MachineInstr * MI)984 virtual bool optimizeCondBranch(MachineInstr *MI) const { return false; } 985 986 /// optimizeLoadInstr - Try to remove the load by folding it to a register 987 /// operand at the use. We fold the load instructions if and only if the 988 /// def and use are in the same BB. We only look at one load and see 989 /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register 990 /// defined by the load we are trying to fold. DefMI returns the machine 991 /// instruction that defines FoldAsLoadDefReg, and the function returns 992 /// the machine instruction generated due to folding. optimizeLoadInstr(MachineInstr * MI,const MachineRegisterInfo * MRI,unsigned & FoldAsLoadDefReg,MachineInstr * & DefMI)993 virtual MachineInstr* optimizeLoadInstr(MachineInstr *MI, 994 const MachineRegisterInfo *MRI, 995 unsigned &FoldAsLoadDefReg, 996 MachineInstr *&DefMI) const { 997 return nullptr; 998 } 999 1000 /// FoldImmediate - 'Reg' is known to be defined by a move immediate 1001 /// instruction, try to fold the immediate into the use instruction. 1002 /// If MRI->hasOneNonDBGUse(Reg) is true, and this function returns true, 1003 /// then the caller may assume that DefMI has been erased from its parent 1004 /// block. The caller may assume that it will not be erased by this 1005 /// function otherwise. FoldImmediate(MachineInstr * UseMI,MachineInstr * DefMI,unsigned Reg,MachineRegisterInfo * MRI)1006 virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, 1007 unsigned Reg, MachineRegisterInfo *MRI) const { 1008 return false; 1009 } 1010 1011 /// getNumMicroOps - Return the number of u-operations the given machine 1012 /// instruction will be decoded to on the target cpu. The itinerary's 1013 /// IssueWidth is the number of microops that can be dispatched each 1014 /// cycle. An instruction with zero microops takes no dispatch resources. 1015 virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData, 1016 const MachineInstr *MI) const; 1017 1018 /// isZeroCost - Return true for pseudo instructions that don't consume any 1019 /// machine resources in their current form. These are common cases that the 1020 /// scheduler should consider free, rather than conservatively handling them 1021 /// as instructions with no itinerary. isZeroCost(unsigned Opcode)1022 bool isZeroCost(unsigned Opcode) const { 1023 return Opcode <= TargetOpcode::COPY; 1024 } 1025 1026 virtual int getOperandLatency(const InstrItineraryData *ItinData, 1027 SDNode *DefNode, unsigned DefIdx, 1028 SDNode *UseNode, unsigned UseIdx) const; 1029 1030 /// getOperandLatency - Compute and return the use operand latency of a given 1031 /// pair of def and use. 1032 /// In most cases, the static scheduling itinerary was enough to determine the 1033 /// operand latency. But it may not be possible for instructions with variable 1034 /// number of defs / uses. 1035 /// 1036 /// This is a raw interface to the itinerary that may be directly overriden by 1037 /// a target. Use computeOperandLatency to get the best estimate of latency. 1038 virtual int getOperandLatency(const InstrItineraryData *ItinData, 1039 const MachineInstr *DefMI, unsigned DefIdx, 1040 const MachineInstr *UseMI, 1041 unsigned UseIdx) const; 1042 1043 /// computeOperandLatency - Compute and return the latency of the given data 1044 /// dependent def and use when the operand indices are already known. 1045 unsigned computeOperandLatency(const InstrItineraryData *ItinData, 1046 const MachineInstr *DefMI, unsigned DefIdx, 1047 const MachineInstr *UseMI, unsigned UseIdx) 1048 const; 1049 1050 /// getInstrLatency - Compute the instruction latency of a given instruction. 1051 /// If the instruction has higher cost when predicated, it's returned via 1052 /// PredCost. 1053 virtual unsigned getInstrLatency(const InstrItineraryData *ItinData, 1054 const MachineInstr *MI, 1055 unsigned *PredCost = nullptr) const; 1056 1057 virtual unsigned getPredicationCost(const MachineInstr *MI) const; 1058 1059 virtual int getInstrLatency(const InstrItineraryData *ItinData, 1060 SDNode *Node) const; 1061 1062 /// Return the default expected latency for a def based on it's opcode. 1063 unsigned defaultDefLatency(const MCSchedModel &SchedModel, 1064 const MachineInstr *DefMI) const; 1065 1066 int computeDefOperandLatency(const InstrItineraryData *ItinData, 1067 const MachineInstr *DefMI) const; 1068 1069 /// isHighLatencyDef - Return true if this opcode has high latency to its 1070 /// result. isHighLatencyDef(int opc)1071 virtual bool isHighLatencyDef(int opc) const { return false; } 1072 1073 /// hasHighOperandLatency - Compute operand latency between a def of 'Reg' 1074 /// and an use in the current loop, return true if the target considered 1075 /// it 'high'. This is used by optimization passes such as machine LICM to 1076 /// determine whether it makes sense to hoist an instruction out even in 1077 /// high register pressure situation. 1078 virtual hasHighOperandLatency(const InstrItineraryData * ItinData,const MachineRegisterInfo * MRI,const MachineInstr * DefMI,unsigned DefIdx,const MachineInstr * UseMI,unsigned UseIdx)1079 bool hasHighOperandLatency(const InstrItineraryData *ItinData, 1080 const MachineRegisterInfo *MRI, 1081 const MachineInstr *DefMI, unsigned DefIdx, 1082 const MachineInstr *UseMI, unsigned UseIdx) const { 1083 return false; 1084 } 1085 1086 /// hasLowDefLatency - Compute operand latency of a def of 'Reg', return true 1087 /// if the target considered it 'low'. 1088 virtual 1089 bool hasLowDefLatency(const InstrItineraryData *ItinData, 1090 const MachineInstr *DefMI, unsigned DefIdx) const; 1091 1092 /// verifyInstruction - Perform target specific instruction verification. 1093 virtual verifyInstruction(const MachineInstr * MI,StringRef & ErrInfo)1094 bool verifyInstruction(const MachineInstr *MI, StringRef &ErrInfo) const { 1095 return true; 1096 } 1097 1098 /// getExecutionDomain - Return the current execution domain and bit mask of 1099 /// possible domains for instruction. 1100 /// 1101 /// Some micro-architectures have multiple execution domains, and multiple 1102 /// opcodes that perform the same operation in different domains. For 1103 /// example, the x86 architecture provides the por, orps, and orpd 1104 /// instructions that all do the same thing. There is a latency penalty if a 1105 /// register is written in one domain and read in another. 1106 /// 1107 /// This function returns a pair (domain, mask) containing the execution 1108 /// domain of MI, and a bit mask of possible domains. The setExecutionDomain 1109 /// function can be used to change the opcode to one of the domains in the 1110 /// bit mask. Instructions whose execution domain can't be changed should 1111 /// return a 0 mask. 1112 /// 1113 /// The execution domain numbers don't have any special meaning except domain 1114 /// 0 is used for instructions that are not associated with any interesting 1115 /// execution domain. 1116 /// 1117 virtual std::pair<uint16_t, uint16_t> getExecutionDomain(const MachineInstr * MI)1118 getExecutionDomain(const MachineInstr *MI) const { 1119 return std::make_pair(0, 0); 1120 } 1121 1122 /// setExecutionDomain - Change the opcode of MI to execute in Domain. 1123 /// 1124 /// The bit (1 << Domain) must be set in the mask returned from 1125 /// getExecutionDomain(MI). 1126 /// setExecutionDomain(MachineInstr * MI,unsigned Domain)1127 virtual void setExecutionDomain(MachineInstr *MI, unsigned Domain) const {} 1128 1129 1130 /// getPartialRegUpdateClearance - Returns the preferred minimum clearance 1131 /// before an instruction with an unwanted partial register update. 1132 /// 1133 /// Some instructions only write part of a register, and implicitly need to 1134 /// read the other parts of the register. This may cause unwanted stalls 1135 /// preventing otherwise unrelated instructions from executing in parallel in 1136 /// an out-of-order CPU. 1137 /// 1138 /// For example, the x86 instruction cvtsi2ss writes its result to bits 1139 /// [31:0] of the destination xmm register. Bits [127:32] are unaffected, so 1140 /// the instruction needs to wait for the old value of the register to become 1141 /// available: 1142 /// 1143 /// addps %xmm1, %xmm0 1144 /// movaps %xmm0, (%rax) 1145 /// cvtsi2ss %rbx, %xmm0 1146 /// 1147 /// In the code above, the cvtsi2ss instruction needs to wait for the addps 1148 /// instruction before it can issue, even though the high bits of %xmm0 1149 /// probably aren't needed. 1150 /// 1151 /// This hook returns the preferred clearance before MI, measured in 1152 /// instructions. Other defs of MI's operand OpNum are avoided in the last N 1153 /// instructions before MI. It should only return a positive value for 1154 /// unwanted dependencies. If the old bits of the defined register have 1155 /// useful values, or if MI is determined to otherwise read the dependency, 1156 /// the hook should return 0. 1157 /// 1158 /// The unwanted dependency may be handled by: 1159 /// 1160 /// 1. Allocating the same register for an MI def and use. That makes the 1161 /// unwanted dependency identical to a required dependency. 1162 /// 1163 /// 2. Allocating a register for the def that has no defs in the previous N 1164 /// instructions. 1165 /// 1166 /// 3. Calling breakPartialRegDependency() with the same arguments. This 1167 /// allows the target to insert a dependency breaking instruction. 1168 /// 1169 virtual unsigned getPartialRegUpdateClearance(const MachineInstr * MI,unsigned OpNum,const TargetRegisterInfo * TRI)1170 getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum, 1171 const TargetRegisterInfo *TRI) const { 1172 // The default implementation returns 0 for no partial register dependency. 1173 return 0; 1174 } 1175 1176 /// \brief Return the minimum clearance before an instruction that reads an 1177 /// unused register. 1178 /// 1179 /// For example, AVX instructions may copy part of an register operand into 1180 /// the unused high bits of the destination register. 1181 /// 1182 /// vcvtsi2sdq %rax, %xmm0<undef>, %xmm14 1183 /// 1184 /// In the code above, vcvtsi2sdq copies %xmm0[127:64] into %xmm14 creating a 1185 /// false dependence on any previous write to %xmm0. 1186 /// 1187 /// This hook works similarly to getPartialRegUpdateClearance, except that it 1188 /// does not take an operand index. Instead sets \p OpNum to the index of the 1189 /// unused register. getUndefRegClearance(const MachineInstr * MI,unsigned & OpNum,const TargetRegisterInfo * TRI)1190 virtual unsigned getUndefRegClearance(const MachineInstr *MI, unsigned &OpNum, 1191 const TargetRegisterInfo *TRI) const { 1192 // The default implementation returns 0 for no undef register dependency. 1193 return 0; 1194 } 1195 1196 /// breakPartialRegDependency - Insert a dependency-breaking instruction 1197 /// before MI to eliminate an unwanted dependency on OpNum. 1198 /// 1199 /// If it wasn't possible to avoid a def in the last N instructions before MI 1200 /// (see getPartialRegUpdateClearance), this hook will be called to break the 1201 /// unwanted dependency. 1202 /// 1203 /// On x86, an xorps instruction can be used as a dependency breaker: 1204 /// 1205 /// addps %xmm1, %xmm0 1206 /// movaps %xmm0, (%rax) 1207 /// xorps %xmm0, %xmm0 1208 /// cvtsi2ss %rbx, %xmm0 1209 /// 1210 /// An <imp-kill> operand should be added to MI if an instruction was 1211 /// inserted. This ties the instructions together in the post-ra scheduler. 1212 /// 1213 virtual void breakPartialRegDependency(MachineBasicBlock::iterator MI,unsigned OpNum,const TargetRegisterInfo * TRI)1214 breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum, 1215 const TargetRegisterInfo *TRI) const {} 1216 1217 /// Create machine specific model for scheduling. 1218 virtual DFAPacketizer * CreateTargetScheduleState(const TargetSubtargetInfo &)1219 CreateTargetScheduleState(const TargetSubtargetInfo &) const { 1220 return nullptr; 1221 } 1222 1223 // areMemAccessesTriviallyDisjoint - Sometimes, it is possible for the target 1224 // to tell, even without aliasing information, that two MIs access different 1225 // memory addresses. This function returns true if two MIs access different 1226 // memory addresses, and false otherwise. 1227 virtual bool 1228 areMemAccessesTriviallyDisjoint(MachineInstr *MIa, MachineInstr *MIb, 1229 AliasAnalysis *AA = nullptr) const { 1230 assert(MIa && (MIa->mayLoad() || MIa->mayStore()) && 1231 "MIa must load from or modify a memory location"); 1232 assert(MIb && (MIb->mayLoad() || MIb->mayStore()) && 1233 "MIb must load from or modify a memory location"); 1234 return false; 1235 } 1236 1237 private: 1238 int CallFrameSetupOpcode, CallFrameDestroyOpcode; 1239 }; 1240 1241 } // End llvm namespace 1242 1243 #endif 1244