1 /////////////////////////////////////////////////////////////////////////
2 // $Id: cpuid.cc 14149 2021-02-16 18:57:49Z sshwarts $
3 /////////////////////////////////////////////////////////////////////////
4 //
5 // Copyright (c) 2014-2020 Stanislav Shwartsman
6 // Written by Stanislav Shwartsman [sshwarts at sourceforge net]
7 //
8 // This library is free software; you can redistribute it and/or
9 // modify it under the terms of the GNU Lesser General Public
10 // License as published by the Free Software Foundation; either
11 // version 2 of the License, or (at your option) any later version.
12 //
13 // This library is distributed in the hope that it will be useful,
14 // but WITHOUT ANY WARRANTY; without even the implied warranty of
15 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 // Lesser General Public License for more details.
17 //
18 // You should have received a copy of the GNU Lesser General Public
19 // License along with this library; if not, write to the Free Software
20 // Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
21 //
22 /////////////////////////////////////////////////////////////////////////
23
24 #include "bochs.h"
25 #include "gui/siminterface.h"
26 #include "cpu.h"
27 #include "param_names.h"
28 #include "cpuid.h"
29
30 static const char *cpu_feature_name[] =
31 {
32 "386ni", // BX_ISA_386
33 "x87", // BX_ISA_X87
34 "486ni", // BX_ISA_486
35 "pentium_ni", // BX_ISA_PENTIUM
36 "p6ni", // BX_ISA_P6
37 "mmx", // BX_ISA_MMX
38 "3dnow!", // BX_ISA_3DNOW
39 "debugext", // BX_ISA_DEBUG_EXTENSIONS
40 "vme", // BX_ISA_VME
41 "pse", // BX_ISA_PSE
42 "pae", // BX_ISA_PAE
43 "pge", // BX_ISA_PGE
44 "pse36", // BX_ISA_PSE36
45 "mtrr", // BX_ISA_MTRR
46 "pat", // BX_ISA_PAT
47 "legacy_syscall_sysret", // BX_ISA_SYSCALL_SYSRET_LEGACY
48 "sysenter_sysexit", // BX_ISA_SYSENTER_SYSEXIT
49 "clflush", // BX_ISA_CLFLUSH
50 "clflushopt", // BX_ISA_CLFLUSHOPT
51 "clwb", // BX_ISA_CLWB
52 "cldemote", // BX_ISA_CLDEMOTE
53 "sse", // BX_ISA_SSE
54 "sse2", // BX_ISA_SSE2
55 "sse3", // BX_ISA_SSE3
56 "ssse3", // BX_ISA_SSSE3
57 "sse4_1", // BX_ISA_SSE4_1
58 "sse4_2", // BX_ISA_SSE4_2
59 "popcnt", // BX_ISA_POPCNT
60 "mwait", // BX_ISA_MONITOR_MWAIT
61 "mwaitx", // BX_ISA_MONITORX_MWAITX
62 "waitpkg", // BX_ISA_WAITPKG
63 "vmx", // BX_ISA_VMX
64 "smx", // BX_ISA_SMX
65 "longmode", // BX_ISA_LONG_MODE
66 "lm_lahf_sahf", // BX_ISA_LM_LAHF_SAHF
67 "nx", // BX_ISA_NX
68 "1g_pages", // BX_ISA_1G_PAGES
69 "cmpxhg16b", // BX_ISA_CMPXCHG16B
70 "rdtscp", // BX_ISA_RDTSCP
71 "ffxsr", // BX_ISA_FFXSR
72 "xsave", // BX_ISA_XSAVE
73 "xsaveopt", // BX_ISA_XSAVEOPT
74 "xsavec", // BX_ISA_XSAVEC
75 "xsaves", // BX_ISA_XSAVES
76 "aes_pclmulqdq", // BX_ISA_AES_PCLMULQDQ
77 "vaes_vpclmulqdq", // BX_ISA_VAES_VPCLMULQDQ
78 "movbe", // BX_ISA_MOVBE
79 "fsgsbase", // BX_ISA_FSGSBASE
80 "invpcid", // BX_ISA_INVPCID
81 "avx", // BX_ISA_AVX
82 "avx2", // BX_ISA_AVX2
83 "avx_f16c", // BX_ISA_AVX_F16C
84 "avx_fma", // BX_ISA_AVX_FMA
85 "altmovcr8", // BX_ISA_ALT_MOV_CR8
86 "sse4a", // BX_ISA_SSE4A
87 "misaligned_sse", // BX_ISA_MISALIGNED_SSE
88 "lzcnt", // BX_ISA_LZCNT
89 "bmi1", // BX_ISA_BMI1
90 "bmi2", // BX_ISA_BMI2
91 "fma4", // BX_ISA_FMA4
92 "xop", // BX_ISA_XOP
93 "tbm", // BX_ISA_TBM
94 "svm", // BX_ISA_SVM
95 "rdrand", // BX_ISA_RDRAND
96 "adx", // BX_ISA_ADX
97 "smap", // BX_ISA_SMAP
98 "rdseed", // BX_ISA_RDSEED
99 "sha", // BX_ISA_SHA
100 "gfni", // BX_ISA_GFNI
101 "avx512", // BX_ISA_AVX512
102 "avx512cd", // BX_ISA_AVX512_CD
103 "avx512pf", // BX_ISA_AVX512_PF
104 "avx512er", // BX_ISA_AVX512_ER
105 "avx512dq", // BX_ISA_AVX512_DQ
106 "avx512bw", // BX_ISA_AVX512_BW
107 "avx512vl", // BX_ISA_AVX512_VL
108 "avx512vbmi", // BX_ISA_AVX512_VBMI
109 "avx512vbmi2", // BX_ISA_AVX512_VBMI2
110 "avx512ifma52", // BX_ISA_AVX512_IFMA52
111 "avx512vpopcnt", // BX_ISA_AVX512_VPOPCNTDQ
112 "avx512vnni", // BX_ISA_AVX512_VNNI
113 "avx512bitalg", // BX_ISA_AVX512_BITALG
114 "avx512vp2intersect", // BX_ISA_AVX512_VP2INTERSECT
115 "avx_vnni", // BX_ISA_AVX_VNNI
116 "xapic", // BX_ISA_XAPIC
117 "x2apic", // BX_ISA_X2APIC
118 "xapicext", // BX_ISA_XAPICEXT
119 "pcid", // BX_ISA_PCID
120 "smep", // BX_ISA_SMEP
121 "tsc_adjust", // BX_ISA_TSC_ADJUST
122 "tsc_deadline", // BX_ISA_TSC_DEADLINE
123 "fopcode_deprecation", // BX_ISA_FOPCODE_DEPRECATION
124 "fcs_fds_deprecation", // BX_ISA_FCS_FDS_DEPRECATION
125 "fdp_deprecation", // BX_ISA_FDP_DEPRECATION
126 "pku", // BX_ISA_PKU
127 "pks", // BX_ISA_PKS
128 "umip", // BX_ISA_UMIP
129 "rdpid", // BX_ISA_RDPID
130 "tce", // BX_ISA_TCE
131 "clzero", // BX_ISA_CLZERO
132 "sca_mitigations", // BX_ISA_SCA_MITIGATIONS
133 "cet", // BX_ISA_CET
134 };
135
get_cpu_feature_name(unsigned feature)136 const char *get_cpu_feature_name(unsigned feature) { return cpu_feature_name[feature]; }
137
138 #define LOG_THIS cpu->
bx_cpuid_t(BX_CPU_C * _cpu)139 bx_cpuid_t::bx_cpuid_t(BX_CPU_C *_cpu): cpu(_cpu)
140 {
141 init();
142 }
143
144 #if BX_SUPPORT_VMX
bx_cpuid_t(BX_CPU_C * _cpu,Bit32u vmcs_revision)145 bx_cpuid_t::bx_cpuid_t(BX_CPU_C *_cpu, Bit32u vmcs_revision):
146 cpu(_cpu), vmcs_map(vmcs_revision)
147 {
148 init();
149 }
150
bx_cpuid_t(BX_CPU_C * _cpu,Bit32u vmcs_revision,const char * filename)151 bx_cpuid_t::bx_cpuid_t(BX_CPU_C *_cpu, Bit32u vmcs_revision, const char *filename):
152 cpu(_cpu), vmcs_map(vmcs_revision, filename)
153 {
154 init();
155 }
156 #endif
157
init()158 void bx_cpuid_t::init()
159 {
160 #if BX_SUPPORT_SMP
161 nthreads = SIM->get_param_num(BXPN_CPU_NTHREADS)->get();
162 ncores = SIM->get_param_num(BXPN_CPU_NCORES)->get();
163 nprocessors = SIM->get_param_num(BXPN_CPU_NPROCESSORS)->get();
164 #else
165 nthreads = 1;
166 ncores = 1;
167 nprocessors = 1;
168 #endif
169
170 for (unsigned n=0; n < BX_ISA_EXTENSIONS_ARRAY_SIZE; n++)
171 ia_extensions_bitmask[n] = 0;
172
173 // every cpu supported by Bochs support all 386 and earlier instructions
174 ia_extensions_bitmask[0] = (1 << BX_ISA_386);
175 }
176
177 #if BX_SUPPORT_APIC
178
ilog2(Bit32u x)179 BX_CPP_INLINE static Bit32u ilog2(Bit32u x)
180 {
181 Bit32u count = 0;
182 while(x>>=1) count++;
183 return count;
184 }
185
186 // leaf 0x0000000B //
get_std_cpuid_extended_topology_leaf(Bit32u subfunction,cpuid_function_t * leaf) const187 void bx_cpuid_t::get_std_cpuid_extended_topology_leaf(Bit32u subfunction, cpuid_function_t *leaf) const
188 {
189 // CPUID function 0x0000000B - Extended Topology Leaf
190 leaf->eax = 0;
191 leaf->ebx = 0;
192 leaf->ecx = subfunction;
193 leaf->edx = cpu->get_apic_id();
194
195 #if BX_SUPPORT_SMP
196 switch(subfunction) {
197 case 0:
198 if (nthreads > 1) {
199 leaf->eax = ilog2(nthreads-1)+1;
200 leaf->ebx = nthreads;
201 leaf->ecx |= (1<<8);
202 }
203 else if (ncores > 1) {
204 leaf->eax = ilog2(ncores-1)+1;
205 leaf->ebx = ncores;
206 leaf->ecx |= (2<<8);
207 }
208 else if (nprocessors > 1) {
209 leaf->eax = ilog2(nprocessors-1)+1;
210 leaf->ebx = nprocessors;
211 }
212 else {
213 leaf->eax = 1;
214 leaf->ebx = 1; // number of logical CPUs at this level
215 }
216 break;
217
218 case 1:
219 if (nthreads > 1) {
220 if (ncores > 1) {
221 leaf->eax = ilog2(ncores-1)+1;
222 leaf->ebx = ncores;
223 leaf->ecx |= (2<<8);
224 }
225 else if (nprocessors > 1) {
226 leaf->eax = ilog2(nprocessors-1)+1;
227 leaf->ebx = nprocessors;
228 }
229 }
230 else if (ncores > 1) {
231 if (nprocessors > 1) {
232 leaf->eax = ilog2(nprocessors-1)+1;
233 leaf->ebx = nprocessors;
234 }
235 }
236 break;
237
238 case 2:
239 if (nthreads > 1) {
240 if (nprocessors > 1) {
241 leaf->eax = ilog2(nprocessors-1)+1;
242 leaf->ebx = nprocessors;
243 }
244 }
245 break;
246
247 default:
248 break;
249 }
250 #endif
251 }
252
253 #endif
254
255 #if BX_CPU_LEVEL >= 6
get_std_cpuid_xsave_leaf(Bit32u subfunction,cpuid_function_t * leaf) const256 void bx_cpuid_t::get_std_cpuid_xsave_leaf(Bit32u subfunction, cpuid_function_t *leaf) const
257 {
258 leaf->eax = 0;
259 leaf->ebx = 0;
260 leaf->ecx = 0;
261 leaf->edx = 0;
262
263 if (is_cpu_extension_supported(BX_ISA_XSAVE))
264 {
265 switch(subfunction) {
266 case 0:
267 // EAX - valid bits of XCR0 (lower part)
268 // EBX - Maximum size (in bytes) required by enabled features
269 // ECX - Maximum size (in bytes) required by CPU supported features
270 // EDX - valid bits of XCR0 (upper part)
271 leaf->eax = cpu->xcr0_suppmask;
272
273 leaf->ebx = 512+64;
274 #if BX_SUPPORT_AVX
275 if (cpu->xcr0.get_YMM())
276 leaf->ebx = XSAVE_YMM_STATE_OFFSET + XSAVE_YMM_STATE_LEN;
277 #endif
278 #if BX_SUPPORT_EVEX
279 if (cpu->xcr0.get_OPMASK())
280 leaf->ebx = XSAVE_OPMASK_STATE_OFFSET + XSAVE_OPMASK_STATE_LEN;
281 if (cpu->xcr0.get_ZMM_HI256())
282 leaf->ebx = XSAVE_ZMM_HI256_STATE_OFFSET + XSAVE_ZMM_HI256_STATE_LEN;
283 if (cpu->xcr0.get_HI_ZMM())
284 leaf->ebx = XSAVE_HI_ZMM_STATE_OFFSET + XSAVE_HI_ZMM_STATE_LEN;
285 #endif
286 #if BX_SUPPORT_PKEYS
287 if (cpu->xcr0.get_PKRU())
288 leaf->ebx = XSAVE_PKRU_STATE_OFFSET + XSAVE_PKRU_STATE_LEN;
289 #endif
290
291 leaf->ecx = 512+64;
292 #if BX_SUPPORT_AVX
293 if (cpu->xcr0_suppmask & BX_XCR0_YMM_MASK)
294 leaf->ecx = XSAVE_YMM_STATE_OFFSET + XSAVE_YMM_STATE_LEN;
295 #endif
296 #if BX_SUPPORT_EVEX
297 if (cpu->xcr0_suppmask & BX_XCR0_OPMASK_MASK)
298 leaf->ecx = XSAVE_OPMASK_STATE_OFFSET + XSAVE_OPMASK_STATE_LEN;
299 if (cpu->xcr0_suppmask & BX_XCR0_ZMM_HI256_MASK)
300 leaf->ecx = XSAVE_ZMM_HI256_STATE_OFFSET + XSAVE_ZMM_HI256_STATE_LEN;
301 if (cpu->xcr0_suppmask & BX_XCR0_HI_ZMM_MASK)
302 leaf->ecx = XSAVE_HI_ZMM_STATE_OFFSET + XSAVE_HI_ZMM_STATE_LEN;
303 #endif
304 #if BX_SUPPORT_PKEYS
305 if (cpu->xcr0_suppmask & BX_XCR0_PKRU_MASK)
306 leaf->ecx = XSAVE_PKRU_STATE_OFFSET + XSAVE_PKRU_STATE_LEN;
307 #endif
308 leaf->edx = 0;
309 break;
310
311 case 1:
312 // EAX[0] - support for the XSAVEOPT instruction
313 // EAX[1] - support for compaction extensions to the XSAVE feature set
314 // EAX[2] - support for execution of XGETBV with ECX = 1
315 // EAX[3] - support for XSAVES, XRSTORS, and the IA32_XSS MSR
316 leaf->eax = 0;
317 if (is_cpu_extension_supported(BX_ISA_XSAVEOPT))
318 leaf->eax |= 0x1;
319 if (is_cpu_extension_supported(BX_ISA_XSAVEC))
320 leaf->eax |= (1<<1) | (1<<2);
321 if (is_cpu_extension_supported(BX_ISA_XSAVES))
322 leaf->eax |= (1<<3);
323
324 // EBX[31:00] - The size (in bytes) of the XSAVE area containing all states enabled by (XCRO | IA32_XSS)
325 leaf->ebx = 0;
326 if (is_cpu_extension_supported(BX_ISA_XSAVES)) {
327 xcr0_t xcr0_xss = cpu->xcr0;
328 xcr0_xss.val32 |= cpu->msr.ia32_xss;
329 #if BX_SUPPORT_AVX
330 if (xcr0_xss.get_YMM())
331 leaf->ebx = XSAVE_YMM_STATE_OFFSET + XSAVE_YMM_STATE_LEN;
332 #endif
333 #if BX_SUPPORT_EVEX
334 if (xcr0_xss.get_OPMASK())
335 leaf->ebx = XSAVE_OPMASK_STATE_OFFSET + XSAVE_OPMASK_STATE_LEN;
336 if (xcr0_xss.get_ZMM_HI256())
337 leaf->ebx = XSAVE_ZMM_HI256_STATE_OFFSET + XSAVE_ZMM_HI256_STATE_LEN;
338 if (xcr0_xss.get_HI_ZMM())
339 leaf->ebx = XSAVE_HI_ZMM_STATE_OFFSET + XSAVE_HI_ZMM_STATE_LEN;
340 #endif
341 #if BX_SUPPORT_PKEYS
342 if (xcr0_xss.get_PKRU())
343 leaf->ebx = XSAVE_PKRU_STATE_OFFSET + XSAVE_PKRU_STATE_LEN;
344 #endif
345 }
346
347 // ECX[31:0] - Reports the supported bits of the lower 32 bits of the IA32_XSS MSR.
348 // IA32_XSS[n] can be set to 1 only if ECX[n] is 1
349 // EDX[31:0] - Reports the supported bits of the upper 32 bits of the IA32_XSS MSR.
350 // IA32_XSS[n+32] can be set to 1 only if EDX[n] is 1
351 leaf->ecx = 0;
352 #if BX_SUPPPORT_CET
353 leaf->ecx |= BX_XCR0_CET_U_MASK | BX_XCR0_CET_S_MASK;
354 #endif
355 leaf->edx = 0;
356 break;
357
358 #if BX_SUPPORT_AVX
359 case 2: // YMM leaf
360 if (cpu->xcr0_suppmask & BX_XCR0_YMM_MASK) {
361 leaf->eax = XSAVE_YMM_STATE_LEN;
362 leaf->ebx = XSAVE_YMM_STATE_OFFSET;
363 leaf->ecx = 0;
364 leaf->edx = 0;
365 }
366 break;
367 #endif
368
369 case 3: // MPX leafs (BNDREGS, BNDCFG)
370 case 4:
371 break;
372
373 #if BX_SUPPORT_EVEX
374 case 5: // OPMASK leaf
375 if (cpu->xcr0_suppmask & BX_XCR0_OPMASK_MASK) {
376 leaf->eax = XSAVE_OPMASK_STATE_LEN;
377 leaf->ebx = XSAVE_OPMASK_STATE_OFFSET;
378 leaf->ecx = 0;
379 leaf->edx = 0;
380 }
381 break;
382 case 6: // ZMM Hi256 leaf
383 if (cpu->xcr0_suppmask & BX_XCR0_ZMM_HI256_MASK) {
384 leaf->eax = XSAVE_ZMM_HI256_STATE_LEN;
385 leaf->ebx = XSAVE_ZMM_HI256_STATE_OFFSET;
386 leaf->ecx = 0;
387 leaf->edx = 0;
388 }
389 break;
390 case 7: // HI_ZMM leaf
391 if (cpu->xcr0_suppmask & BX_XCR0_HI_ZMM_MASK) {
392 leaf->eax = XSAVE_HI_ZMM_STATE_LEN;
393 leaf->ebx = XSAVE_HI_ZMM_STATE_OFFSET;
394 leaf->ecx = 0;
395 leaf->edx = 0;
396 }
397 break;
398 #endif
399
400 case 8: // Processor trace leaf
401 break;
402
403 #if BX_SUPPPORT_PKEYS
404 case 9: // Protection keys
405 if (cpu->xcr0_suppmask & BX_XCR0_PKRU_MASK) {
406 leaf->eax = XSAVE_PKRU_STATE_LEN;
407 leaf->ebx = XSAVE_PKRU_STATE_OFFSET;
408 leaf->ecx = 0;
409 leaf->edx = 0;
410 }
411 break;
412 #endif
413
414 #if BX_SUPPPORT_CET
415 case 10:
416 if (cpu->xcr0_suppmask & BX_XCR0_CET_U_MASK) {
417 leaf->eax = XSAVE_CET_U_STATE_LEN;
418 leaf->ebx = 0; // doesn't map to a valid bit in XCR0 register
419 leaf->ecx = 1; // managed through IA32_XSS register
420 leaf->edx = 0;
421 }
422 break;
423 case 11:
424 if (cpu->xcr0_suppmask & BX_XCR0_CET_S_MASK) {
425 leaf->eax = XSAVE_CET_S_STATE_LEN;
426 leaf->ebx = 0; // doesn't map to a valid bit in XCR0 register
427 leaf->ecx = 1; // managed through IA32_XSS register
428 leaf->edx = 0;
429 }
430 break;
431 #endif
432
433 }
434 }
435 }
436 #endif
437
get_leaf_0(unsigned max_leaf,const char * vendor_string,cpuid_function_t * leaf,unsigned limited_max_leaf) const438 void bx_cpuid_t::get_leaf_0(unsigned max_leaf, const char *vendor_string, cpuid_function_t *leaf, unsigned limited_max_leaf) const
439 {
440 // EAX: highest function understood by CPUID
441 // EBX: vendor ID string
442 // EDX: vendor ID string
443 // ECX: vendor ID string
444 if (max_leaf < 0x80000000 && max_leaf > 0x2) {
445 // do not limit extended CPUID leafs
446 static bool cpuid_limit_winnt = SIM->get_param_bool(BXPN_CPUID_LIMIT_WINNT)->get();
447 if (cpuid_limit_winnt)
448 max_leaf = (limited_max_leaf < 0x02) ? limited_max_leaf : 0x02;
449 }
450 leaf->eax = max_leaf;
451
452 if (vendor_string == NULL) {
453 leaf->ebx = 0;
454 leaf->ecx = 0; // Reserved
455 leaf->edx = 0;
456 return;
457 }
458
459 // CPUID vendor string (e.g. GenuineIntel, AuthenticAMD, CentaurHauls, ...)
460 memcpy(&(leaf->ebx), vendor_string, 4);
461 memcpy(&(leaf->edx), vendor_string + 4, 4);
462 memcpy(&(leaf->ecx), vendor_string + 8, 4);
463 #ifdef BX_BIG_ENDIAN
464 leaf->ebx = bx_bswap32(leaf->ebx);
465 leaf->ecx = bx_bswap32(leaf->ecx);
466 leaf->edx = bx_bswap32(leaf->edx);
467 #endif
468 }
469
get_ext_cpuid_brand_string_leaf(const char * brand_string,Bit32u function,cpuid_function_t * leaf) const470 void bx_cpuid_t::get_ext_cpuid_brand_string_leaf(const char *brand_string, Bit32u function, cpuid_function_t *leaf) const
471 {
472 switch(function) {
473 case 0x80000002:
474 memcpy(&(leaf->eax), brand_string , 4);
475 memcpy(&(leaf->ebx), brand_string + 4, 4);
476 memcpy(&(leaf->ecx), brand_string + 8, 4);
477 memcpy(&(leaf->edx), brand_string + 12, 4);
478 break;
479 case 0x80000003:
480 memcpy(&(leaf->eax), brand_string + 16, 4);
481 memcpy(&(leaf->ebx), brand_string + 20, 4);
482 memcpy(&(leaf->ecx), brand_string + 24, 4);
483 memcpy(&(leaf->edx), brand_string + 28, 4);
484 break;
485 case 0x80000004:
486 memcpy(&(leaf->eax), brand_string + 32, 4);
487 memcpy(&(leaf->ebx), brand_string + 36, 4);
488 memcpy(&(leaf->ecx), brand_string + 40, 4);
489 memcpy(&(leaf->edx), brand_string + 44, 4);
490 break;
491 default:
492 break;
493 }
494
495 #ifdef BX_BIG_ENDIAN
496 leaf->eax = bx_bswap32(leaf->eax);
497 leaf->ebx = bx_bswap32(leaf->ebx);
498 leaf->ecx = bx_bswap32(leaf->ecx);
499 leaf->edx = bx_bswap32(leaf->edx);
500 #endif
501 }
502
503 // leaf 0x00000007 - EBX
get_std_cpuid_leaf_7_ebx(Bit32u extra) const504 Bit32u bx_cpuid_t::get_std_cpuid_leaf_7_ebx(Bit32u extra) const
505 {
506 Bit32u ebx = extra;
507
508 // [0:0] FS/GS BASE access instructions
509 if (is_cpu_extension_supported(BX_ISA_FSGSBASE))
510 ebx |= BX_CPUID_EXT3_FSGSBASE;
511
512 // [1:1] Support for IA32_TSC_ADJUST MSR
513 if (is_cpu_extension_supported(BX_ISA_TSC_ADJUST))
514 ebx |= BX_CPUID_EXT3_TSC_ADJUST;
515
516 // [2:2] SGX: Intel Software Guard Extensions - not supported
517
518 // [3:3] BMI1: Advanced Bit Manipulation Extensions
519 if (is_cpu_extension_supported(BX_ISA_BMI1))
520 ebx |= BX_CPUID_EXT3_BMI1;
521
522 // [4:4] HLE: Hardware Lock Elision - not supported
523
524 // [5:5] AVX2
525 if (is_cpu_extension_supported(BX_ISA_AVX2))
526 ebx |= BX_CPUID_EXT3_AVX2;
527
528 // [6:6] FDP Deprecation
529 if (is_cpu_extension_supported(BX_ISA_FDP_DEPRECATION))
530 ebx |= BX_CPUID_EXT3_FDP_DEPRECATION;
531
532 // [7:7] SMEP: Supervisor Mode Execution Protection
533 if (is_cpu_extension_supported(BX_ISA_SMEP))
534 ebx |= BX_CPUID_EXT3_SMEP;
535
536 // [8:8] BMI2: Advanced Bit Manipulation Extensions
537 if (is_cpu_extension_supported(BX_ISA_BMI2))
538 ebx |= BX_CPUID_EXT3_BMI2;
539
540 // [9:9] Support for Enhanced REP MOVSB/STOSB - no special emulation required, could be enabled through extra
541
542 // [10:10] Support for INVPCID instruction
543 if (is_cpu_extension_supported(BX_ISA_INVPCID))
544 ebx |= BX_CPUID_EXT3_INVPCID;
545
546 // [11:11] RTM: Restricted Transactional Memory - not supported
547 // [12:12] Supports Platform Quality of Service Monitoring (PQM) capability - not supported
548
549 // [13:13] Deprecates FPU CS and FPU DS values
550 if (is_cpu_extension_supported(BX_ISA_FCS_FDS_DEPRECATION))
551 ebx |= BX_CPUID_EXT3_DEPRECATE_FCS_FDS;
552
553 // [14:14] Intel Memory Protection Extensions - not supported
554 // [15:15] Supports Platform Quality of Service Enforcement (PQE) capability - not supported
555
556 // [16:16] AVX512F instructions support
557 // [17:17] AVX512DQ instructions support
558 #if BX_SUPPORT_EVEX
559 if (is_cpu_extension_supported(BX_ISA_AVX512)) {
560 ebx |= BX_CPUID_EXT3_AVX512F;
561 if (is_cpu_extension_supported(BX_ISA_AVX512_DQ))
562 ebx |= BX_CPUID_EXT3_AVX512DQ;
563 }
564 #endif
565
566 // [18:18] RDSEED instruction support
567 if (is_cpu_extension_supported(BX_ISA_RDSEED))
568 ebx |= BX_CPUID_EXT3_RDSEED;
569
570 // [19:19] ADCX/ADOX instructions support
571 if (is_cpu_extension_supported(BX_ISA_ADX))
572 ebx |= BX_CPUID_EXT3_ADX;
573
574 // [20:20] SMAP: Supervisor Mode Access Prevention
575 if (is_cpu_extension_supported(BX_ISA_SMAP))
576 ebx |= BX_CPUID_EXT3_SMAP;
577
578 // [22:21] AVX512IFMA52 instructions support
579 #if BX_SUPPORT_EVEX
580 if (is_cpu_extension_supported(BX_ISA_AVX512)) {
581 if (is_cpu_extension_supported(BX_ISA_AVX512_IFMA52))
582 ebx |= BX_CPUID_EXT3_AVX512IFMA52;
583 }
584 #endif
585
586 // [22:22] reserved
587
588 // [23:23] CLFLUSHOPT instruction
589 // [24:24] CLWB instruction
590 if (is_cpu_extension_supported(BX_ISA_CLFLUSHOPT))
591 ebx |= BX_CPUID_EXT3_CLFLUSHOPT;
592 if (is_cpu_extension_supported(BX_ISA_CLWB))
593 ebx |= BX_CPUID_EXT3_CLWB;
594
595 // [25:25] Intel Processor Trace - not supported
596 // [26:26] AVX512PF instructions support - not supported
597 // [27:27] AVX512ER instructions support - not supported
598 // [28:28] AVX512CD instructions support
599 #if BX_SUPPORT_EVEX
600 if (is_cpu_extension_supported(BX_ISA_AVX512)) {
601 if (is_cpu_extension_supported(BX_ISA_AVX512_CD))
602 ebx |= BX_CPUID_EXT3_AVX512CD;
603 }
604 #endif
605
606 // [29:29] SHA instructions support
607 if (is_cpu_extension_supported(BX_ISA_SHA))
608 ebx |= BX_CPUID_EXT3_SHA;
609
610 // [30:30] AVX512BW instructions support
611 // [31:31] AVX512VL variable vector length support
612 if (is_cpu_extension_supported(BX_ISA_AVX512)) {
613 if (is_cpu_extension_supported(BX_ISA_AVX512_BW))
614 ebx |= BX_CPUID_EXT3_AVX512BW;
615 ebx |= BX_CPUID_EXT3_AVX512VL;
616 }
617
618 return ebx;
619 }
620
621 // leaf 0x00000007 - ECX
get_std_cpuid_leaf_7_ecx(Bit32u extra) const622 Bit32u bx_cpuid_t::get_std_cpuid_leaf_7_ecx(Bit32u extra) const
623 {
624 Bit32u ecx = extra;
625
626 // [0:0] PREFETCHW1 instruction - not supported
627
628 // [1:1] AVX512 VBMI instructions
629 #if BX_SUPPORT_EVEX
630 if (is_cpu_extension_supported(BX_ISA_AVX512)) {
631 if (is_cpu_extension_supported(BX_ISA_AVX512_VBMI))
632 ecx |= BX_CPUID_EXT4_AVX512_VBMI;
633 }
634 #endif
635
636 // [2:2] UMIP: Supports user-mode instruction prevention
637 if (is_cpu_extension_supported(BX_ISA_UMIP))
638 ecx |= BX_CPUID_EXT4_UMIP;
639
640 // [3:3] PKU: Protection keys for user-mode pages
641 // [4:4] OSPKE: OS has set CR4.PKE to enable protection keys
642 #if BX_SUPPORT_PKEYS
643 if (is_cpu_extension_supported(BX_ISA_PKU)) {
644 ecx |= BX_CPUID_EXT4_PKU;
645 if (cpu->cr4.get_PKE())
646 ecx |= BX_CPUID_EXT4_OSPKE;
647 }
648 #endif
649
650 // [5:5] WAITPKG (TPAUSE/UMONITOR/UMWAIT) support - not supported
651
652 // [6:6] AVX512 VBMI2 instructions support
653 #if BX_SUPPORT_EVEX
654 if (is_cpu_extension_supported(BX_ISA_AVX512)) {
655 if (is_cpu_extension_supported(BX_ISA_AVX512_VBMI2))
656 ecx |= BX_CPUID_EXT4_AVX512_VBMI2;
657 }
658 #endif
659
660 // [7:7] CET_SS: Support CET Shadow Stack
661 #if BX_SUPPORT_CET
662 if (is_cpu_extension_supported(BX_ISA_CET))
663 ecx |= BX_CPUID_EXT4_CET_SS;
664 #endif
665
666 // [8:8] GFNI instructions support
667 #if BX_SUPPORT_EVEX
668 if (is_cpu_extension_supported(BX_ISA_GFNI))
669 ecx |= BX_CPUID_EXT4_GFNI;
670 #endif
671
672 // [9:9] VAES instructions support
673 // [10:10] VPCLMULQDQ instruction support
674 #if BX_SUPPORT_EVEX
675 if (is_cpu_extension_supported(BX_ISA_VAES_VPCLMULQDQ))
676 ecx |= BX_CPUID_EXT4_VAES | BX_CPUID_EXT4_VPCLMULQDQ;
677 #endif
678
679 // [11:11] AVX512 VNNI instructions support
680 // [12:12] AVX512 BITALG instructions support
681 // [13:13] reserved
682 // [14:14] AVX512 VPOPCNTDQ: AVX512 VPOPCNTD/VPOPCNTQ instructions
683 #if BX_SUPPORT_EVEX
684 if (is_cpu_extension_supported(BX_ISA_AVX512)) {
685 if (is_cpu_extension_supported(BX_ISA_AVX512_VNNI))
686 ecx |= BX_CPUID_EXT4_AVX512_VNNI;
687 if (is_cpu_extension_supported(BX_ISA_AVX512_BITALG))
688 ecx |= BX_CPUID_EXT4_AVX512_BITALG;
689 if (is_cpu_extension_supported(BX_ISA_AVX512_VPOPCNTDQ))
690 ecx |= BX_CPUID_EXT4_AVX512_VPOPCNTDQ;
691 }
692 #endif
693
694 // [15:15] reserved
695 // [16:16] LA57: LA57 and 5-level paging - not supported
696 // [17:17] reserved
697 // [18:18] reserved
698 // [19:19] reserved
699 // [20:20] reserved
700 // [21:21] reserved
701
702 // [22:22] RDPID: Read Processor ID support
703 if (is_cpu_extension_supported(BX_ISA_RDPID))
704 ecx |= BX_CPUID_EXT4_RDPID;
705
706 // [23:23] Keylocker support - not supported
707 // [24:24] reserved
708 // [25:25] CLDEMOTE: CLDEMOTE instruction support - not supported
709 // [26:26] reserved
710 // [27:27] MOVDIRI: MOVDIRI instruction support - not supported
711 // [28:28] MOVDIRI64: MOVDIRI64 instruction support - not supported
712 // [29:29] ENQCMD: Enqueue Stores support - not supported
713 // [30:30] SGX_LC: SGX Launch Configuration - not supported
714
715 // [31:31] PKS: Protection keys for supervisor-mode pages
716 #if BX_SUPPORT_PKEYS
717 if (is_cpu_extension_supported(BX_ISA_PKS))
718 ecx |= BX_CPUID_EXT4_PKS;
719 #endif
720
721 return ecx;
722 }
723
724 // leaf 0x80000008 - return Intel defaults //
get_ext_cpuid_leaf_8(cpuid_function_t * leaf) const725 void bx_cpuid_t::get_ext_cpuid_leaf_8(cpuid_function_t *leaf) const
726 {
727 // virtual & phys address size in low 2 bytes of EAX.
728 // TODO: physical address width should be 32-bit when no PSE-36 is supported
729 Bit32u phy_addr_width = BX_PHY_ADDRESS_WIDTH;
730 Bit32u lin_addr_width = is_cpu_extension_supported(BX_ISA_LONG_MODE) ? BX_LIN_ADDRESS_WIDTH : 32;
731
732 leaf->eax = phy_addr_width | (lin_addr_width << 8);
733
734 // [0:0] CLZERO support
735 // [1:1] Instruction Retired Counter MSR available
736 // [2:2] FP Error Pointers Restored by XRSTOR
737 // [3:3] reserved
738 // [4:4] RDPRU support
739 // [5:5] reserved
740 // [6:6] Memory Bandwidth Enforcement (MBE) support
741 // [8:7] reserved
742 // [9:9] WBNOINVD support - not supported yet
743 leaf->ebx = 0;
744 if (is_cpu_extension_supported(BX_ISA_CLZERO))
745 leaf->ebx |= 0x1;
746
747 leaf->ecx = 0; // Reserved, undefined for Intel
748 leaf->edx = 0;
749 }
750
get_cpuid_hidden_level(cpuid_function_t * leaf,const char * magic_string) const751 void bx_cpuid_t::get_cpuid_hidden_level(cpuid_function_t *leaf, const char *magic_string) const
752 {
753 memcpy(&(leaf->eax), magic_string , 4);
754 memcpy(&(leaf->ebx), magic_string + 4, 4);
755 memcpy(&(leaf->ecx), magic_string + 8, 4);
756 memcpy(&(leaf->edx), magic_string + 12, 4);
757
758 #ifdef BX_BIG_ENDIAN
759 leaf->eax = bx_bswap32(leaf->eax);
760 leaf->ebx = bx_bswap32(leaf->ebx);
761 leaf->ecx = bx_bswap32(leaf->ecx);
762 leaf->edx = bx_bswap32(leaf->edx);
763 #endif
764 }
765
dump_cpuid_leaf(unsigned function,unsigned subfunction) const766 void bx_cpuid_t::dump_cpuid_leaf(unsigned function, unsigned subfunction) const
767 {
768 struct cpuid_function_t leaf;
769 get_cpuid_leaf(function, subfunction, &leaf);
770 BX_INFO(("CPUID[0x%08x]: %08x %08x %08x %08x", function, leaf.eax, leaf.ebx, leaf.ecx, leaf.edx));
771 }
772
dump_cpuid(unsigned max_std_leaf,unsigned max_ext_leaf) const773 void bx_cpuid_t::dump_cpuid(unsigned max_std_leaf, unsigned max_ext_leaf) const
774 {
775 for (unsigned std_leaf=0; std_leaf<=max_std_leaf; std_leaf++) {
776 dump_cpuid_leaf(std_leaf);
777 }
778
779 if (max_ext_leaf == 0) return;
780
781 for (unsigned ext_leaf=0x80000000; ext_leaf<=(0x80000000 + max_ext_leaf); ext_leaf++) {
782 dump_cpuid_leaf(ext_leaf);
783 }
784 }
785
warning_messages(unsigned extension) const786 void bx_cpuid_t::warning_messages(unsigned extension) const
787 {
788 switch(extension) {
789 case BX_ISA_3DNOW:
790 BX_INFO(("WARNING: 3DNow! is not implemented yet !"));
791 break;
792 case BX_ISA_RDRAND:
793 BX_INFO(("WARNING: RDRAND would not produce true random numbers !"));
794 break;
795 case BX_ISA_RDSEED:
796 BX_INFO(("WARNING: RDSEED would not produce true random numbers !"));
797 break;
798 default:
799 break;
800 }
801 }
802
dump_features() const803 void bx_cpuid_t::dump_features() const
804 {
805 BX_INFO(("CPU Features supported:"));
806 for (unsigned i=1; i<BX_ISA_EXTENSION_LAST; i++)
807 if (is_cpu_extension_supported(i))
808 BX_INFO(("\t\t%s", cpu_feature_name[i]));
809 }
810