| /dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/arch/mips/mach-mscc/include/mach/serval/ |
| H A D | serval_devcpu_gcb_miim_regs.h | 10 #define MIIM_MII_STATUS(gi) (0x5c + (gi * 36)) argument
11 #define MIIM_MII_CMD(gi) (0x64 + (gi * 36)) argument
12 #define MIIM_MII_DATA(gi) (0x68 + (gi * 36)) argument
|
| /dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/arch/mips/mach-mscc/include/mach/servalt/ |
| H A D | servalt_devcpu_gcb_miim_regs.h | 10 #define MIIM_MII_STATUS(gi) (0xc4 + (gi * 36)) argument
11 #define MIIM_MII_CMD(gi) (0xcc + (gi * 36)) argument
12 #define MIIM_MII_DATA(gi) (0xd0 + (gi * 36)) argument
|
| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/mips/mach-mscc/include/mach/ocelot/ |
| H A D | ocelot_devcpu_gcb_miim_regs.h | 10 #define MIIM_MII_STATUS(gi) (0x9c + (gi * 36)) argument
11 #define MIIM_MII_CMD(gi) (0xa4 + (gi * 36)) argument
12 #define MIIM_MII_DATA(gi) (0xa8 + (gi * 36)) argument
|
| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/mips/mach-mscc/include/mach/servalt/ |
| H A D | servalt_devcpu_gcb_miim_regs.h | 10 #define MIIM_MII_STATUS(gi) (0xc4 + (gi * 36)) argument
11 #define MIIM_MII_CMD(gi) (0xcc + (gi * 36)) argument
12 #define MIIM_MII_DATA(gi) (0xd0 + (gi * 36)) argument
|
| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/mips/mach-mscc/include/mach/jr2/ |
| H A D | jr2_devcpu_gcb_miim_regs.h | 11 #define MIIM_MII_STATUS(gi) (0xc8 + (gi * 36)) argument
12 #define MIIM_MII_CMD(gi) (0xd0 + (gi * 36)) argument
13 #define MIIM_MII_DATA(gi) (0xd4 + (gi * 36)) argument
|
| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/mips/mach-mscc/include/mach/serval/ |
| H A D | serval_devcpu_gcb_miim_regs.h | 10 #define MIIM_MII_STATUS(gi) (0x5c + (gi * 36)) argument
11 #define MIIM_MII_CMD(gi) (0x64 + (gi * 36)) argument
12 #define MIIM_MII_DATA(gi) (0x68 + (gi * 36)) argument
|
| /dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/arch/mips/mach-mscc/include/mach/jr2/ |
| H A D | jr2_devcpu_gcb_miim_regs.h | 11 #define MIIM_MII_STATUS(gi) (0xc8 + (gi * 36)) argument
12 #define MIIM_MII_CMD(gi) (0xd0 + (gi * 36)) argument
13 #define MIIM_MII_DATA(gi) (0xd4 + (gi * 36)) argument
|
| /dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/arch/mips/mach-mscc/include/mach/ocelot/ |
| H A D | ocelot_devcpu_gcb_miim_regs.h | 10 #define MIIM_MII_STATUS(gi) (0x9c + (gi * 36)) argument
11 #define MIIM_MII_CMD(gi) (0xa4 + (gi * 36)) argument
12 #define MIIM_MII_DATA(gi) (0xa8 + (gi * 36)) argument
|
| /dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/arch/mips/mach-mscc/include/mach/serval/ |
| H A D | serval_devcpu_gcb_miim_regs.h | 10 #define MIIM_MII_STATUS(gi) (0x5c + (gi * 36)) argument
11 #define MIIM_MII_CMD(gi) (0x64 + (gi * 36)) argument
12 #define MIIM_MII_DATA(gi) (0x68 + (gi * 36)) argument
|
| /dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/arch/mips/mach-mscc/include/mach/servalt/ |
| H A D | servalt_devcpu_gcb_miim_regs.h | 10 #define MIIM_MII_STATUS(gi) (0xc4 + (gi * 36)) argument
11 #define MIIM_MII_CMD(gi) (0xcc + (gi * 36)) argument
12 #define MIIM_MII_DATA(gi) (0xd0 + (gi * 36)) argument
|
| /dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/mips/mach-mscc/include/mach/ocelot/ |
| H A D | ocelot_devcpu_gcb_miim_regs.h | 10 #define MIIM_MII_STATUS(gi) (0x9c + (gi * 36)) argument
11 #define MIIM_MII_CMD(gi) (0xa4 + (gi * 36)) argument
12 #define MIIM_MII_DATA(gi) (0xa8 + (gi * 36)) argument
|
| /dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/mips/mach-mscc/include/mach/servalt/ |
| H A D | servalt_devcpu_gcb_miim_regs.h | 10 #define MIIM_MII_STATUS(gi) (0xc4 + (gi * 36)) argument
11 #define MIIM_MII_CMD(gi) (0xcc + (gi * 36)) argument
12 #define MIIM_MII_DATA(gi) (0xd0 + (gi * 36)) argument
|
| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/mips/mach-mscc/include/mach/jr2/ |
| H A D | jr2_devcpu_gcb_miim_regs.h | 11 #define MIIM_MII_STATUS(gi) (0xc8 + (gi * 36)) argument
12 #define MIIM_MII_CMD(gi) (0xd0 + (gi * 36)) argument
13 #define MIIM_MII_DATA(gi) (0xd4 + (gi * 36)) argument
|
| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/mips/mach-mscc/include/mach/serval/ |
| H A D | serval_devcpu_gcb_miim_regs.h | 10 #define MIIM_MII_STATUS(gi) (0x5c + (gi * 36)) argument
11 #define MIIM_MII_CMD(gi) (0x64 + (gi * 36)) argument
12 #define MIIM_MII_DATA(gi) (0x68 + (gi * 36)) argument
|
| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/mips/mach-mscc/include/mach/servalt/ |
| H A D | servalt_devcpu_gcb_miim_regs.h | 10 #define MIIM_MII_STATUS(gi) (0xc4 + (gi * 36)) argument
11 #define MIIM_MII_CMD(gi) (0xcc + (gi * 36)) argument
12 #define MIIM_MII_DATA(gi) (0xd0 + (gi * 36)) argument
|
| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/mips/mach-mscc/include/mach/ocelot/ |
| H A D | ocelot_devcpu_gcb_miim_regs.h | 10 #define MIIM_MII_STATUS(gi) (0x9c + (gi * 36)) argument
11 #define MIIM_MII_CMD(gi) (0xa4 + (gi * 36)) argument
12 #define MIIM_MII_DATA(gi) (0xa8 + (gi * 36)) argument
|
| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/mips/mach-mscc/include/mach/ocelot/ |
| H A D | ocelot_devcpu_gcb_miim_regs.h | 10 #define MIIM_MII_STATUS(gi) (0x9c + (gi * 36)) argument
11 #define MIIM_MII_CMD(gi) (0xa4 + (gi * 36)) argument
12 #define MIIM_MII_DATA(gi) (0xa8 + (gi * 36)) argument
|
| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/mips/mach-mscc/include/mach/serval/ |
| H A D | serval_devcpu_gcb_miim_regs.h | 10 #define MIIM_MII_STATUS(gi) (0x5c + (gi * 36)) argument
11 #define MIIM_MII_CMD(gi) (0x64 + (gi * 36)) argument
12 #define MIIM_MII_DATA(gi) (0x68 + (gi * 36)) argument
|
| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/mips/mach-mscc/include/mach/servalt/ |
| H A D | servalt_devcpu_gcb_miim_regs.h | 10 #define MIIM_MII_STATUS(gi) (0xc4 + (gi * 36)) argument
11 #define MIIM_MII_CMD(gi) (0xcc + (gi * 36)) argument
12 #define MIIM_MII_DATA(gi) (0xd0 + (gi * 36)) argument
|
| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/mips/mach-mscc/include/mach/jr2/ |
| H A D | jr2_devcpu_gcb_miim_regs.h | 11 #define MIIM_MII_STATUS(gi) (0xc8 + (gi * 36)) argument
12 #define MIIM_MII_CMD(gi) (0xd0 + (gi * 36)) argument
13 #define MIIM_MII_DATA(gi) (0xd4 + (gi * 36)) argument
|
| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/mips/mach-mscc/include/mach/serval/ |
| H A D | serval_devcpu_gcb_miim_regs.h | 10 #define MIIM_MII_STATUS(gi) (0x5c + (gi * 36)) argument
11 #define MIIM_MII_CMD(gi) (0x64 + (gi * 36)) argument
12 #define MIIM_MII_DATA(gi) (0x68 + (gi * 36)) argument
|
| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/mips/mach-mscc/include/mach/jr2/ |
| H A D | jr2_devcpu_gcb_miim_regs.h | 11 #define MIIM_MII_STATUS(gi) (0xc8 + (gi * 36)) argument
12 #define MIIM_MII_CMD(gi) (0xd0 + (gi * 36)) argument
13 #define MIIM_MII_DATA(gi) (0xd4 + (gi * 36)) argument
|
| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/mips/mach-mscc/include/mach/servalt/ |
| H A D | servalt_devcpu_gcb_miim_regs.h | 10 #define MIIM_MII_STATUS(gi) (0xc4 + (gi * 36)) argument
11 #define MIIM_MII_CMD(gi) (0xcc + (gi * 36)) argument
12 #define MIIM_MII_DATA(gi) (0xd0 + (gi * 36)) argument
|
| /dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/arch/mips/mach-mscc/include/mach/jr2/ |
| H A D | jr2_devcpu_gcb_miim_regs.h | 11 #define MIIM_MII_STATUS(gi) (0xc8 + (gi * 36)) argument
12 #define MIIM_MII_CMD(gi) (0xd0 + (gi * 36)) argument
13 #define MIIM_MII_DATA(gi) (0xd4 + (gi * 36)) argument
|
| /dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/arch/mips/mach-mscc/include/mach/ocelot/ |
| H A D | ocelot_devcpu_gcb_miim_regs.h | 10 #define MIIM_MII_STATUS(gi) (0x9c + (gi * 36)) argument
11 #define MIIM_MII_CMD(gi) (0xa4 + (gi * 36)) argument
12 #define MIIM_MII_DATA(gi) (0xa8 + (gi * 36)) argument
|