1 /*
2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 *
17 * $FreeBSD$
18 */
19 #ifndef _ATH_AH_INTERAL_H_
20 #define _ATH_AH_INTERAL_H_
21 /*
22 * Atheros Device Hardware Access Layer (HAL).
23 *
24 * Internal definitions.
25 */
26 #define AH_NULL 0
27 #define AH_MIN(a,b) ((a)<(b)?(a):(b))
28 #define AH_MAX(a,b) ((a)>(b)?(a):(b))
29
30 #include <netproto/802_11/_ieee80211.h>
31 #include "opt_ah.h" /* needed for AH_SUPPORT_AR5416 */
32
33 #ifndef AH_SUPPORT_AR5416
34 #define AH_SUPPORT_AR5416 1
35 #endif
36
37 #ifndef NBBY
38 #define NBBY 8 /* number of bits/byte */
39 #endif
40
41 #ifndef roundup
42 #define roundup(x, y) ((((x)+((y)-1))/(y))*(y)) /* to any y */
43 #endif
44 #ifndef howmany
45 #define howmany(x, y) (((x)+((y)-1))/(y))
46 #endif
47
48 #ifndef offsetof
49 #define offsetof(type, field) ((size_t)(&((type *)0)->field))
50 #endif
51
52 typedef struct {
53 uint32_t start; /* first register */
54 uint32_t end; /* ending register or zero */
55 } HAL_REGRANGE;
56
57 typedef struct {
58 uint32_t addr; /* regiser address/offset */
59 uint32_t value; /* value to write */
60 } HAL_REGWRITE;
61
62 /*
63 * Transmit power scale factor.
64 *
65 * NB: This is not public because we want to discourage the use of
66 * scaling; folks should use the tx power limit interface.
67 */
68 typedef enum {
69 HAL_TP_SCALE_MAX = 0, /* no scaling (default) */
70 HAL_TP_SCALE_50 = 1, /* 50% of max (-3 dBm) */
71 HAL_TP_SCALE_25 = 2, /* 25% of max (-6 dBm) */
72 HAL_TP_SCALE_12 = 3, /* 12% of max (-9 dBm) */
73 HAL_TP_SCALE_MIN = 4, /* min, but still on */
74 } HAL_TP_SCALE;
75
76 typedef enum {
77 HAL_CAP_RADAR = 0, /* Radar capability */
78 HAL_CAP_AR = 1, /* AR capability */
79 } HAL_PHYDIAG_CAPS;
80
81 /*
82 * Enable/disable strong signal fast diversity
83 */
84 #define HAL_CAP_STRONG_DIV 2
85
86 /*
87 * Each chip or class of chips registers to offer support.
88 */
89 struct ath_hal_chip {
90 const char *name;
91 const char *(*probe)(uint16_t vendorid, uint16_t devid);
92 struct ath_hal *(*attach)(uint16_t devid, HAL_SOFTC,
93 HAL_BUS_TAG, HAL_BUS_HANDLE, uint16_t *eepromdata,
94 HAL_OPS_CONFIG *ah,
95 HAL_STATUS *error);
96 };
97 #ifndef AH_CHIP
98 #define AH_CHIP(_name, _probe, _attach) \
99 static struct ath_hal_chip _name##_chip = { \
100 .name = #_name, \
101 .probe = _probe, \
102 .attach = _attach \
103 }; \
104 OS_DATA_SET(ah_chips, _name##_chip)
105 #endif
106
107 /*
108 * Each RF backend registers to offer support; this is mostly
109 * used by multi-chip 5212 solutions. Single-chip solutions
110 * have a fixed idea about which RF to use.
111 */
112 struct ath_hal_rf {
113 const char *name;
114 HAL_BOOL (*probe)(struct ath_hal *ah);
115 HAL_BOOL (*attach)(struct ath_hal *ah, HAL_STATUS *ecode);
116 };
117 #ifndef AH_RF
118 #define AH_RF(_name, _probe, _attach) \
119 static struct ath_hal_rf _name##_rf = { \
120 .name = __STRING(_name), \
121 .probe = _probe, \
122 .attach = _attach \
123 }; \
124 OS_DATA_SET(ah_rfs, _name##_rf)
125 #endif
126
127 struct ath_hal_rf *ath_hal_rfprobe(struct ath_hal *ah, HAL_STATUS *ecode);
128
129 /*
130 * Maximum number of internal channels. Entries are per unique
131 * frequency so this might be need to be increased to handle all
132 * usage cases; typically no more than 32 are really needed but
133 * dynamically allocating the data structures is a bit painful
134 * right now.
135 */
136 #ifndef AH_MAXCHAN
137 #define AH_MAXCHAN 128
138 #endif
139
140 #define HAL_NF_CAL_HIST_LEN_FULL 5
141 #define HAL_NF_CAL_HIST_LEN_SMALL 1
142 #define HAL_NUM_NF_READINGS 6 /* 3 chains * (ctl + ext) */
143 #define HAL_NF_LOAD_DELAY 1000
144
145 /*
146 * PER_CHAN doesn't work for now, as it looks like the device layer
147 * has to pre-populate the per-channel list with nominal values.
148 */
149 //#define ATH_NF_PER_CHAN 1
150
151 typedef struct {
152 u_int8_t curr_index;
153 int8_t invalidNFcount; /* TO DO: REMOVE THIS! */
154 int16_t priv_nf[HAL_NUM_NF_READINGS];
155 } HAL_NFCAL_BASE;
156
157 typedef struct {
158 HAL_NFCAL_BASE base;
159 int16_t nf_cal_buffer[HAL_NF_CAL_HIST_LEN_FULL][HAL_NUM_NF_READINGS];
160 } HAL_NFCAL_HIST_FULL;
161
162 typedef struct {
163 HAL_NFCAL_BASE base;
164 int16_t nf_cal_buffer[HAL_NF_CAL_HIST_LEN_SMALL][HAL_NUM_NF_READINGS];
165 } HAL_NFCAL_HIST_SMALL;
166
167 #ifdef ATH_NF_PER_CHAN
168 typedef HAL_NFCAL_HIST_FULL HAL_CHAN_NFCAL_HIST;
169 #define AH_HOME_CHAN_NFCAL_HIST(ah, ichan) (ichan ? &ichan->nf_cal_hist: NULL)
170 #else
171 typedef HAL_NFCAL_HIST_SMALL HAL_CHAN_NFCAL_HIST;
172 #define AH_HOME_CHAN_NFCAL_HIST(ah, ichan) (&AH_PRIVATE(ah)->nf_cal_hist)
173 #endif /* ATH_NF_PER_CHAN */
174
175 /*
176 * Internal per-channel state. These are found
177 * using ic_devdata in the ieee80211_channel.
178 */
179 typedef struct {
180 uint16_t channel; /* h/w frequency, NB: may be mapped */
181 uint8_t privFlags;
182 #define CHANNEL_IQVALID 0x01 /* IQ calibration valid */
183 #define CHANNEL_ANI_INIT 0x02 /* ANI state initialized */
184 #define CHANNEL_ANI_SETUP 0x04 /* ANI state setup */
185 #define CHANNEL_MIMO_NF_VALID 0x04 /* Mimo NF values are valid */
186 uint8_t calValid; /* bitmask of cal types */
187 int8_t iCoff;
188 int8_t qCoff;
189 int16_t rawNoiseFloor;
190 int16_t noiseFloorAdjust;
191 #ifdef AH_SUPPORT_AR5416
192 int16_t noiseFloorCtl[AH_MAX_CHAINS];
193 int16_t noiseFloorExt[AH_MAX_CHAINS];
194 #endif /* AH_SUPPORT_AR5416 */
195 uint16_t mainSpur; /* cached spur value for this channel */
196
197 /*XXX TODO: make these part of privFlags */
198 uint8_t paprd_done:1, /* 1: PAPRD DONE, 0: PAPRD Cal not done */
199 paprd_table_write_done:1; /* 1: DONE, 0: Cal data write not done */
200 int one_time_cals_done;
201 HAL_CHAN_NFCAL_HIST nf_cal_hist;
202 } HAL_CHANNEL_INTERNAL;
203
204 /* channel requires noise floor check */
205 #define CHANNEL_NFCREQUIRED IEEE80211_CHAN_PRIV0
206
207 /* all full-width channels */
208 #define IEEE80211_CHAN_ALLFULL \
209 (IEEE80211_CHAN_ALL - (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER))
210 #define IEEE80211_CHAN_ALLTURBOFULL \
211 (IEEE80211_CHAN_ALLTURBO - \
212 (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER))
213
214 typedef struct {
215 uint32_t halChanSpreadSupport : 1,
216 halSleepAfterBeaconBroken : 1,
217 halCompressSupport : 1,
218 halBurstSupport : 1,
219 halFastFramesSupport : 1,
220 halChapTuningSupport : 1,
221 halTurboGSupport : 1,
222 halTurboPrimeSupport : 1,
223 halMicAesCcmSupport : 1,
224 halMicCkipSupport : 1,
225 halMicTkipSupport : 1,
226 halTkipMicTxRxKeySupport : 1,
227 halCipherAesCcmSupport : 1,
228 halCipherCkipSupport : 1,
229 halCipherTkipSupport : 1,
230 halPSPollBroken : 1,
231 halVEOLSupport : 1,
232 halBssIdMaskSupport : 1,
233 halMcastKeySrchSupport : 1,
234 halTsfAddSupport : 1,
235 halChanHalfRate : 1,
236 halChanQuarterRate : 1,
237 halHTSupport : 1,
238 halHTSGI20Support : 1,
239 halRfSilentSupport : 1,
240 halHwPhyCounterSupport : 1,
241 halWowSupport : 1,
242 halWowMatchPatternExact : 1,
243 halAutoSleepSupport : 1,
244 halFastCCSupport : 1,
245 halBtCoexSupport : 1;
246 uint32_t halRxStbcSupport : 1,
247 halTxStbcSupport : 1,
248 halGTTSupport : 1,
249 halCSTSupport : 1,
250 halRifsRxSupport : 1,
251 halRifsTxSupport : 1,
252 hal4AddrAggrSupport : 1,
253 halExtChanDfsSupport : 1,
254 halUseCombinedRadarRssi : 1,
255 halForcePpmSupport : 1,
256 halEnhancedPmSupport : 1,
257 halEnhancedDfsSupport : 1,
258 halMbssidAggrSupport : 1,
259 halBssidMatchSupport : 1,
260 hal4kbSplitTransSupport : 1,
261 halHasRxSelfLinkedTail : 1,
262 halSupportsFastClock5GHz : 1,
263 halHasLongRxDescTsf : 1,
264 halHasBBReadWar : 1,
265 halSerialiseRegWar : 1,
266 halMciSupport : 1,
267 halRxTxAbortSupport : 1,
268 halPaprdEnabled : 1,
269 halHasUapsdSupport : 1,
270 halWpsPushButtonSupport : 1,
271 halBtCoexApsmWar : 1,
272 halGenTimerSupport : 1,
273 halLDPCSupport : 1,
274 halHwBeaconProcSupport : 1,
275 halEnhancedDmaSupport : 1;
276 uint32_t halIsrRacSupport : 1,
277 halApmEnable : 1,
278 halIntrMitigation : 1,
279 hal49GhzSupport : 1,
280 halAntDivCombSupport : 1,
281 halAntDivCombSupportOrg : 1,
282 halRadioRetentionSupport : 1,
283 halSpectralScanSupport : 1,
284 halRxUsingLnaMixing : 1,
285 halRxDoMyBeacon : 1,
286 halHwUapsdTrig : 1;
287
288 uint32_t halWirelessModes;
289 uint16_t halTotalQueues;
290 uint16_t halKeyCacheSize;
291 uint16_t halLow5GhzChan, halHigh5GhzChan;
292 uint16_t halLow2GhzChan, halHigh2GhzChan;
293 int halTstampPrecision;
294 int halRtsAggrLimit;
295 uint8_t halTxChainMask;
296 uint8_t halRxChainMask;
297 uint8_t halNumGpioPins;
298 uint8_t halNumAntCfg2GHz;
299 uint8_t halNumAntCfg5GHz;
300 uint32_t halIntrMask;
301 uint8_t halTxStreams;
302 uint8_t halRxStreams;
303 HAL_MFP_OPT_T halMfpSupport;
304
305 /* AR9300 HAL porting capabilities */
306 int hal_paprd_enabled;
307 int hal_pcie_lcr_offset;
308 int hal_pcie_lcr_extsync_en;
309 int halNumTxMaps;
310 int halTxDescLen;
311 int halTxStatusLen;
312 int halRxStatusLen;
313 int halRxHpFifoDepth;
314 int halRxLpFifoDepth;
315 uint32_t halRegCap; /* XXX needed? */
316 int halNumMRRetries;
317 int hal_ani_poll_interval;
318 int hal_channel_switch_time_usec;
319 } HAL_CAPABILITIES;
320
321 struct regDomain;
322
323 /*
324 * Definitions for ah_flags in ath_hal_private
325 */
326 #define AH_USE_EEPROM 0x1
327 #define AH_IS_HB63 0x2
328
329 /*
330 * The ``private area'' follows immediately after the ``public area''
331 * in the data structure returned by ath_hal_attach. Private data are
332 * used by device-independent code such as the regulatory domain support.
333 * In general, code within the HAL should never depend on data in the
334 * public area. Instead any public data needed internally should be
335 * shadowed here.
336 *
337 * When declaring a device-specific ath_hal data structure this structure
338 * is assumed to at the front; e.g.
339 *
340 * struct ath_hal_5212 {
341 * struct ath_hal_private ah_priv;
342 * ...
343 * };
344 *
345 * It might be better to manage the method pointers in this structure
346 * using an indirect pointer to a read-only data structure but this would
347 * disallow class-style method overriding.
348 */
349 struct ath_hal_private {
350 struct ath_hal h; /* public area */
351
352 /* NB: all methods go first to simplify initialization */
353 HAL_BOOL (*ah_getChannelEdges)(struct ath_hal*,
354 uint16_t channelFlags,
355 uint16_t *lowChannel, uint16_t *highChannel);
356 u_int (*ah_getWirelessModes)(struct ath_hal*);
357 HAL_BOOL (*ah_eepromRead)(struct ath_hal *, u_int off,
358 uint16_t *data);
359 HAL_BOOL (*ah_eepromWrite)(struct ath_hal *, u_int off,
360 uint16_t data);
361 HAL_BOOL (*ah_getChipPowerLimits)(struct ath_hal *,
362 struct ieee80211_channel *);
363 int16_t (*ah_getNfAdjust)(struct ath_hal *,
364 const HAL_CHANNEL_INTERNAL*);
365 void (*ah_getNoiseFloor)(struct ath_hal *,
366 int16_t nfarray[]);
367
368 void *ah_eeprom; /* opaque EEPROM state */
369 uint16_t ah_eeversion; /* EEPROM version */
370 void (*ah_eepromDetach)(struct ath_hal *);
371 HAL_STATUS (*ah_eepromGet)(struct ath_hal *, int, void *);
372 HAL_STATUS (*ah_eepromSet)(struct ath_hal *, int, int);
373 uint16_t (*ah_getSpurChan)(struct ath_hal *, int, HAL_BOOL);
374 HAL_BOOL (*ah_eepromDiag)(struct ath_hal *, int request,
375 const void *args, uint32_t argsize,
376 void **result, uint32_t *resultsize);
377
378 /*
379 * Device revision information.
380 */
381 uint16_t ah_devid; /* PCI device ID */
382 uint16_t ah_subvendorid; /* PCI subvendor ID */
383 uint32_t ah_macVersion; /* MAC version id */
384 uint16_t ah_macRev; /* MAC revision */
385 uint16_t ah_phyRev; /* PHY revision */
386 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */
387 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */
388 uint32_t ah_flags; /* misc flags */
389 uint8_t ah_ispcie; /* PCIE, special treatment */
390 uint8_t ah_devType; /* card type - CB, PCI, PCIe */
391
392 HAL_OPMODE ah_opmode; /* operating mode from reset */
393 const struct ieee80211_channel *ah_curchan;/* operating channel */
394 HAL_CAPABILITIES ah_caps; /* device capabilities */
395 uint32_t ah_diagreg; /* user-specified AR_DIAG_SW */
396 int16_t ah_powerLimit; /* tx power cap */
397 uint16_t ah_maxPowerLevel; /* calculated max tx power */
398 u_int ah_tpScale; /* tx power scale factor */
399 u_int16_t ah_extraTxPow; /* low rates extra-txpower */
400 uint32_t ah_11nCompat; /* 11n compat controls */
401
402 /*
403 * State for regulatory domain handling.
404 */
405 HAL_REG_DOMAIN ah_currentRD; /* EEPROM regulatory domain */
406 HAL_REG_DOMAIN ah_currentRDext; /* EEPROM extended regdomain flags */
407 HAL_DFS_DOMAIN ah_dfsDomain; /* current DFS domain */
408 HAL_CHANNEL_INTERNAL ah_channels[AH_MAXCHAN]; /* private chan state */
409 u_int ah_nchan; /* valid items in ah_channels */
410 const struct regDomain *ah_rd2GHz; /* reg state for 2G band */
411 const struct regDomain *ah_rd5GHz; /* reg state for 5G band */
412
413 uint8_t ah_coverageClass; /* coverage class */
414 /*
415 * RF Silent handling; setup according to the EEPROM.
416 */
417 uint16_t ah_rfsilent; /* GPIO pin + polarity */
418 HAL_BOOL ah_rfkillEnabled; /* enable/disable RfKill */
419 /*
420 * Diagnostic support for discriminating HIUERR reports.
421 */
422 uint32_t ah_fatalState[6]; /* AR_ISR+shadow regs */
423 int ah_rxornIsFatal; /* how to treat HAL_INT_RXORN */
424
425 /* Only used if ATH_NF_PER_CHAN is defined */
426 HAL_NFCAL_HIST_FULL nf_cal_hist;
427
428 /*
429 * Channel survey history - current channel only.
430 */
431 HAL_CHANNEL_SURVEY ah_chansurvey; /* channel survey */
432 };
433
434 #define AH_PRIVATE(_ah) ((struct ath_hal_private *)(_ah))
435
436 #define ath_hal_getChannelEdges(_ah, _cf, _lc, _hc) \
437 AH_PRIVATE(_ah)->ah_getChannelEdges(_ah, _cf, _lc, _hc)
438 #define ath_hal_getWirelessModes(_ah) \
439 AH_PRIVATE(_ah)->ah_getWirelessModes(_ah)
440 #define ath_hal_eepromRead(_ah, _off, _data) \
441 AH_PRIVATE(_ah)->ah_eepromRead(_ah, _off, _data)
442 #define ath_hal_eepromWrite(_ah, _off, _data) \
443 AH_PRIVATE(_ah)->ah_eepromWrite(_ah, _off, _data)
444 #define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \
445 (_ah)->ah_gpioCfgOutput(_ah, _gpio, _type)
446 #define ath_hal_gpioCfgInput(_ah, _gpio) \
447 (_ah)->ah_gpioCfgInput(_ah, _gpio)
448 #define ath_hal_gpioGet(_ah, _gpio) \
449 (_ah)->ah_gpioGet(_ah, _gpio)
450 #define ath_hal_gpioSet(_ah, _gpio, _val) \
451 (_ah)->ah_gpioSet(_ah, _gpio, _val)
452 #define ath_hal_gpioSetIntr(_ah, _gpio, _ilevel) \
453 (_ah)->ah_gpioSetIntr(_ah, _gpio, _ilevel)
454 #define ath_hal_getpowerlimits(_ah, _chan) \
455 AH_PRIVATE(_ah)->ah_getChipPowerLimits(_ah, _chan)
456 #define ath_hal_getNfAdjust(_ah, _c) \
457 AH_PRIVATE(_ah)->ah_getNfAdjust(_ah, _c)
458 #define ath_hal_getNoiseFloor(_ah, _nfArray) \
459 AH_PRIVATE(_ah)->ah_getNoiseFloor(_ah, _nfArray)
460 #define ath_hal_configPCIE(_ah, _reset, _poweroff) \
461 (_ah)->ah_configPCIE(_ah, _reset, _poweroff)
462 #define ath_hal_disablePCIE(_ah) \
463 (_ah)->ah_disablePCIE(_ah)
464 #define ath_hal_setInterrupts(_ah, _mask) \
465 (_ah)->ah_setInterrupts(_ah, _mask)
466
467 #define ath_hal_isrfkillenabled(_ah) \
468 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, AH_NULL) == HAL_OK)
469 #define ath_hal_enable_rfkill(_ah, _v) \
470 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _v, AH_NULL)
471 #define ath_hal_hasrfkill_int(_ah) \
472 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 3, AH_NULL) == HAL_OK)
473
474 #define ath_hal_eepromDetach(_ah) do { \
475 if (AH_PRIVATE(_ah)->ah_eepromDetach != AH_NULL) \
476 AH_PRIVATE(_ah)->ah_eepromDetach(_ah); \
477 } while (0)
478 #define ath_hal_eepromGet(_ah, _param, _val) \
479 AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, _val)
480 #define ath_hal_eepromSet(_ah, _param, _val) \
481 AH_PRIVATE(_ah)->ah_eepromSet(_ah, _param, _val)
482 #define ath_hal_eepromGetFlag(_ah, _param) \
483 (AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, AH_NULL) == HAL_OK)
484 #define ath_hal_getSpurChan(_ah, _ix, _is2G) \
485 AH_PRIVATE(_ah)->ah_getSpurChan(_ah, _ix, _is2G)
486 #define ath_hal_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) \
487 AH_PRIVATE(_ah)->ah_eepromDiag(_ah, _request, _a, _asize, _r, _rsize)
488
489 #ifndef _NET_IF_IEEE80211_H_
490 /*
491 * Stuff that would naturally come from _ieee80211.h
492 */
493 #define IEEE80211_ADDR_LEN 6
494
495 #define IEEE80211_WEP_IVLEN 3 /* 24bit */
496 #define IEEE80211_WEP_KIDLEN 1 /* 1 octet */
497 #define IEEE80211_WEP_CRCLEN 4 /* CRC-32 */
498
499 #define IEEE80211_CRC_LEN 4
500
501 #define IEEE80211_MAX_LEN (2300 + IEEE80211_CRC_LEN + \
502 (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + IEEE80211_WEP_CRCLEN))
503 #endif /* _NET_IF_IEEE80211_H_ */
504
505 #define HAL_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001
506
507 #define INIT_AIFS 2
508 #define INIT_CWMIN 15
509 #define INIT_CWMIN_11B 31
510 #define INIT_CWMAX 1023
511 #define INIT_SH_RETRY 10
512 #define INIT_LG_RETRY 10
513 #define INIT_SSH_RETRY 32
514 #define INIT_SLG_RETRY 32
515
516 typedef struct {
517 uint32_t tqi_ver; /* HAL TXQ verson */
518 HAL_TX_QUEUE tqi_type; /* hw queue type*/
519 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* queue subtype, if applicable */
520 HAL_TX_QUEUE_FLAGS tqi_qflags; /* queue flags */
521 uint32_t tqi_priority;
522 uint32_t tqi_aifs; /* aifs */
523 uint32_t tqi_cwmin; /* cwMin */
524 uint32_t tqi_cwmax; /* cwMax */
525 uint16_t tqi_shretry; /* frame short retry limit */
526 uint16_t tqi_lgretry; /* frame long retry limit */
527 uint32_t tqi_cbrPeriod;
528 uint32_t tqi_cbrOverflowLimit;
529 uint32_t tqi_burstTime;
530 uint32_t tqi_readyTime;
531 uint32_t tqi_physCompBuf;
532 uint32_t tqi_intFlags; /* flags for internal use */
533 } HAL_TX_QUEUE_INFO;
534
535 extern HAL_BOOL ath_hal_setTxQProps(struct ath_hal *ah,
536 HAL_TX_QUEUE_INFO *qi, const HAL_TXQ_INFO *qInfo);
537 extern HAL_BOOL ath_hal_getTxQProps(struct ath_hal *ah,
538 HAL_TXQ_INFO *qInfo, const HAL_TX_QUEUE_INFO *qi);
539
540 #define HAL_SPUR_VAL_MASK 0x3FFF
541 #define HAL_SPUR_CHAN_WIDTH 87
542 #define HAL_BIN_WIDTH_BASE_100HZ 3125
543 #define HAL_BIN_WIDTH_TURBO_100HZ 6250
544 #define HAL_MAX_BINS_ALLOWED 28
545
546 #define IS_CHAN_5GHZ(_c) ((_c)->channel > 4900)
547 #define IS_CHAN_2GHZ(_c) (!IS_CHAN_5GHZ(_c))
548
549 #define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990)
550
551 /*
552 * Deduce if the host cpu has big- or litt-endian byte order.
553 */
554 static __inline__ int
isBigEndian(void)555 isBigEndian(void)
556 {
557 union {
558 int32_t i;
559 char c[4];
560 } u;
561 u.i = 1;
562 return (u.c[0] == 0);
563 }
564
565 /* unalligned little endian access */
566 #define LE_READ_2(p) \
567 ((uint16_t) \
568 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8)))
569 #define LE_READ_4(p) \
570 ((uint32_t) \
571 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8) |\
572 (((const uint8_t *)(p))[2]<<16) | (((const uint8_t *)(p))[3]<<24)))
573
574 /*
575 * Register manipulation macros that expect bit field defines
576 * to follow the convention that an _S suffix is appended for
577 * a shift count, while the field mask has no suffix.
578 */
579 #define SM(_v, _f) (((_v) << _f##_S) & (_f))
580 #define MS(_v, _f) (((_v) & (_f)) >> _f##_S)
581 #define OS_REG_RMW(_a, _r, _set, _clr) \
582 OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) & ~(_clr)) | (_set))
583 #define OS_REG_RMW_FIELD(_a, _r, _f, _v) \
584 OS_REG_WRITE(_a, _r, \
585 (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f)))
586 #define OS_REG_SET_BIT(_a, _r, _f) \
587 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) | (_f))
588 #define OS_REG_CLR_BIT(_a, _r, _f) \
589 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) &~ (_f))
590 #define OS_REG_IS_BIT_SET(_a, _r, _f) \
591 ((OS_REG_READ(_a, _r) & (_f)) != 0)
592 #define OS_REG_RMW_FIELD_ALT(_a, _r, _f, _v) \
593 OS_REG_WRITE(_a, _r, \
594 (OS_REG_READ(_a, _r) &~(_f<<_f##_S)) | \
595 (((_v) << _f##_S) & (_f<<_f##_S)))
596 #define OS_REG_READ_FIELD(_a, _r, _f) \
597 (((OS_REG_READ(_a, _r) & _f) >> _f##_S))
598 #define OS_REG_READ_FIELD_ALT(_a, _r, _f) \
599 ((OS_REG_READ(_a, _r) >> (_f##_S))&(_f))
600
601 /* Analog register writes may require a delay between each one (eg Merlin?) */
602 #define OS_A_REG_RMW_FIELD(_a, _r, _f, _v) \
603 do { OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) &~ (_f)) | \
604 (((_v) << _f##_S) & (_f))) ; OS_DELAY(100); } while (0)
605 #define OS_A_REG_WRITE(_a, _r, _v) \
606 do { OS_REG_WRITE(_a, _r, _v); OS_DELAY(100); } while (0)
607
608 /* wait for the register contents to have the specified value */
609 extern HAL_BOOL ath_hal_wait(struct ath_hal *, u_int reg,
610 uint32_t mask, uint32_t val);
611 extern HAL_BOOL ath_hal_waitfor(struct ath_hal *, u_int reg,
612 uint32_t mask, uint32_t val, uint32_t timeout);
613
614 /* return the first n bits in val reversed */
615 extern uint32_t ath_hal_reverseBits(uint32_t val, uint32_t n);
616
617 /* printf interfaces */
618 extern void ath_hal_printf(struct ath_hal *, const char*, ...)
619 __printflike(2,3);
620 extern void ath_hal_vprintf(struct ath_hal *, const char*, __va_list)
621 __printflike(2, 0);
622 extern const char* ath_hal_ether_sprintf(const uint8_t *mac);
623
624 /* allocate and free memory */
625 extern void *ath_hal_malloc(size_t);
626 extern void ath_hal_free(void *);
627
628 /* common debugging interfaces */
629 #ifdef AH_DEBUG
630 #include "ah_debug.h"
631 extern int ath_hal_debug; /* Global debug flags */
632
633 /*
634 * The typecast is purely because some callers will pass in
635 * AH_NULL directly rather than using a NULL ath_hal pointer.
636 */
637 #define HALDEBUG(_ah, __m, ...) \
638 do { \
639 if ((__m) == HAL_DEBUG_UNMASKABLE || \
640 ath_hal_debug & (__m) || \
641 ((_ah) != NULL && \
642 ((struct ath_hal *) (_ah))->ah_config.ah_debug & (__m))) { \
643 DO_HALDEBUG((_ah), (__m), __VA_ARGS__); \
644 } \
645 } while(0)
646
647 extern void DO_HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...)
648 __printflike(3,4);
649 #else
650 #define HALDEBUG(_ah, __m, ...) do { } while (0)
651 #endif /* AH_DEBUG */
652
653 /*
654 * Register logging definitions shared with ardecode.
655 */
656 #include "ah_decode.h"
657
658 /*
659 * Common assertion interface. Note: it is a bad idea to generate
660 * an assertion failure for any recoverable event. Instead catch
661 * the violation and, if possible, fix it up or recover from it; either
662 * with an error return value or a diagnostic messages. System software
663 * does not panic unless the situation is hopeless.
664 */
665 #ifdef AH_ASSERT
666 extern void ath_hal_assert_failed(const char* filename,
667 int lineno, const char* msg);
668
669 #define HALASSERT(_x) do { \
670 if (!(_x)) { \
671 ath_hal_assert_failed(__FILE__, __LINE__, #_x); \
672 } \
673 } while (0)
674 #else
675 #define HALASSERT(_x)
676 #endif /* AH_ASSERT */
677
678 /*
679 * Regulatory domain support.
680 */
681
682 /*
683 * Return the max allowed antenna gain and apply any regulatory
684 * domain specific changes.
685 */
686 u_int ath_hal_getantennareduction(struct ath_hal *ah,
687 const struct ieee80211_channel *chan, u_int twiceGain);
688
689 /*
690 * Return the test group for the specific channel based on
691 * the current regulatory setup.
692 */
693 u_int ath_hal_getctl(struct ath_hal *, const struct ieee80211_channel *);
694
695 /*
696 * Map a public channel definition to the corresponding
697 * internal data structure. This implicitly specifies
698 * whether or not the specified channel is ok to use
699 * based on the current regulatory domain constraints.
700 */
701 #ifndef AH_DEBUG
702 static OS_INLINE HAL_CHANNEL_INTERNAL *
ath_hal_checkchannel(struct ath_hal * ah,const struct ieee80211_channel * c)703 ath_hal_checkchannel(struct ath_hal *ah, const struct ieee80211_channel *c)
704 {
705 HAL_CHANNEL_INTERNAL *cc;
706
707 HALASSERT(c->ic_devdata < AH_PRIVATE(ah)->ah_nchan);
708 cc = &AH_PRIVATE(ah)->ah_channels[c->ic_devdata];
709 HALASSERT(c->ic_freq == cc->channel || IEEE80211_IS_CHAN_GSM(c));
710 return cc;
711 }
712 #else
713 /* NB: non-inline version that checks state */
714 HAL_CHANNEL_INTERNAL *ath_hal_checkchannel(struct ath_hal *,
715 const struct ieee80211_channel *);
716 #endif /* AH_DEBUG */
717
718 /*
719 * Return the h/w frequency for a channel. This may be
720 * different from ic_freq if this is a GSM device that
721 * takes 2.4GHz frequencies and down-converts them.
722 */
723 static OS_INLINE uint16_t
ath_hal_gethwchannel(struct ath_hal * ah,const struct ieee80211_channel * c)724 ath_hal_gethwchannel(struct ath_hal *ah, const struct ieee80211_channel *c)
725 {
726 return ath_hal_checkchannel(ah, c)->channel;
727 }
728
729 /*
730 * Convert between microseconds and core system clocks.
731 */
732 extern u_int ath_hal_mac_clks(struct ath_hal *ah, u_int usecs);
733 extern u_int ath_hal_mac_usec(struct ath_hal *ah, u_int clks);
734
735 /*
736 * Generic get/set capability support. Each chip overrides
737 * this routine to support chip-specific capabilities.
738 */
739 extern HAL_STATUS ath_hal_getcapability(struct ath_hal *ah,
740 HAL_CAPABILITY_TYPE type, uint32_t capability,
741 uint32_t *result);
742 extern HAL_BOOL ath_hal_setcapability(struct ath_hal *ah,
743 HAL_CAPABILITY_TYPE type, uint32_t capability,
744 uint32_t setting, HAL_STATUS *status);
745
746 /* The diagnostic codes used to be internally defined here -adrian */
747 #include "ah_diagcodes.h"
748
749 /*
750 * The AR5416 and later HALs have MAC and baseband hang checking.
751 */
752 typedef struct {
753 uint32_t hang_reg_offset;
754 uint32_t hang_val;
755 uint32_t hang_mask;
756 uint32_t hang_offset;
757 } hal_hw_hang_check_t;
758
759 typedef struct {
760 uint32_t dma_dbg_3;
761 uint32_t dma_dbg_4;
762 uint32_t dma_dbg_5;
763 uint32_t dma_dbg_6;
764 } mac_dbg_regs_t;
765
766 typedef enum {
767 dcu_chain_state = 0x1,
768 dcu_complete_state = 0x2,
769 qcu_state = 0x4,
770 qcu_fsp_ok = 0x8,
771 qcu_fsp_state = 0x10,
772 qcu_stitch_state = 0x20,
773 qcu_fetch_state = 0x40,
774 qcu_complete_state = 0x80
775 } hal_mac_hangs_t;
776
777 typedef struct {
778 int states;
779 uint8_t dcu_chain_state;
780 uint8_t dcu_complete_state;
781 uint8_t qcu_state;
782 uint8_t qcu_fsp_ok;
783 uint8_t qcu_fsp_state;
784 uint8_t qcu_stitch_state;
785 uint8_t qcu_fetch_state;
786 uint8_t qcu_complete_state;
787 } hal_mac_hang_check_t;
788
789 enum {
790 HAL_BB_HANG_DFS = 0x0001,
791 HAL_BB_HANG_RIFS = 0x0002,
792 HAL_BB_HANG_RX_CLEAR = 0x0004,
793 HAL_BB_HANG_UNKNOWN = 0x0080,
794
795 HAL_MAC_HANG_SIG1 = 0x0100,
796 HAL_MAC_HANG_SIG2 = 0x0200,
797 HAL_MAC_HANG_UNKNOWN = 0x8000,
798
799 HAL_BB_HANGS = HAL_BB_HANG_DFS
800 | HAL_BB_HANG_RIFS
801 | HAL_BB_HANG_RX_CLEAR
802 | HAL_BB_HANG_UNKNOWN,
803 HAL_MAC_HANGS = HAL_MAC_HANG_SIG1
804 | HAL_MAC_HANG_SIG2
805 | HAL_MAC_HANG_UNKNOWN,
806 };
807
808 /* Merge these with above */
809 typedef enum hal_hw_hangs {
810 HAL_DFS_BB_HANG_WAR = 0x1,
811 HAL_RIFS_BB_HANG_WAR = 0x2,
812 HAL_RX_STUCK_LOW_BB_HANG_WAR = 0x4,
813 HAL_MAC_HANG_WAR = 0x8,
814 HAL_PHYRESTART_CLR_WAR = 0x10,
815 HAL_MAC_HANG_DETECTED = 0x40000000,
816 HAL_BB_HANG_DETECTED = 0x80000000
817 } hal_hw_hangs_t;
818
819 /*
820 * Device revision information.
821 */
822 typedef struct {
823 uint16_t ah_devid; /* PCI device ID */
824 uint16_t ah_subvendorid; /* PCI subvendor ID */
825 uint32_t ah_macVersion; /* MAC version id */
826 uint16_t ah_macRev; /* MAC revision */
827 uint16_t ah_phyRev; /* PHY revision */
828 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */
829 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */
830 } HAL_REVS;
831
832 /*
833 * Argument payload for HAL_DIAG_SETKEY.
834 */
835 typedef struct {
836 HAL_KEYVAL dk_keyval;
837 uint16_t dk_keyix; /* key index */
838 uint8_t dk_mac[IEEE80211_ADDR_LEN];
839 int dk_xor; /* XOR key data */
840 } HAL_DIAG_KEYVAL;
841
842 /*
843 * Argument payload for HAL_DIAG_EEWRITE.
844 */
845 typedef struct {
846 uint16_t ee_off; /* eeprom offset */
847 uint16_t ee_data; /* write data */
848 } HAL_DIAG_EEVAL;
849
850
851 typedef struct {
852 u_int offset; /* reg offset */
853 uint32_t val; /* reg value */
854 } HAL_DIAG_REGVAL;
855
856 /*
857 * 11n compatibility tweaks.
858 */
859 #define HAL_DIAG_11N_SERVICES 0x00000003
860 #define HAL_DIAG_11N_SERVICES_S 0
861 #define HAL_DIAG_11N_TXSTOMP 0x0000000c
862 #define HAL_DIAG_11N_TXSTOMP_S 2
863
864 typedef struct {
865 int maxNoiseImmunityLevel; /* [0..4] */
866 int totalSizeDesired[5];
867 int coarseHigh[5];
868 int coarseLow[5];
869 int firpwr[5];
870
871 int maxSpurImmunityLevel; /* [0..7] */
872 int cycPwrThr1[8];
873
874 int maxFirstepLevel; /* [0..2] */
875 int firstep[3];
876
877 uint32_t ofdmTrigHigh;
878 uint32_t ofdmTrigLow;
879 int32_t cckTrigHigh;
880 int32_t cckTrigLow;
881 int32_t rssiThrLow;
882 int32_t rssiThrHigh;
883
884 int period; /* update listen period */
885 } HAL_ANI_PARAMS;
886
887 extern HAL_BOOL ath_hal_getdiagstate(struct ath_hal *ah, int request,
888 const void *args, uint32_t argsize,
889 void **result, uint32_t *resultsize);
890
891 /*
892 * Setup a h/w rate table for use.
893 */
894 extern void ath_hal_setupratetable(struct ath_hal *ah, HAL_RATE_TABLE *rt);
895
896 /*
897 * Common routine for implementing getChanNoise api.
898 */
899 int16_t ath_hal_getChanNoise(struct ath_hal *, const struct ieee80211_channel *);
900
901 /*
902 * Initialization support.
903 */
904 typedef struct {
905 const uint32_t *data;
906 int rows, cols;
907 } HAL_INI_ARRAY;
908
909 #define HAL_INI_INIT(_ia, _data, _cols) do { \
910 (_ia)->data = (const uint32_t *)(_data); \
911 (_ia)->rows = sizeof(_data) / sizeof((_data)[0]); \
912 (_ia)->cols = (_cols); \
913 } while (0)
914 #define HAL_INI_VAL(_ia, _r, _c) \
915 ((_ia)->data[((_r)*(_ia)->cols) + (_c)])
916
917 /*
918 * OS_DELAY() does a PIO READ on the PCI bus which allows
919 * other cards' DMA reads to complete in the middle of our reset.
920 */
921 #define DMA_YIELD(x) do { \
922 if ((++(x) % 64) == 0) \
923 OS_DELAY(1); \
924 } while (0)
925
926 #define HAL_INI_WRITE_ARRAY(ah, regArray, col, regWr) do { \
927 int r; \
928 for (r = 0; r < N(regArray); r++) { \
929 OS_REG_WRITE(ah, (regArray)[r][0], (regArray)[r][col]); \
930 DMA_YIELD(regWr); \
931 } \
932 } while (0)
933
934 #define HAL_INI_WRITE_BANK(ah, regArray, bankData, regWr) do { \
935 int r; \
936 for (r = 0; r < N(regArray); r++) { \
937 OS_REG_WRITE(ah, (regArray)[r][0], (bankData)[r]); \
938 DMA_YIELD(regWr); \
939 } \
940 } while (0)
941
942 extern int ath_hal_ini_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia,
943 int col, int regWr);
944 extern void ath_hal_ini_bank_setup(uint32_t data[], const HAL_INI_ARRAY *ia,
945 int col);
946 extern int ath_hal_ini_bank_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia,
947 const uint32_t data[], int regWr);
948
949 #define CCK_SIFS_TIME 10
950 #define CCK_PREAMBLE_BITS 144
951 #define CCK_PLCP_BITS 48
952
953 #define OFDM_SIFS_TIME 16
954 #define OFDM_PREAMBLE_TIME 20
955 #define OFDM_PLCP_BITS 22
956 #define OFDM_SYMBOL_TIME 4
957
958 #define OFDM_HALF_SIFS_TIME 32
959 #define OFDM_HALF_PREAMBLE_TIME 40
960 #define OFDM_HALF_PLCP_BITS 22
961 #define OFDM_HALF_SYMBOL_TIME 8
962
963 #define OFDM_QUARTER_SIFS_TIME 64
964 #define OFDM_QUARTER_PREAMBLE_TIME 80
965 #define OFDM_QUARTER_PLCP_BITS 22
966 #define OFDM_QUARTER_SYMBOL_TIME 16
967
968 #define TURBO_SIFS_TIME 8
969 #define TURBO_PREAMBLE_TIME 14
970 #define TURBO_PLCP_BITS 22
971 #define TURBO_SYMBOL_TIME 4
972
973 #define WLAN_CTRL_FRAME_SIZE (2+2+6+4) /* ACK+FCS */
974
975 /* Generic EEPROM board value functions */
976 extern HAL_BOOL ath_ee_getLowerUpperIndex(uint8_t target, uint8_t *pList,
977 uint16_t listSize, uint16_t *indexL, uint16_t *indexR);
978 extern HAL_BOOL ath_ee_FillVpdTable(uint8_t pwrMin, uint8_t pwrMax,
979 uint8_t *pPwrList, uint8_t *pVpdList, uint16_t numIntercepts,
980 uint8_t *pRetVpdList);
981 extern int16_t ath_ee_interpolate(uint16_t target, uint16_t srcLeft,
982 uint16_t srcRight, int16_t targetLeft, int16_t targetRight);
983
984 /* Whether 5ghz fast clock is needed */
985 /*
986 * The chipset (Merlin, AR9300/later) should set the capability flag below;
987 * this flag simply says that the hardware can do it, not that the EEPROM
988 * says it can.
989 *
990 * Merlin 2.0/2.1 chips with an EEPROM version > 16 do 5ghz fast clock
991 * if the relevant eeprom flag is set.
992 * Merlin 2.0/2.1 chips with an EEPROM version <= 16 do 5ghz fast clock
993 * by default.
994 */
995 #define IS_5GHZ_FAST_CLOCK_EN(_ah, _c) \
996 (IEEE80211_IS_CHAN_5GHZ(_c) && \
997 AH_PRIVATE((_ah))->ah_caps.halSupportsFastClock5GHz && \
998 ath_hal_eepromGetFlag((_ah), AR_EEP_FSTCLK_5G))
999
1000 /*
1001 * Fetch the maximum regulatory domain power for the given channel
1002 * in 1/2dBm steps.
1003 */
1004 static inline int
ath_hal_get_twice_max_regpower(struct ath_hal_private * ahp,const HAL_CHANNEL_INTERNAL * ichan,const struct ieee80211_channel * chan)1005 ath_hal_get_twice_max_regpower(struct ath_hal_private *ahp,
1006 const HAL_CHANNEL_INTERNAL *ichan, const struct ieee80211_channel *chan)
1007 {
1008 struct ath_hal *ah = &ahp->h;
1009
1010 if (! chan) {
1011 ath_hal_printf(ah, "%s: called with chan=NULL!\n", __func__);
1012 return (0);
1013 }
1014 return (chan->ic_maxpower);
1015 }
1016
1017 /*
1018 * Get the maximum antenna gain allowed, in 1/2dBm steps.
1019 */
1020 static inline int
ath_hal_getantennaallowed(struct ath_hal * ah,const struct ieee80211_channel * chan)1021 ath_hal_getantennaallowed(struct ath_hal *ah,
1022 const struct ieee80211_channel *chan)
1023 {
1024
1025 if (! chan)
1026 return (0);
1027
1028 return (chan->ic_maxantgain);
1029 }
1030
1031 /*
1032 * Map the given 2GHz channel to an IEEE number.
1033 */
1034 extern int ath_hal_mhz2ieee_2ghz(struct ath_hal *, int freq);
1035
1036 /*
1037 * Clear the channel survey data.
1038 */
1039 extern void ath_hal_survey_clear(struct ath_hal *ah);
1040
1041 /*
1042 * Add a sample to the channel survey data.
1043 */
1044 extern void ath_hal_survey_add_sample(struct ath_hal *ah,
1045 HAL_SURVEY_SAMPLE *hs);
1046
1047 #endif /* _ATH_AH_INTERAL_H_ */
1048