1 /*
2 * QEMU CPU model
3 *
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
19 */
20 #ifndef QEMU_CPU_H
21 #define QEMU_CPU_H
22
23 #include "hw/qdev-core.h"
24 #include "disas/dis-asm.h"
25 #include "exec/breakpoint.h"
26 #include "exec/hwaddr.h"
27 #include "exec/vaddr.h"
28 #include "exec/memattrs.h"
29 #include "exec/mmu-access-type.h"
30 #include "exec/tlb-common.h"
31 #include "qapi/qapi-types-machine.h"
32 #include "qapi/qapi-types-run-state.h"
33 #include "qemu/bitmap.h"
34 #include "qemu/rcu_queue.h"
35 #include "qemu/queue.h"
36 #include "qemu/thread.h"
37 #include "qom/object.h"
38
39 typedef int (*WriteCoreDumpFunction)(const void *buf, size_t size,
40 void *opaque);
41
42 /**
43 * SECTION:cpu
44 * @section_id: QEMU-cpu
45 * @title: CPU Class
46 * @short_description: Base class for all CPUs
47 */
48
49 #define TYPE_CPU "cpu"
50
51 /* Since this macro is used a lot in hot code paths and in conjunction with
52 * FooCPU *foo_env_get_cpu(), we deviate from usual QOM practice by using
53 * an unchecked cast.
54 */
55 #define CPU(obj) ((CPUState *)(obj))
56
57 /*
58 * The class checkers bring in CPU_GET_CLASS() which is potentially
59 * expensive given the eventual call to
60 * object_class_dynamic_cast_assert(). Because of this the CPUState
61 * has a cached value for the class in cs->cc which is set up in
62 * cpu_exec_realizefn() for use in hot code paths.
63 */
64 typedef struct CPUClass CPUClass;
65 DECLARE_CLASS_CHECKERS(CPUClass, CPU,
66 TYPE_CPU)
67
68 /**
69 * OBJECT_DECLARE_CPU_TYPE:
70 * @CpuInstanceType: instance struct name
71 * @CpuClassType: class struct name
72 * @CPU_MODULE_OBJ_NAME: the CPU name in uppercase with underscore separators
73 *
74 * This macro is typically used in "cpu-qom.h" header file, and will:
75 *
76 * - create the typedefs for the CPU object and class structs
77 * - register the type for use with g_autoptr
78 * - provide three standard type cast functions
79 *
80 * The object struct and class struct need to be declared manually.
81 */
82 #define OBJECT_DECLARE_CPU_TYPE(CpuInstanceType, CpuClassType, CPU_MODULE_OBJ_NAME) \
83 typedef struct ArchCPU CpuInstanceType; \
84 OBJECT_DECLARE_TYPE(ArchCPU, CpuClassType, CPU_MODULE_OBJ_NAME);
85
86 typedef struct CPUWatchpoint CPUWatchpoint;
87
88 /* see physmem.c */
89 struct CPUAddressSpace;
90
91 /* see accel/tcg/tb-jmp-cache.h */
92 struct CPUJumpCache;
93
94 /* see accel-cpu.h */
95 struct AccelCPUClass;
96
97 /* see sysemu-cpu-ops.h */
98 struct SysemuCPUOps;
99
100 /**
101 * CPUClass:
102 * @class_by_name: Callback to map -cpu command line model name to an
103 * instantiatable CPU type.
104 * @parse_features: Callback to parse command line arguments.
105 * @reset_dump_flags: #CPUDumpFlags to use for reset logging.
106 * @has_work: Callback for checking if there is work to do.
107 * @mmu_index: Callback for choosing softmmu mmu index;
108 * may be used internally by memory_rw_debug without TCG.
109 * @memory_rw_debug: Callback for GDB memory access.
110 * @dump_state: Callback for dumping state.
111 * @query_cpu_fast:
112 * Fill in target specific information for the "query-cpus-fast"
113 * QAPI call.
114 * @get_arch_id: Callback for getting architecture-dependent CPU ID.
115 * @set_pc: Callback for setting the Program Counter register. This
116 * should have the semantics used by the target architecture when
117 * setting the PC from a source such as an ELF file entry point;
118 * for example on Arm it will also set the Thumb mode bit based
119 * on the least significant bit of the new PC value.
120 * If the target behaviour here is anything other than "set
121 * the PC register to the value passed in" then the target must
122 * also implement the synchronize_from_tb hook.
123 * @get_pc: Callback for getting the Program Counter register.
124 * As above, with the semantics of the target architecture.
125 * @gdb_read_register: Callback for letting GDB read a register.
126 * @gdb_write_register: Callback for letting GDB write a register.
127 * @gdb_adjust_breakpoint: Callback for adjusting the address of a
128 * breakpoint. Used by AVR to handle a gdb mis-feature with
129 * its Harvard architecture split code and data.
130 * @gdb_num_core_regs: Number of core registers accessible to GDB or 0 to infer
131 * from @gdb_core_xml_file.
132 * @gdb_core_xml_file: File name for core registers GDB XML description.
133 * @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to stop
134 * before the insn which triggers a watchpoint rather than after it.
135 * @gdb_arch_name: Optional callback that returns the architecture name known
136 * to GDB. The caller must free the returned string with g_free.
137 * @disas_set_info: Setup architecture specific components of disassembly info
138 * @adjust_watchpoint_address: Perform a target-specific adjustment to an
139 * address before attempting to match it against watchpoints.
140 * @deprecation_note: If this CPUClass is deprecated, this field provides
141 * related information.
142 *
143 * Represents a CPU family or model.
144 */
145 struct CPUClass {
146 /*< private >*/
147 DeviceClass parent_class;
148 /*< public >*/
149
150 ObjectClass *(*class_by_name)(const char *cpu_model);
151 void (*parse_features)(const char *typename, char *str, Error **errp);
152
153 bool (*has_work)(CPUState *cpu);
154 int (*mmu_index)(CPUState *cpu, bool ifetch);
155 int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
156 uint8_t *buf, int len, bool is_write);
157 void (*dump_state)(CPUState *cpu, FILE *, int flags);
158 void (*query_cpu_fast)(CPUState *cpu, CpuInfoFast *value);
159 int64_t (*get_arch_id)(CPUState *cpu);
160 void (*set_pc)(CPUState *cpu, vaddr value);
161 vaddr (*get_pc)(CPUState *cpu);
162 int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg);
163 int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
164 vaddr (*gdb_adjust_breakpoint)(CPUState *cpu, vaddr addr);
165
166 const char *gdb_core_xml_file;
167 const gchar * (*gdb_arch_name)(CPUState *cpu);
168
169 void (*disas_set_info)(CPUState *cpu, disassemble_info *info);
170
171 const char *deprecation_note;
172 struct AccelCPUClass *accel_cpu;
173
174 /* when system emulation is not available, this pointer is NULL */
175 const struct SysemuCPUOps *sysemu_ops;
176
177 /* when TCG is not available, this pointer is NULL */
178 const TCGCPUOps *tcg_ops;
179
180 /*
181 * if not NULL, this is called in order for the CPUClass to initialize
182 * class data that depends on the accelerator, see accel/accel-common.c.
183 */
184 void (*init_accel_cpu)(struct AccelCPUClass *accel_cpu, CPUClass *cc);
185
186 /*
187 * Keep non-pointer data at the end to minimize holes.
188 */
189 int reset_dump_flags;
190 int gdb_num_core_regs;
191 bool gdb_stop_before_watchpoint;
192 };
193
194 /*
195 * Fix the number of mmu modes to 16, which is also the maximum
196 * supported by the softmmu tlb api.
197 */
198 #define NB_MMU_MODES 16
199
200 /* Use a fully associative victim tlb of 8 entries. */
201 #define CPU_VTLB_SIZE 8
202
203 /*
204 * The full TLB entry, which is not accessed by generated TCG code,
205 * so the layout is not as critical as that of CPUTLBEntry. This is
206 * also why we don't want to combine the two structs.
207 */
208 typedef struct CPUTLBEntryFull {
209 /*
210 * @xlat_section contains:
211 * - in the lower TARGET_PAGE_BITS, a physical section number
212 * - with the lower TARGET_PAGE_BITS masked off, an offset which
213 * must be added to the virtual address to obtain:
214 * + the ram_addr_t of the target RAM (if the physical section
215 * number is PHYS_SECTION_NOTDIRTY or PHYS_SECTION_ROM)
216 * + the offset within the target MemoryRegion (otherwise)
217 */
218 hwaddr xlat_section;
219
220 /*
221 * @phys_addr contains the physical address in the address space
222 * given by cpu_asidx_from_attrs(cpu, @attrs).
223 */
224 hwaddr phys_addr;
225
226 /* @attrs contains the memory transaction attributes for the page. */
227 MemTxAttrs attrs;
228
229 /* @prot contains the complete protections for the page. */
230 uint8_t prot;
231
232 /* @lg_page_size contains the log2 of the page size. */
233 uint8_t lg_page_size;
234
235 /* Additional tlb flags requested by tlb_fill. */
236 uint8_t tlb_fill_flags;
237
238 /*
239 * Additional tlb flags for use by the slow path. If non-zero,
240 * the corresponding CPUTLBEntry comparator must have TLB_FORCE_SLOW.
241 */
242 uint8_t slow_flags[MMU_ACCESS_COUNT];
243
244 /*
245 * Allow target-specific additions to this structure.
246 * This may be used to cache items from the guest cpu
247 * page tables for later use by the implementation.
248 */
249 union {
250 /*
251 * Cache the attrs and shareability fields from the page table entry.
252 *
253 * For ARMMMUIdx_Stage2*, pte_attrs is the S2 descriptor bits [5:2].
254 * Otherwise, pte_attrs is the same as the MAIR_EL1 8-bit format.
255 * For shareability and guarded, as in the SH and GP fields respectively
256 * of the VMSAv8-64 PTEs.
257 */
258 struct {
259 uint8_t pte_attrs;
260 uint8_t shareability;
261 bool guarded;
262 } arm;
263 } extra;
264 } CPUTLBEntryFull;
265
266 /*
267 * Data elements that are per MMU mode, minus the bits accessed by
268 * the TCG fast path.
269 */
270 typedef struct CPUTLBDesc {
271 /*
272 * Describe a region covering all of the large pages allocated
273 * into the tlb. When any page within this region is flushed,
274 * we must flush the entire tlb. The region is matched if
275 * (addr & large_page_mask) == large_page_addr.
276 */
277 vaddr large_page_addr;
278 vaddr large_page_mask;
279 /* host time (in ns) at the beginning of the time window */
280 int64_t window_begin_ns;
281 /* maximum number of entries observed in the window */
282 size_t window_max_entries;
283 size_t n_used_entries;
284 /* The next index to use in the tlb victim table. */
285 size_t vindex;
286 /* The tlb victim table, in two parts. */
287 CPUTLBEntry vtable[CPU_VTLB_SIZE];
288 CPUTLBEntryFull vfulltlb[CPU_VTLB_SIZE];
289 CPUTLBEntryFull *fulltlb;
290 } CPUTLBDesc;
291
292 /*
293 * Data elements that are shared between all MMU modes.
294 */
295 typedef struct CPUTLBCommon {
296 /* Serialize updates to f.table and d.vtable, and others as noted. */
297 QemuSpin lock;
298 /*
299 * Within dirty, for each bit N, modifications have been made to
300 * mmu_idx N since the last time that mmu_idx was flushed.
301 * Protected by tlb_c.lock.
302 */
303 uint16_t dirty;
304 /*
305 * Statistics. These are not lock protected, but are read and
306 * written atomically. This allows the monitor to print a snapshot
307 * of the stats without interfering with the cpu.
308 */
309 size_t full_flush_count;
310 size_t part_flush_count;
311 size_t elide_flush_count;
312 } CPUTLBCommon;
313
314 /*
315 * The entire softmmu tlb, for all MMU modes.
316 * The meaning of each of the MMU modes is defined in the target code.
317 * Since this is placed within CPUNegativeOffsetState, the smallest
318 * negative offsets are at the end of the struct.
319 */
320 typedef struct CPUTLB {
321 #ifdef CONFIG_TCG
322 CPUTLBCommon c;
323 CPUTLBDesc d[NB_MMU_MODES];
324 CPUTLBDescFast f[NB_MMU_MODES];
325 #endif
326 } CPUTLB;
327
328 /*
329 * Low 16 bits: number of cycles left, used only in icount mode.
330 * High 16 bits: Set to -1 to force TCG to stop executing linked TBs
331 * for this CPU and return to its top level loop (even in non-icount mode).
332 * This allows a single read-compare-cbranch-write sequence to test
333 * for both decrementer underflow and exceptions.
334 */
335 typedef union IcountDecr {
336 uint32_t u32;
337 struct {
338 #if HOST_BIG_ENDIAN
339 uint16_t high;
340 uint16_t low;
341 #else
342 uint16_t low;
343 uint16_t high;
344 #endif
345 } u16;
346 } IcountDecr;
347
348 /**
349 * CPUNegativeOffsetState: Elements of CPUState most efficiently accessed
350 * from CPUArchState, via small negative offsets.
351 * @can_do_io: True if memory-mapped IO is allowed.
352 * @plugin_mem_cbs: active plugin memory callbacks
353 * @plugin_mem_value_low: 64 lower bits of latest accessed mem value.
354 * @plugin_mem_value_high: 64 higher bits of latest accessed mem value.
355 */
356 typedef struct CPUNegativeOffsetState {
357 CPUTLB tlb;
358 #ifdef CONFIG_PLUGIN
359 /*
360 * The callback pointer are accessed via TCG (see gen_empty_mem_helper).
361 */
362 GArray *plugin_mem_cbs;
363 uint64_t plugin_mem_value_low;
364 uint64_t plugin_mem_value_high;
365 #endif
366 IcountDecr icount_decr;
367 bool can_do_io;
368 } CPUNegativeOffsetState;
369
370 struct KVMState;
371 struct kvm_run;
372
373 /* work queue */
374
375 /* The union type allows passing of 64 bit target pointers on 32 bit
376 * hosts in a single parameter
377 */
378 typedef union {
379 int host_int;
380 unsigned long host_ulong;
381 void *host_ptr;
382 vaddr target_ptr;
383 } run_on_cpu_data;
384
385 #define RUN_ON_CPU_HOST_PTR(p) ((run_on_cpu_data){.host_ptr = (p)})
386 #define RUN_ON_CPU_HOST_INT(i) ((run_on_cpu_data){.host_int = (i)})
387 #define RUN_ON_CPU_HOST_ULONG(ul) ((run_on_cpu_data){.host_ulong = (ul)})
388 #define RUN_ON_CPU_TARGET_PTR(v) ((run_on_cpu_data){.target_ptr = (v)})
389 #define RUN_ON_CPU_NULL RUN_ON_CPU_HOST_PTR(NULL)
390
391 typedef void (*run_on_cpu_func)(CPUState *cpu, run_on_cpu_data data);
392
393 struct qemu_work_item;
394
395 #define CPU_UNSET_NUMA_NODE_ID -1
396
397 /**
398 * struct CPUState - common state of one CPU core or thread.
399 *
400 * @cpu_index: CPU index (informative).
401 * @cluster_index: Identifies which cluster this CPU is in.
402 * For boards which don't define clusters or for "loose" CPUs not assigned
403 * to a cluster this will be UNASSIGNED_CLUSTER_INDEX; otherwise it will
404 * be the same as the cluster-id property of the CPU object's TYPE_CPU_CLUSTER
405 * QOM parent.
406 * Under TCG this value is propagated to @tcg_cflags.
407 * See TranslationBlock::TCG CF_CLUSTER_MASK.
408 * @tcg_cflags: Pre-computed cflags for this cpu.
409 * @nr_cores: Number of cores within this CPU package.
410 * @nr_threads: Number of threads within this CPU core.
411 * @thread: Host thread details, only live once @created is #true
412 * @sem: WIN32 only semaphore used only for qtest
413 * @thread_id: native thread id of vCPU, only live once @created is #true
414 * @running: #true if CPU is currently running (lockless).
415 * @has_waiter: #true if a CPU is currently waiting for the cpu_exec_end;
416 * valid under cpu_list_lock.
417 * @created: Indicates whether the CPU thread has been successfully created.
418 * @halt_cond: condition variable sleeping threads can wait on.
419 * @interrupt_request: Indicates a pending interrupt request.
420 * @halted: Nonzero if the CPU is in suspended state.
421 * @stop: Indicates a pending stop request.
422 * @stopped: Indicates the CPU has been artificially stopped.
423 * @unplug: Indicates a pending CPU unplug request.
424 * @crash_occurred: Indicates the OS reported a crash (panic) for this CPU
425 * @singlestep_enabled: Flags for single-stepping.
426 * @icount_extra: Instructions until next timer event.
427 * @cpu_ases: Pointer to array of CPUAddressSpaces (which define the
428 * AddressSpaces this CPU has)
429 * @num_ases: number of CPUAddressSpaces in @cpu_ases
430 * @as: Pointer to the first AddressSpace, for the convenience of targets which
431 * only have a single AddressSpace
432 * @gdb_regs: Additional GDB registers.
433 * @gdb_num_regs: Number of total registers accessible to GDB.
434 * @gdb_num_g_regs: Number of registers in GDB 'g' packets.
435 * @node: QTAILQ of CPUs sharing TB cache.
436 * @opaque: User data.
437 * @mem_io_pc: Host Program Counter at which the memory was accessed.
438 * @accel: Pointer to accelerator specific state.
439 * @kvm_fd: vCPU file descriptor for KVM.
440 * @work_mutex: Lock to prevent multiple access to @work_list.
441 * @work_list: List of pending asynchronous work.
442 * @plugin_state: per-CPU plugin state
443 * @ignore_memory_transaction_failures: Cached copy of the MachineState
444 * flag of the same name: allows the board to suppress calling of the
445 * CPU do_transaction_failed hook function.
446 * @kvm_dirty_gfns: Points to the KVM dirty ring for this CPU when KVM dirty
447 * ring is enabled.
448 * @kvm_fetch_index: Keeps the index that we last fetched from the per-vCPU
449 * dirty ring structure.
450 *
451 * @neg_align: The CPUState is the common part of a concrete ArchCPU
452 * which is allocated when an individual CPU instance is created. As
453 * such care is taken is ensure there is no gap between between
454 * CPUState and CPUArchState within ArchCPU.
455 *
456 * @neg: The architectural register state ("cpu_env") immediately follows
457 * CPUState in ArchCPU and is passed to TCG code. The @neg structure holds
458 * some common TCG CPU variables which are accessed with a negative offset
459 * from cpu_env.
460 */
461 struct CPUState {
462 /*< private >*/
463 DeviceState parent_obj;
464 /* cache to avoid expensive CPU_GET_CLASS */
465 CPUClass *cc;
466 /*< public >*/
467
468 int nr_cores;
469 int nr_threads;
470
471 struct QemuThread *thread;
472 #ifdef _WIN32
473 QemuSemaphore sem;
474 #endif
475 int thread_id;
476 bool running, has_waiter;
477 struct QemuCond *halt_cond;
478 bool thread_kicked;
479 bool created;
480 bool stop;
481 bool stopped;
482
483 /* Should CPU start in powered-off state? */
484 bool start_powered_off;
485
486 bool unplug;
487 bool crash_occurred;
488 bool exit_request;
489 int exclusive_context_count;
490 uint32_t cflags_next_tb;
491 /* updates protected by BQL */
492 uint32_t interrupt_request;
493 int singlestep_enabled;
494 int64_t icount_budget;
495 int64_t icount_extra;
496 uint64_t random_seed;
497 sigjmp_buf jmp_env;
498
499 QemuMutex work_mutex;
500 QSIMPLEQ_HEAD(, qemu_work_item) work_list;
501
502 struct CPUAddressSpace *cpu_ases;
503 int cpu_ases_count;
504 int num_ases;
505 AddressSpace *as;
506 MemoryRegion *memory;
507
508 struct CPUJumpCache *tb_jmp_cache;
509
510 GArray *gdb_regs;
511 int gdb_num_regs;
512 int gdb_num_g_regs;
513 QTAILQ_ENTRY(CPUState) node;
514
515 /* ice debug support */
516 QTAILQ_HEAD(, CPUBreakpoint) breakpoints;
517
518 QTAILQ_HEAD(, CPUWatchpoint) watchpoints;
519 CPUWatchpoint *watchpoint_hit;
520
521 void *opaque;
522
523 /* In order to avoid passing too many arguments to the MMIO helpers,
524 * we store some rarely used information in the CPU context.
525 */
526 uintptr_t mem_io_pc;
527
528 /* Only used in KVM */
529 int kvm_fd;
530 struct KVMState *kvm_state;
531 struct kvm_run *kvm_run;
532 struct kvm_dirty_gfn *kvm_dirty_gfns;
533 uint32_t kvm_fetch_index;
534 uint64_t dirty_pages;
535 int kvm_vcpu_stats_fd;
536 bool vcpu_dirty;
537
538 /* Use by accel-block: CPU is executing an ioctl() */
539 QemuLockCnt in_ioctl_lock;
540
541 #ifdef CONFIG_PLUGIN
542 CPUPluginState *plugin_state;
543 #endif
544
545 /* TODO Move common fields from CPUArchState here. */
546 int cpu_index;
547 int cluster_index;
548 uint32_t tcg_cflags;
549 uint32_t halted;
550 int32_t exception_index;
551
552 AccelCPUState *accel;
553
554 /* Used to keep track of an outstanding cpu throttle thread for migration
555 * autoconverge
556 */
557 bool throttle_thread_scheduled;
558
559 /*
560 * Sleep throttle_us_per_full microseconds once dirty ring is full
561 * if dirty page rate limit is enabled.
562 */
563 int64_t throttle_us_per_full;
564
565 bool ignore_memory_transaction_failures;
566
567 /* Used for user-only emulation of prctl(PR_SET_UNALIGN). */
568 bool prctl_unalign_sigbus;
569
570 /* track IOMMUs whose translations we've cached in the TCG TLB */
571 GArray *iommu_notifiers;
572
573 /*
574 * MUST BE LAST in order to minimize the displacement to CPUArchState.
575 */
576 char neg_align[-sizeof(CPUNegativeOffsetState) % 16] QEMU_ALIGNED(16);
577 CPUNegativeOffsetState neg;
578 };
579
580 /* Validate placement of CPUNegativeOffsetState. */
581 QEMU_BUILD_BUG_ON(offsetof(CPUState, neg) !=
582 sizeof(CPUState) - sizeof(CPUNegativeOffsetState));
583
cpu_env(CPUState * cpu)584 static inline CPUArchState *cpu_env(CPUState *cpu)
585 {
586 /* We validate that CPUArchState follows CPUState in cpu-all.h. */
587 return (CPUArchState *)(cpu + 1);
588 }
589
590 typedef QTAILQ_HEAD(CPUTailQ, CPUState) CPUTailQ;
591 extern CPUTailQ cpus_queue;
592
593 #define first_cpu QTAILQ_FIRST_RCU(&cpus_queue)
594 #define CPU_NEXT(cpu) QTAILQ_NEXT_RCU(cpu, node)
595 #define CPU_FOREACH(cpu) QTAILQ_FOREACH_RCU(cpu, &cpus_queue, node)
596 #define CPU_FOREACH_SAFE(cpu, next_cpu) \
597 QTAILQ_FOREACH_SAFE_RCU(cpu, &cpus_queue, node, next_cpu)
598
599 extern __thread CPUState *current_cpu;
600
601 /**
602 * qemu_tcg_mttcg_enabled:
603 * Check whether we are running MultiThread TCG or not.
604 *
605 * Returns: %true if we are in MTTCG mode %false otherwise.
606 */
607 extern bool mttcg_enabled;
608 #define qemu_tcg_mttcg_enabled() (mttcg_enabled)
609
610 /**
611 * cpu_paging_enabled:
612 * @cpu: The CPU whose state is to be inspected.
613 *
614 * Returns: %true if paging is enabled, %false otherwise.
615 */
616 bool cpu_paging_enabled(const CPUState *cpu);
617
618 /**
619 * cpu_get_memory_mapping:
620 * @cpu: The CPU whose memory mappings are to be obtained.
621 * @list: Where to write the memory mappings to.
622 * @errp: Pointer for reporting an #Error.
623 *
624 * Returns: %true on success, %false otherwise.
625 */
626 bool cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
627 Error **errp);
628
629 #if !defined(CONFIG_USER_ONLY)
630
631 /**
632 * cpu_write_elf64_note:
633 * @f: pointer to a function that writes memory to a file
634 * @cpu: The CPU whose memory is to be dumped
635 * @cpuid: ID number of the CPU
636 * @opaque: pointer to the CPUState struct
637 */
638 int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
639 int cpuid, void *opaque);
640
641 /**
642 * cpu_write_elf64_qemunote:
643 * @f: pointer to a function that writes memory to a file
644 * @cpu: The CPU whose memory is to be dumped
645 * @cpuid: ID number of the CPU
646 * @opaque: pointer to the CPUState struct
647 */
648 int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
649 void *opaque);
650
651 /**
652 * cpu_write_elf32_note:
653 * @f: pointer to a function that writes memory to a file
654 * @cpu: The CPU whose memory is to be dumped
655 * @cpuid: ID number of the CPU
656 * @opaque: pointer to the CPUState struct
657 */
658 int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
659 int cpuid, void *opaque);
660
661 /**
662 * cpu_write_elf32_qemunote:
663 * @f: pointer to a function that writes memory to a file
664 * @cpu: The CPU whose memory is to be dumped
665 * @cpuid: ID number of the CPU
666 * @opaque: pointer to the CPUState struct
667 */
668 int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
669 void *opaque);
670
671 /**
672 * cpu_get_crash_info:
673 * @cpu: The CPU to get crash information for
674 *
675 * Gets the previously saved crash information.
676 * Caller is responsible for freeing the data.
677 */
678 GuestPanicInformation *cpu_get_crash_info(CPUState *cpu);
679
680 #endif /* !CONFIG_USER_ONLY */
681
682 /**
683 * CPUDumpFlags:
684 * @CPU_DUMP_CODE:
685 * @CPU_DUMP_FPU: dump FPU register state, not just integer
686 * @CPU_DUMP_CCOP: dump info about TCG QEMU's condition code optimization state
687 * @CPU_DUMP_VPU: dump VPU registers
688 */
689 enum CPUDumpFlags {
690 CPU_DUMP_CODE = 0x00010000,
691 CPU_DUMP_FPU = 0x00020000,
692 CPU_DUMP_CCOP = 0x00040000,
693 CPU_DUMP_VPU = 0x00080000,
694 };
695
696 /**
697 * cpu_dump_state:
698 * @cpu: The CPU whose state is to be dumped.
699 * @f: If non-null, dump to this stream, else to current print sink.
700 *
701 * Dumps CPU state.
702 */
703 void cpu_dump_state(CPUState *cpu, FILE *f, int flags);
704
705 #ifndef CONFIG_USER_ONLY
706 /**
707 * cpu_get_phys_page_attrs_debug:
708 * @cpu: The CPU to obtain the physical page address for.
709 * @addr: The virtual address.
710 * @attrs: Updated on return with the memory transaction attributes to use
711 * for this access.
712 *
713 * Obtains the physical page corresponding to a virtual one, together
714 * with the corresponding memory transaction attributes to use for the access.
715 * Use it only for debugging because no protection checks are done.
716 *
717 * Returns: Corresponding physical page address or -1 if no page found.
718 */
719 hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
720 MemTxAttrs *attrs);
721
722 /**
723 * cpu_get_phys_page_debug:
724 * @cpu: The CPU to obtain the physical page address for.
725 * @addr: The virtual address.
726 *
727 * Obtains the physical page corresponding to a virtual one.
728 * Use it only for debugging because no protection checks are done.
729 *
730 * Returns: Corresponding physical page address or -1 if no page found.
731 */
732 hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
733
734 /** cpu_asidx_from_attrs:
735 * @cpu: CPU
736 * @attrs: memory transaction attributes
737 *
738 * Returns the address space index specifying the CPU AddressSpace
739 * to use for a memory access with the given transaction attributes.
740 */
741 int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs);
742
743 /**
744 * cpu_virtio_is_big_endian:
745 * @cpu: CPU
746
747 * Returns %true if a CPU which supports runtime configurable endianness
748 * is currently big-endian.
749 */
750 bool cpu_virtio_is_big_endian(CPUState *cpu);
751
752 #endif /* CONFIG_USER_ONLY */
753
754 /**
755 * cpu_list_add:
756 * @cpu: The CPU to be added to the list of CPUs.
757 */
758 void cpu_list_add(CPUState *cpu);
759
760 /**
761 * cpu_list_remove:
762 * @cpu: The CPU to be removed from the list of CPUs.
763 */
764 void cpu_list_remove(CPUState *cpu);
765
766 /**
767 * cpu_reset:
768 * @cpu: The CPU whose state is to be reset.
769 */
770 void cpu_reset(CPUState *cpu);
771
772 /**
773 * cpu_class_by_name:
774 * @typename: The CPU base type.
775 * @cpu_model: The model string without any parameters.
776 *
777 * Looks up a concrete CPU #ObjectClass matching name @cpu_model.
778 *
779 * Returns: A concrete #CPUClass or %NULL if no matching class is found
780 * or if the matching class is abstract.
781 */
782 ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model);
783
784 /**
785 * cpu_model_from_type:
786 * @typename: The CPU type name
787 *
788 * Extract the CPU model name from the CPU type name. The
789 * CPU type name is either the combination of the CPU model
790 * name and suffix, or same to the CPU model name.
791 *
792 * Returns: CPU model name or NULL if the CPU class doesn't exist
793 * The user should g_free() the string once no longer needed.
794 */
795 char *cpu_model_from_type(const char *typename);
796
797 /**
798 * cpu_create:
799 * @typename: The CPU type.
800 *
801 * Instantiates a CPU and realizes the CPU.
802 *
803 * Returns: A #CPUState or %NULL if an error occurred.
804 */
805 CPUState *cpu_create(const char *typename);
806
807 /**
808 * parse_cpu_option:
809 * @cpu_option: The -cpu option including optional parameters.
810 *
811 * processes optional parameters and registers them as global properties
812 *
813 * Returns: type of CPU to create or prints error and terminates process
814 * if an error occurred.
815 */
816 const char *parse_cpu_option(const char *cpu_option);
817
818 /**
819 * cpu_has_work:
820 * @cpu: The vCPU to check.
821 *
822 * Checks whether the CPU has work to do.
823 *
824 * Returns: %true if the CPU has work, %false otherwise.
825 */
cpu_has_work(CPUState * cpu)826 static inline bool cpu_has_work(CPUState *cpu)
827 {
828 CPUClass *cc = CPU_GET_CLASS(cpu);
829
830 g_assert(cc->has_work);
831 return cc->has_work(cpu);
832 }
833
834 /**
835 * qemu_cpu_is_self:
836 * @cpu: The vCPU to check against.
837 *
838 * Checks whether the caller is executing on the vCPU thread.
839 *
840 * Returns: %true if called from @cpu's thread, %false otherwise.
841 */
842 bool qemu_cpu_is_self(CPUState *cpu);
843
844 /**
845 * qemu_cpu_kick:
846 * @cpu: The vCPU to kick.
847 *
848 * Kicks @cpu's thread.
849 */
850 void qemu_cpu_kick(CPUState *cpu);
851
852 /**
853 * cpu_is_stopped:
854 * @cpu: The CPU to check.
855 *
856 * Checks whether the CPU is stopped.
857 *
858 * Returns: %true if run state is not running or if artificially stopped;
859 * %false otherwise.
860 */
861 bool cpu_is_stopped(CPUState *cpu);
862
863 /**
864 * do_run_on_cpu:
865 * @cpu: The vCPU to run on.
866 * @func: The function to be executed.
867 * @data: Data to pass to the function.
868 * @mutex: Mutex to release while waiting for @func to run.
869 *
870 * Used internally in the implementation of run_on_cpu.
871 */
872 void do_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data,
873 QemuMutex *mutex);
874
875 /**
876 * run_on_cpu:
877 * @cpu: The vCPU to run on.
878 * @func: The function to be executed.
879 * @data: Data to pass to the function.
880 *
881 * Schedules the function @func for execution on the vCPU @cpu.
882 */
883 void run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data);
884
885 /**
886 * async_run_on_cpu:
887 * @cpu: The vCPU to run on.
888 * @func: The function to be executed.
889 * @data: Data to pass to the function.
890 *
891 * Schedules the function @func for execution on the vCPU @cpu asynchronously.
892 */
893 void async_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data);
894
895 /**
896 * async_safe_run_on_cpu:
897 * @cpu: The vCPU to run on.
898 * @func: The function to be executed.
899 * @data: Data to pass to the function.
900 *
901 * Schedules the function @func for execution on the vCPU @cpu asynchronously,
902 * while all other vCPUs are sleeping.
903 *
904 * Unlike run_on_cpu and async_run_on_cpu, the function is run outside the
905 * BQL.
906 */
907 void async_safe_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data);
908
909 /**
910 * cpu_in_exclusive_context()
911 * @cpu: The vCPU to check
912 *
913 * Returns true if @cpu is an exclusive context, for example running
914 * something which has previously been queued via async_safe_run_on_cpu().
915 */
cpu_in_exclusive_context(const CPUState * cpu)916 static inline bool cpu_in_exclusive_context(const CPUState *cpu)
917 {
918 return cpu->exclusive_context_count;
919 }
920
921 /**
922 * qemu_get_cpu:
923 * @index: The CPUState@cpu_index value of the CPU to obtain.
924 *
925 * Gets a CPU matching @index.
926 *
927 * Returns: The CPU or %NULL if there is no matching CPU.
928 */
929 CPUState *qemu_get_cpu(int index);
930
931 /**
932 * cpu_exists:
933 * @id: Guest-exposed CPU ID to lookup.
934 *
935 * Search for CPU with specified ID.
936 *
937 * Returns: %true - CPU is found, %false - CPU isn't found.
938 */
939 bool cpu_exists(int64_t id);
940
941 /**
942 * cpu_by_arch_id:
943 * @id: Guest-exposed CPU ID of the CPU to obtain.
944 *
945 * Get a CPU with matching @id.
946 *
947 * Returns: The CPU or %NULL if there is no matching CPU.
948 */
949 CPUState *cpu_by_arch_id(int64_t id);
950
951 /**
952 * cpu_interrupt:
953 * @cpu: The CPU to set an interrupt on.
954 * @mask: The interrupts to set.
955 *
956 * Invokes the interrupt handler.
957 */
958
959 void cpu_interrupt(CPUState *cpu, int mask);
960
961 /**
962 * cpu_set_pc:
963 * @cpu: The CPU to set the program counter for.
964 * @addr: Program counter value.
965 *
966 * Sets the program counter for a CPU.
967 */
cpu_set_pc(CPUState * cpu,vaddr addr)968 static inline void cpu_set_pc(CPUState *cpu, vaddr addr)
969 {
970 CPUClass *cc = CPU_GET_CLASS(cpu);
971
972 cc->set_pc(cpu, addr);
973 }
974
975 /**
976 * cpu_reset_interrupt:
977 * @cpu: The CPU to clear the interrupt on.
978 * @mask: The interrupt mask to clear.
979 *
980 * Resets interrupts on the vCPU @cpu.
981 */
982 void cpu_reset_interrupt(CPUState *cpu, int mask);
983
984 /**
985 * cpu_exit:
986 * @cpu: The CPU to exit.
987 *
988 * Requests the CPU @cpu to exit execution.
989 */
990 void cpu_exit(CPUState *cpu);
991
992 /**
993 * cpu_pause:
994 * @cpu: The CPU to pause.
995 *
996 * Pauses CPU, i.e. puts CPU into stopped state.
997 */
998 void cpu_pause(CPUState *cpu);
999
1000 /**
1001 * cpu_resume:
1002 * @cpu: The CPU to resume.
1003 *
1004 * Resumes CPU, i.e. puts CPU into runnable state.
1005 */
1006 void cpu_resume(CPUState *cpu);
1007
1008 /**
1009 * cpu_remove_sync:
1010 * @cpu: The CPU to remove.
1011 *
1012 * Requests the CPU to be removed and waits till it is removed.
1013 */
1014 void cpu_remove_sync(CPUState *cpu);
1015
1016 /**
1017 * free_queued_cpu_work() - free all items on CPU work queue
1018 * @cpu: The CPU which work queue to free.
1019 */
1020 void free_queued_cpu_work(CPUState *cpu);
1021
1022 /**
1023 * process_queued_cpu_work() - process all items on CPU work queue
1024 * @cpu: The CPU which work queue to process.
1025 */
1026 void process_queued_cpu_work(CPUState *cpu);
1027
1028 /**
1029 * cpu_exec_start:
1030 * @cpu: The CPU for the current thread.
1031 *
1032 * Record that a CPU has started execution and can be interrupted with
1033 * cpu_exit.
1034 */
1035 void cpu_exec_start(CPUState *cpu);
1036
1037 /**
1038 * cpu_exec_end:
1039 * @cpu: The CPU for the current thread.
1040 *
1041 * Record that a CPU has stopped execution and exclusive sections
1042 * can be executed without interrupting it.
1043 */
1044 void cpu_exec_end(CPUState *cpu);
1045
1046 /**
1047 * start_exclusive:
1048 *
1049 * Wait for a concurrent exclusive section to end, and then start
1050 * a section of work that is run while other CPUs are not running
1051 * between cpu_exec_start and cpu_exec_end. CPUs that are running
1052 * cpu_exec are exited immediately. CPUs that call cpu_exec_start
1053 * during the exclusive section go to sleep until this CPU calls
1054 * end_exclusive.
1055 */
1056 void start_exclusive(void);
1057
1058 /**
1059 * end_exclusive:
1060 *
1061 * Concludes an exclusive execution section started by start_exclusive.
1062 */
1063 void end_exclusive(void);
1064
1065 /**
1066 * qemu_init_vcpu:
1067 * @cpu: The vCPU to initialize.
1068 *
1069 * Initializes a vCPU.
1070 */
1071 void qemu_init_vcpu(CPUState *cpu);
1072
1073 #define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */
1074 #define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */
1075 #define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */
1076
1077 /**
1078 * cpu_single_step:
1079 * @cpu: CPU to the flags for.
1080 * @enabled: Flags to enable.
1081 *
1082 * Enables or disables single-stepping for @cpu.
1083 */
1084 void cpu_single_step(CPUState *cpu, int enabled);
1085
1086 /* Breakpoint/watchpoint flags */
1087 #define BP_MEM_READ 0x01
1088 #define BP_MEM_WRITE 0x02
1089 #define BP_MEM_ACCESS (BP_MEM_READ | BP_MEM_WRITE)
1090 #define BP_STOP_BEFORE_ACCESS 0x04
1091 /* 0x08 currently unused */
1092 #define BP_GDB 0x10
1093 #define BP_CPU 0x20
1094 #define BP_ANY (BP_GDB | BP_CPU)
1095 #define BP_HIT_SHIFT 6
1096 #define BP_WATCHPOINT_HIT_READ (BP_MEM_READ << BP_HIT_SHIFT)
1097 #define BP_WATCHPOINT_HIT_WRITE (BP_MEM_WRITE << BP_HIT_SHIFT)
1098 #define BP_WATCHPOINT_HIT (BP_MEM_ACCESS << BP_HIT_SHIFT)
1099
1100 int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
1101 CPUBreakpoint **breakpoint);
1102 int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags);
1103 void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint);
1104 void cpu_breakpoint_remove_all(CPUState *cpu, int mask);
1105
1106 /* Return true if PC matches an installed breakpoint. */
cpu_breakpoint_test(CPUState * cpu,vaddr pc,int mask)1107 static inline bool cpu_breakpoint_test(CPUState *cpu, vaddr pc, int mask)
1108 {
1109 CPUBreakpoint *bp;
1110
1111 if (unlikely(!QTAILQ_EMPTY(&cpu->breakpoints))) {
1112 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
1113 if (bp->pc == pc && (bp->flags & mask)) {
1114 return true;
1115 }
1116 }
1117 }
1118 return false;
1119 }
1120
1121 #if defined(CONFIG_USER_ONLY)
cpu_watchpoint_insert(CPUState * cpu,vaddr addr,vaddr len,int flags,CPUWatchpoint ** watchpoint)1122 static inline int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
1123 int flags, CPUWatchpoint **watchpoint)
1124 {
1125 return -ENOSYS;
1126 }
1127
cpu_watchpoint_remove(CPUState * cpu,vaddr addr,vaddr len,int flags)1128 static inline int cpu_watchpoint_remove(CPUState *cpu, vaddr addr,
1129 vaddr len, int flags)
1130 {
1131 return -ENOSYS;
1132 }
1133
cpu_watchpoint_remove_by_ref(CPUState * cpu,CPUWatchpoint * wp)1134 static inline void cpu_watchpoint_remove_by_ref(CPUState *cpu,
1135 CPUWatchpoint *wp)
1136 {
1137 }
1138
cpu_watchpoint_remove_all(CPUState * cpu,int mask)1139 static inline void cpu_watchpoint_remove_all(CPUState *cpu, int mask)
1140 {
1141 }
1142 #else
1143 int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
1144 int flags, CPUWatchpoint **watchpoint);
1145 int cpu_watchpoint_remove(CPUState *cpu, vaddr addr,
1146 vaddr len, int flags);
1147 void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint);
1148 void cpu_watchpoint_remove_all(CPUState *cpu, int mask);
1149 #endif
1150
1151 /**
1152 * cpu_get_address_space:
1153 * @cpu: CPU to get address space from
1154 * @asidx: index identifying which address space to get
1155 *
1156 * Return the requested address space of this CPU. @asidx
1157 * specifies which address space to read.
1158 */
1159 AddressSpace *cpu_get_address_space(CPUState *cpu, int asidx);
1160
1161 G_NORETURN void cpu_abort(CPUState *cpu, const char *fmt, ...)
1162 G_GNUC_PRINTF(2, 3);
1163
1164 /* $(top_srcdir)/cpu.c */
1165 void cpu_class_init_props(DeviceClass *dc);
1166 void cpu_exec_initfn(CPUState *cpu);
1167 bool cpu_exec_realizefn(CPUState *cpu, Error **errp);
1168 void cpu_exec_unrealizefn(CPUState *cpu);
1169 void cpu_exec_reset_hold(CPUState *cpu);
1170
1171 const char *target_name(void);
1172
1173 #ifdef COMPILING_PER_TARGET
1174
1175 #ifndef CONFIG_USER_ONLY
1176
1177 extern const VMStateDescription vmstate_cpu_common;
1178
1179 #define VMSTATE_CPU() { \
1180 .name = "parent_obj", \
1181 .size = sizeof(CPUState), \
1182 .vmsd = &vmstate_cpu_common, \
1183 .flags = VMS_STRUCT, \
1184 .offset = 0, \
1185 }
1186 #endif /* !CONFIG_USER_ONLY */
1187
1188 #endif /* COMPILING_PER_TARGET */
1189
1190 #define UNASSIGNED_CPU_INDEX -1
1191 #define UNASSIGNED_CLUSTER_INDEX -1
1192
1193 #endif
1194