1 //===-- LiveIntervalAnalysis.cpp - Live Interval Analysis -----------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the LiveInterval analysis pass which is used
11 // by the Linear Scan Register allocator. This pass linearizes the
12 // basic blocks of the function in DFS order and uses the
13 // LiveVariables pass to conservatively compute live intervals for
14 // each virtual and physical register.
15 //
16 //===----------------------------------------------------------------------===//
17
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "LiveRangeCalc.h"
20 #include "llvm/ADT/DenseSet.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/Analysis/AliasAnalysis.h"
23 #include "llvm/CodeGen/LiveVariables.h"
24 #include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
25 #include "llvm/CodeGen/MachineDominators.h"
26 #include "llvm/CodeGen/MachineInstr.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/Passes.h"
29 #include "llvm/CodeGen/VirtRegMap.h"
30 #include "llvm/IR/Value.h"
31 #include "llvm/Support/BlockFrequency.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/Format.h"
36 #include "llvm/Support/raw_ostream.h"
37 #include "llvm/Target/TargetInstrInfo.h"
38 #include "llvm/Target/TargetRegisterInfo.h"
39 #include "llvm/Target/TargetSubtargetInfo.h"
40 #include <algorithm>
41 #include <cmath>
42 #include <limits>
43 using namespace llvm;
44
45 #define DEBUG_TYPE "regalloc"
46
47 char LiveIntervals::ID = 0;
48 char &llvm::LiveIntervalsID = LiveIntervals::ID;
49 INITIALIZE_PASS_BEGIN(LiveIntervals, "liveintervals",
50 "Live Interval Analysis", false, false)
51 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
52 INITIALIZE_PASS_DEPENDENCY(LiveVariables)
53 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
54 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
55 INITIALIZE_PASS_END(LiveIntervals, "liveintervals",
56 "Live Interval Analysis", false, false)
57
58 #ifndef NDEBUG
59 static cl::opt<bool> EnablePrecomputePhysRegs(
60 "precompute-phys-liveness", cl::Hidden,
61 cl::desc("Eagerly compute live intervals for all physreg units."));
62 #else
63 static bool EnablePrecomputePhysRegs = false;
64 #endif // NDEBUG
65
66 static cl::opt<bool> EnableSubRegLiveness(
67 "enable-subreg-liveness", cl::Hidden, cl::init(true),
68 cl::desc("Enable subregister liveness tracking."));
69
getAnalysisUsage(AnalysisUsage & AU) const70 void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const {
71 AU.setPreservesCFG();
72 AU.addRequired<AliasAnalysis>();
73 AU.addPreserved<AliasAnalysis>();
74 // LiveVariables isn't really required by this analysis, it is only required
75 // here to make sure it is live during TwoAddressInstructionPass and
76 // PHIElimination. This is temporary.
77 AU.addRequired<LiveVariables>();
78 AU.addPreserved<LiveVariables>();
79 AU.addPreservedID(MachineLoopInfoID);
80 AU.addRequiredTransitiveID(MachineDominatorsID);
81 AU.addPreservedID(MachineDominatorsID);
82 AU.addPreserved<SlotIndexes>();
83 AU.addRequiredTransitive<SlotIndexes>();
84 MachineFunctionPass::getAnalysisUsage(AU);
85 }
86
LiveIntervals()87 LiveIntervals::LiveIntervals() : MachineFunctionPass(ID),
88 DomTree(nullptr), LRCalc(nullptr) {
89 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
90 }
91
~LiveIntervals()92 LiveIntervals::~LiveIntervals() {
93 delete LRCalc;
94 }
95
releaseMemory()96 void LiveIntervals::releaseMemory() {
97 // Free the live intervals themselves.
98 for (unsigned i = 0, e = VirtRegIntervals.size(); i != e; ++i)
99 delete VirtRegIntervals[TargetRegisterInfo::index2VirtReg(i)];
100 VirtRegIntervals.clear();
101 RegMaskSlots.clear();
102 RegMaskBits.clear();
103 RegMaskBlocks.clear();
104
105 for (unsigned i = 0, e = RegUnitRanges.size(); i != e; ++i)
106 delete RegUnitRanges[i];
107 RegUnitRanges.clear();
108
109 // Release VNInfo memory regions, VNInfo objects don't need to be dtor'd.
110 VNInfoAllocator.Reset();
111 }
112
113 /// runOnMachineFunction - calculates LiveIntervals
114 ///
runOnMachineFunction(MachineFunction & fn)115 bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
116 MF = &fn;
117 MRI = &MF->getRegInfo();
118 TRI = MF->getSubtarget().getRegisterInfo();
119 TII = MF->getSubtarget().getInstrInfo();
120 AA = &getAnalysis<AliasAnalysis>();
121 Indexes = &getAnalysis<SlotIndexes>();
122 DomTree = &getAnalysis<MachineDominatorTree>();
123
124 if (EnableSubRegLiveness && MF->getSubtarget().enableSubRegLiveness())
125 MRI->enableSubRegLiveness(true);
126
127 if (!LRCalc)
128 LRCalc = new LiveRangeCalc();
129
130 // Allocate space for all virtual registers.
131 VirtRegIntervals.resize(MRI->getNumVirtRegs());
132
133 computeVirtRegs();
134 computeRegMasks();
135 computeLiveInRegUnits();
136
137 if (EnablePrecomputePhysRegs) {
138 // For stress testing, precompute live ranges of all physical register
139 // units, including reserved registers.
140 for (unsigned i = 0, e = TRI->getNumRegUnits(); i != e; ++i)
141 getRegUnit(i);
142 }
143 DEBUG(dump());
144 return true;
145 }
146
147 /// print - Implement the dump method.
print(raw_ostream & OS,const Module *) const148 void LiveIntervals::print(raw_ostream &OS, const Module* ) const {
149 OS << "********** INTERVALS **********\n";
150
151 // Dump the regunits.
152 for (unsigned i = 0, e = RegUnitRanges.size(); i != e; ++i)
153 if (LiveRange *LR = RegUnitRanges[i])
154 OS << PrintRegUnit(i, TRI) << ' ' << *LR << '\n';
155
156 // Dump the virtregs.
157 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
158 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
159 if (hasInterval(Reg))
160 OS << getInterval(Reg) << '\n';
161 }
162
163 OS << "RegMasks:";
164 for (unsigned i = 0, e = RegMaskSlots.size(); i != e; ++i)
165 OS << ' ' << RegMaskSlots[i];
166 OS << '\n';
167
168 printInstrs(OS);
169 }
170
printInstrs(raw_ostream & OS) const171 void LiveIntervals::printInstrs(raw_ostream &OS) const {
172 OS << "********** MACHINEINSTRS **********\n";
173 MF->print(OS, Indexes);
174 }
175
176 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
dumpInstrs() const177 void LiveIntervals::dumpInstrs() const {
178 printInstrs(dbgs());
179 }
180 #endif
181
createInterval(unsigned reg)182 LiveInterval* LiveIntervals::createInterval(unsigned reg) {
183 float Weight = TargetRegisterInfo::isPhysicalRegister(reg) ?
184 llvm::huge_valf : 0.0F;
185 return new LiveInterval(reg, Weight);
186 }
187
188
189 /// computeVirtRegInterval - Compute the live interval of a virtual register,
190 /// based on defs and uses.
computeVirtRegInterval(LiveInterval & LI)191 void LiveIntervals::computeVirtRegInterval(LiveInterval &LI) {
192 assert(LRCalc && "LRCalc not initialized.");
193 assert(LI.empty() && "Should only compute empty intervals.");
194 LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
195 LRCalc->calculate(LI);
196 computeDeadValues(LI, nullptr);
197 }
198
computeVirtRegs()199 void LiveIntervals::computeVirtRegs() {
200 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
201 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
202 if (MRI->reg_nodbg_empty(Reg))
203 continue;
204 createAndComputeVirtRegInterval(Reg);
205 }
206 }
207
computeRegMasks()208 void LiveIntervals::computeRegMasks() {
209 RegMaskBlocks.resize(MF->getNumBlockIDs());
210
211 // Find all instructions with regmask operands.
212 for (MachineFunction::iterator MBBI = MF->begin(), E = MF->end();
213 MBBI != E; ++MBBI) {
214 MachineBasicBlock *MBB = MBBI;
215 std::pair<unsigned, unsigned> &RMB = RegMaskBlocks[MBB->getNumber()];
216 RMB.first = RegMaskSlots.size();
217 for (MachineBasicBlock::iterator MI = MBB->begin(), ME = MBB->end();
218 MI != ME; ++MI)
219 for (MIOperands MO(MI); MO.isValid(); ++MO) {
220 if (!MO->isRegMask())
221 continue;
222 RegMaskSlots.push_back(Indexes->getInstructionIndex(MI).getRegSlot());
223 RegMaskBits.push_back(MO->getRegMask());
224 }
225 // Compute the number of register mask instructions in this block.
226 RMB.second = RegMaskSlots.size() - RMB.first;
227 }
228 }
229
230 //===----------------------------------------------------------------------===//
231 // Register Unit Liveness
232 //===----------------------------------------------------------------------===//
233 //
234 // Fixed interference typically comes from ABI boundaries: Function arguments
235 // and return values are passed in fixed registers, and so are exception
236 // pointers entering landing pads. Certain instructions require values to be
237 // present in specific registers. That is also represented through fixed
238 // interference.
239 //
240
241 /// computeRegUnitInterval - Compute the live range of a register unit, based
242 /// on the uses and defs of aliasing registers. The range should be empty,
243 /// or contain only dead phi-defs from ABI blocks.
computeRegUnitRange(LiveRange & LR,unsigned Unit)244 void LiveIntervals::computeRegUnitRange(LiveRange &LR, unsigned Unit) {
245 assert(LRCalc && "LRCalc not initialized.");
246 LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
247
248 // The physregs aliasing Unit are the roots and their super-registers.
249 // Create all values as dead defs before extending to uses. Note that roots
250 // may share super-registers. That's OK because createDeadDefs() is
251 // idempotent. It is very rare for a register unit to have multiple roots, so
252 // uniquing super-registers is probably not worthwhile.
253 for (MCRegUnitRootIterator Roots(Unit, TRI); Roots.isValid(); ++Roots) {
254 for (MCSuperRegIterator Supers(*Roots, TRI, /*IncludeSelf=*/true);
255 Supers.isValid(); ++Supers) {
256 if (!MRI->reg_empty(*Supers))
257 LRCalc->createDeadDefs(LR, *Supers);
258 }
259 }
260
261 // Now extend LR to reach all uses.
262 // Ignore uses of reserved registers. We only track defs of those.
263 for (MCRegUnitRootIterator Roots(Unit, TRI); Roots.isValid(); ++Roots) {
264 for (MCSuperRegIterator Supers(*Roots, TRI, /*IncludeSelf=*/true);
265 Supers.isValid(); ++Supers) {
266 unsigned Reg = *Supers;
267 if (!MRI->isReserved(Reg) && !MRI->reg_empty(Reg))
268 LRCalc->extendToUses(LR, Reg);
269 }
270 }
271 }
272
273
274 /// computeLiveInRegUnits - Precompute the live ranges of any register units
275 /// that are live-in to an ABI block somewhere. Register values can appear
276 /// without a corresponding def when entering the entry block or a landing pad.
277 ///
computeLiveInRegUnits()278 void LiveIntervals::computeLiveInRegUnits() {
279 RegUnitRanges.resize(TRI->getNumRegUnits());
280 DEBUG(dbgs() << "Computing live-in reg-units in ABI blocks.\n");
281
282 // Keep track of the live range sets allocated.
283 SmallVector<unsigned, 8> NewRanges;
284
285 // Check all basic blocks for live-ins.
286 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
287 MFI != MFE; ++MFI) {
288 const MachineBasicBlock *MBB = MFI;
289
290 // We only care about ABI blocks: Entry + landing pads.
291 if ((MFI != MF->begin() && !MBB->isLandingPad()) || MBB->livein_empty())
292 continue;
293
294 // Create phi-defs at Begin for all live-in registers.
295 SlotIndex Begin = Indexes->getMBBStartIdx(MBB);
296 DEBUG(dbgs() << Begin << "\tBB#" << MBB->getNumber());
297 for (MachineBasicBlock::livein_iterator LII = MBB->livein_begin(),
298 LIE = MBB->livein_end(); LII != LIE; ++LII) {
299 for (MCRegUnitIterator Units(*LII, TRI); Units.isValid(); ++Units) {
300 unsigned Unit = *Units;
301 LiveRange *LR = RegUnitRanges[Unit];
302 if (!LR) {
303 LR = RegUnitRanges[Unit] = new LiveRange();
304 NewRanges.push_back(Unit);
305 }
306 VNInfo *VNI = LR->createDeadDef(Begin, getVNInfoAllocator());
307 (void)VNI;
308 DEBUG(dbgs() << ' ' << PrintRegUnit(Unit, TRI) << '#' << VNI->id);
309 }
310 }
311 DEBUG(dbgs() << '\n');
312 }
313 DEBUG(dbgs() << "Created " << NewRanges.size() << " new intervals.\n");
314
315 // Compute the 'normal' part of the ranges.
316 for (unsigned i = 0, e = NewRanges.size(); i != e; ++i) {
317 unsigned Unit = NewRanges[i];
318 computeRegUnitRange(*RegUnitRanges[Unit], Unit);
319 }
320 }
321
322
createSegmentsForValues(LiveRange & LR,iterator_range<LiveInterval::vni_iterator> VNIs)323 static void createSegmentsForValues(LiveRange &LR,
324 iterator_range<LiveInterval::vni_iterator> VNIs) {
325 for (auto VNI : VNIs) {
326 if (VNI->isUnused())
327 continue;
328 SlotIndex Def = VNI->def;
329 LR.addSegment(LiveRange::Segment(Def, Def.getDeadSlot(), VNI));
330 }
331 }
332
333 typedef SmallVector<std::pair<SlotIndex, VNInfo*>, 16> ShrinkToUsesWorkList;
334
extendSegmentsToUses(LiveRange & LR,const SlotIndexes & Indexes,ShrinkToUsesWorkList & WorkList,const LiveRange & OldRange)335 static void extendSegmentsToUses(LiveRange &LR, const SlotIndexes &Indexes,
336 ShrinkToUsesWorkList &WorkList,
337 const LiveRange &OldRange) {
338 // Keep track of the PHIs that are in use.
339 SmallPtrSet<VNInfo*, 8> UsedPHIs;
340 // Blocks that have already been added to WorkList as live-out.
341 SmallPtrSet<MachineBasicBlock*, 16> LiveOut;
342
343 // Extend intervals to reach all uses in WorkList.
344 while (!WorkList.empty()) {
345 SlotIndex Idx = WorkList.back().first;
346 VNInfo *VNI = WorkList.back().second;
347 WorkList.pop_back();
348 const MachineBasicBlock *MBB = Indexes.getMBBFromIndex(Idx.getPrevSlot());
349 SlotIndex BlockStart = Indexes.getMBBStartIdx(MBB);
350
351 // Extend the live range for VNI to be live at Idx.
352 if (VNInfo *ExtVNI = LR.extendInBlock(BlockStart, Idx)) {
353 assert(ExtVNI == VNI && "Unexpected existing value number");
354 (void)ExtVNI;
355 // Is this a PHIDef we haven't seen before?
356 if (!VNI->isPHIDef() || VNI->def != BlockStart ||
357 !UsedPHIs.insert(VNI).second)
358 continue;
359 // The PHI is live, make sure the predecessors are live-out.
360 for (auto &Pred : MBB->predecessors()) {
361 if (!LiveOut.insert(Pred).second)
362 continue;
363 SlotIndex Stop = Indexes.getMBBEndIdx(Pred);
364 // A predecessor is not required to have a live-out value for a PHI.
365 if (VNInfo *PVNI = OldRange.getVNInfoBefore(Stop))
366 WorkList.push_back(std::make_pair(Stop, PVNI));
367 }
368 continue;
369 }
370
371 // VNI is live-in to MBB.
372 DEBUG(dbgs() << " live-in at " << BlockStart << '\n');
373 LR.addSegment(LiveRange::Segment(BlockStart, Idx, VNI));
374
375 // Make sure VNI is live-out from the predecessors.
376 for (auto &Pred : MBB->predecessors()) {
377 if (!LiveOut.insert(Pred).second)
378 continue;
379 SlotIndex Stop = Indexes.getMBBEndIdx(Pred);
380 assert(OldRange.getVNInfoBefore(Stop) == VNI &&
381 "Wrong value out of predecessor");
382 WorkList.push_back(std::make_pair(Stop, VNI));
383 }
384 }
385 }
386
387 /// shrinkToUses - After removing some uses of a register, shrink its live
388 /// range to just the remaining uses. This method does not compute reaching
389 /// defs for new uses, and it doesn't remove dead defs.
shrinkToUses(LiveInterval * li,SmallVectorImpl<MachineInstr * > * dead)390 bool LiveIntervals::shrinkToUses(LiveInterval *li,
391 SmallVectorImpl<MachineInstr*> *dead) {
392 DEBUG(dbgs() << "Shrink: " << *li << '\n');
393 assert(TargetRegisterInfo::isVirtualRegister(li->reg)
394 && "Can only shrink virtual registers");
395
396 // Shrink subregister live ranges.
397 for (LiveInterval::SubRange &S : li->subranges()) {
398 shrinkToUses(S, li->reg);
399 }
400
401 // Find all the values used, including PHI kills.
402 ShrinkToUsesWorkList WorkList;
403
404 // Visit all instructions reading li->reg.
405 for (MachineRegisterInfo::reg_instr_iterator
406 I = MRI->reg_instr_begin(li->reg), E = MRI->reg_instr_end();
407 I != E; ) {
408 MachineInstr *UseMI = &*(I++);
409 if (UseMI->isDebugValue() || !UseMI->readsVirtualRegister(li->reg))
410 continue;
411 SlotIndex Idx = getInstructionIndex(UseMI).getRegSlot();
412 LiveQueryResult LRQ = li->Query(Idx);
413 VNInfo *VNI = LRQ.valueIn();
414 if (!VNI) {
415 // This shouldn't happen: readsVirtualRegister returns true, but there is
416 // no live value. It is likely caused by a target getting <undef> flags
417 // wrong.
418 DEBUG(dbgs() << Idx << '\t' << *UseMI
419 << "Warning: Instr claims to read non-existent value in "
420 << *li << '\n');
421 continue;
422 }
423 // Special case: An early-clobber tied operand reads and writes the
424 // register one slot early.
425 if (VNInfo *DefVNI = LRQ.valueDefined())
426 Idx = DefVNI->def;
427
428 WorkList.push_back(std::make_pair(Idx, VNI));
429 }
430
431 // Create new live ranges with only minimal live segments per def.
432 LiveRange NewLR;
433 createSegmentsForValues(NewLR, make_range(li->vni_begin(), li->vni_end()));
434 extendSegmentsToUses(NewLR, *Indexes, WorkList, *li);
435
436 // Move the trimmed segments back.
437 li->segments.swap(NewLR.segments);
438
439 // Handle dead values.
440 bool CanSeparate = computeDeadValues(*li, dead);
441 DEBUG(dbgs() << "Shrunk: " << *li << '\n');
442 return CanSeparate;
443 }
444
computeDeadValues(LiveInterval & LI,SmallVectorImpl<MachineInstr * > * dead)445 bool LiveIntervals::computeDeadValues(LiveInterval &LI,
446 SmallVectorImpl<MachineInstr*> *dead) {
447 bool PHIRemoved = false;
448 for (auto VNI : LI.valnos) {
449 if (VNI->isUnused())
450 continue;
451 LiveRange::iterator I = LI.FindSegmentContaining(VNI->def);
452 assert(I != LI.end() && "Missing segment for VNI");
453 if (I->end != VNI->def.getDeadSlot())
454 continue;
455 if (VNI->isPHIDef()) {
456 // This is a dead PHI. Remove it.
457 VNI->markUnused();
458 LI.removeSegment(I);
459 DEBUG(dbgs() << "Dead PHI at " << VNI->def << " may separate interval\n");
460 PHIRemoved = true;
461 } else {
462 // This is a dead def. Make sure the instruction knows.
463 MachineInstr *MI = getInstructionFromIndex(VNI->def);
464 assert(MI && "No instruction defining live value");
465 MI->addRegisterDead(LI.reg, TRI);
466 if (dead && MI->allDefsAreDead()) {
467 DEBUG(dbgs() << "All defs dead: " << VNI->def << '\t' << *MI);
468 dead->push_back(MI);
469 }
470 }
471 }
472 return PHIRemoved;
473 }
474
shrinkToUses(LiveInterval::SubRange & SR,unsigned Reg)475 void LiveIntervals::shrinkToUses(LiveInterval::SubRange &SR, unsigned Reg)
476 {
477 DEBUG(dbgs() << "Shrink: " << SR << '\n');
478 assert(TargetRegisterInfo::isVirtualRegister(Reg)
479 && "Can only shrink virtual registers");
480 // Find all the values used, including PHI kills.
481 ShrinkToUsesWorkList WorkList;
482
483 // Visit all instructions reading Reg.
484 SlotIndex LastIdx;
485 for (MachineOperand &MO : MRI->reg_operands(Reg)) {
486 MachineInstr *UseMI = MO.getParent();
487 if (UseMI->isDebugValue())
488 continue;
489 // Maybe the operand is for a subregister we don't care about.
490 unsigned SubReg = MO.getSubReg();
491 if (SubReg != 0) {
492 unsigned SubRegMask = TRI->getSubRegIndexLaneMask(SubReg);
493 if ((SubRegMask & SR.LaneMask) == 0)
494 continue;
495 }
496 // We only need to visit each instruction once.
497 SlotIndex Idx = getInstructionIndex(UseMI).getRegSlot();
498 if (Idx == LastIdx)
499 continue;
500 LastIdx = Idx;
501
502 LiveQueryResult LRQ = SR.Query(Idx);
503 VNInfo *VNI = LRQ.valueIn();
504 // For Subranges it is possible that only undef values are left in that
505 // part of the subregister, so there is no real liverange at the use
506 if (!VNI)
507 continue;
508
509 // Special case: An early-clobber tied operand reads and writes the
510 // register one slot early.
511 if (VNInfo *DefVNI = LRQ.valueDefined())
512 Idx = DefVNI->def;
513
514 WorkList.push_back(std::make_pair(Idx, VNI));
515 }
516
517 // Create a new live ranges with only minimal live segments per def.
518 LiveRange NewLR;
519 createSegmentsForValues(NewLR, make_range(SR.vni_begin(), SR.vni_end()));
520 extendSegmentsToUses(NewLR, *Indexes, WorkList, SR);
521
522 // Move the trimmed ranges back.
523 SR.segments.swap(NewLR.segments);
524
525 // Remove dead PHI value numbers
526 for (auto VNI : SR.valnos) {
527 if (VNI->isUnused())
528 continue;
529 const LiveRange::Segment *Segment = SR.getSegmentContaining(VNI->def);
530 assert(Segment != nullptr && "Missing segment for VNI");
531 if (Segment->end != VNI->def.getDeadSlot())
532 continue;
533 if (VNI->isPHIDef()) {
534 // This is a dead PHI. Remove it.
535 VNI->markUnused();
536 SR.removeSegment(*Segment);
537 DEBUG(dbgs() << "Dead PHI at " << VNI->def << " may separate interval\n");
538 }
539 }
540
541 DEBUG(dbgs() << "Shrunk: " << SR << '\n');
542 }
543
extendToIndices(LiveRange & LR,ArrayRef<SlotIndex> Indices)544 void LiveIntervals::extendToIndices(LiveRange &LR,
545 ArrayRef<SlotIndex> Indices) {
546 assert(LRCalc && "LRCalc not initialized.");
547 LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
548 for (unsigned i = 0, e = Indices.size(); i != e; ++i)
549 LRCalc->extend(LR, Indices[i]);
550 }
551
pruneValue(LiveRange & LR,SlotIndex Kill,SmallVectorImpl<SlotIndex> * EndPoints)552 void LiveIntervals::pruneValue(LiveRange &LR, SlotIndex Kill,
553 SmallVectorImpl<SlotIndex> *EndPoints) {
554 LiveQueryResult LRQ = LR.Query(Kill);
555 VNInfo *VNI = LRQ.valueOutOrDead();
556 if (!VNI)
557 return;
558
559 MachineBasicBlock *KillMBB = Indexes->getMBBFromIndex(Kill);
560 SlotIndex MBBEnd = Indexes->getMBBEndIdx(KillMBB);
561
562 // If VNI isn't live out from KillMBB, the value is trivially pruned.
563 if (LRQ.endPoint() < MBBEnd) {
564 LR.removeSegment(Kill, LRQ.endPoint());
565 if (EndPoints) EndPoints->push_back(LRQ.endPoint());
566 return;
567 }
568
569 // VNI is live out of KillMBB.
570 LR.removeSegment(Kill, MBBEnd);
571 if (EndPoints) EndPoints->push_back(MBBEnd);
572
573 // Find all blocks that are reachable from KillMBB without leaving VNI's live
574 // range. It is possible that KillMBB itself is reachable, so start a DFS
575 // from each successor.
576 typedef SmallPtrSet<MachineBasicBlock*, 9> VisitedTy;
577 VisitedTy Visited;
578 for (MachineBasicBlock::succ_iterator
579 SuccI = KillMBB->succ_begin(), SuccE = KillMBB->succ_end();
580 SuccI != SuccE; ++SuccI) {
581 for (df_ext_iterator<MachineBasicBlock*, VisitedTy>
582 I = df_ext_begin(*SuccI, Visited), E = df_ext_end(*SuccI, Visited);
583 I != E;) {
584 MachineBasicBlock *MBB = *I;
585
586 // Check if VNI is live in to MBB.
587 SlotIndex MBBStart, MBBEnd;
588 std::tie(MBBStart, MBBEnd) = Indexes->getMBBRange(MBB);
589 LiveQueryResult LRQ = LR.Query(MBBStart);
590 if (LRQ.valueIn() != VNI) {
591 // This block isn't part of the VNI segment. Prune the search.
592 I.skipChildren();
593 continue;
594 }
595
596 // Prune the search if VNI is killed in MBB.
597 if (LRQ.endPoint() < MBBEnd) {
598 LR.removeSegment(MBBStart, LRQ.endPoint());
599 if (EndPoints) EndPoints->push_back(LRQ.endPoint());
600 I.skipChildren();
601 continue;
602 }
603
604 // VNI is live through MBB.
605 LR.removeSegment(MBBStart, MBBEnd);
606 if (EndPoints) EndPoints->push_back(MBBEnd);
607 ++I;
608 }
609 }
610 }
611
pruneValue(LiveInterval & LI,SlotIndex Kill,SmallVectorImpl<SlotIndex> * EndPoints)612 void LiveIntervals::pruneValue(LiveInterval &LI, SlotIndex Kill,
613 SmallVectorImpl<SlotIndex> *EndPoints) {
614 pruneValue((LiveRange&)LI, Kill, EndPoints);
615
616 for (LiveInterval::SubRange &SR : LI.subranges()) {
617 pruneValue(SR, Kill, nullptr);
618 }
619 }
620
621 //===----------------------------------------------------------------------===//
622 // Register allocator hooks.
623 //
624
addKillFlags(const VirtRegMap * VRM)625 void LiveIntervals::addKillFlags(const VirtRegMap *VRM) {
626 // Keep track of regunit ranges.
627 SmallVector<std::pair<const LiveRange*, LiveRange::const_iterator>, 8> RU;
628 // Keep track of subregister ranges.
629 SmallVector<std::pair<const LiveInterval::SubRange*,
630 LiveRange::const_iterator>, 4> SRs;
631
632 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
633 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
634 if (MRI->reg_nodbg_empty(Reg))
635 continue;
636 const LiveInterval &LI = getInterval(Reg);
637 if (LI.empty())
638 continue;
639
640 // Find the regunit intervals for the assigned register. They may overlap
641 // the virtual register live range, cancelling any kills.
642 RU.clear();
643 for (MCRegUnitIterator Units(VRM->getPhys(Reg), TRI); Units.isValid();
644 ++Units) {
645 const LiveRange &RURange = getRegUnit(*Units);
646 if (RURange.empty())
647 continue;
648 RU.push_back(std::make_pair(&RURange, RURange.find(LI.begin()->end)));
649 }
650
651 if (MRI->tracksSubRegLiveness()) {
652 SRs.clear();
653 for (const LiveInterval::SubRange &SR : LI.subranges()) {
654 SRs.push_back(std::make_pair(&SR, SR.find(LI.begin()->end)));
655 }
656 }
657
658 // Every instruction that kills Reg corresponds to a segment range end
659 // point.
660 for (LiveInterval::const_iterator RI = LI.begin(), RE = LI.end(); RI != RE;
661 ++RI) {
662 // A block index indicates an MBB edge.
663 if (RI->end.isBlock())
664 continue;
665 MachineInstr *MI = getInstructionFromIndex(RI->end);
666 if (!MI)
667 continue;
668
669 // Check if any of the regunits are live beyond the end of RI. That could
670 // happen when a physreg is defined as a copy of a virtreg:
671 //
672 // %EAX = COPY %vreg5
673 // FOO %vreg5 <--- MI, cancel kill because %EAX is live.
674 // BAR %EAX<kill>
675 //
676 // There should be no kill flag on FOO when %vreg5 is rewritten as %EAX.
677 for (auto &RUP : RU) {
678 const LiveRange &RURange = *RUP.first;
679 LiveRange::const_iterator &I = RUP.second;
680 if (I == RURange.end())
681 continue;
682 I = RURange.advanceTo(I, RI->end);
683 if (I == RURange.end() || I->start >= RI->end)
684 continue;
685 // I is overlapping RI.
686 goto CancelKill;
687 }
688
689 if (MRI->tracksSubRegLiveness()) {
690 // When reading a partial undefined value we must not add a kill flag.
691 // The regalloc might have used the undef lane for something else.
692 // Example:
693 // %vreg1 = ... ; R32: %vreg1
694 // %vreg2:high16 = ... ; R64: %vreg2
695 // = read %vreg2<kill> ; R64: %vreg2
696 // = read %vreg1 ; R32: %vreg1
697 // The <kill> flag is correct for %vreg2, but the register allocator may
698 // assign R0L to %vreg1, and R0 to %vreg2 because the low 32bits of R0
699 // are actually never written by %vreg2. After assignment the <kill>
700 // flag at the read instruction is invalid.
701 unsigned DefinedLanesMask;
702 if (!SRs.empty()) {
703 // Compute a mask of lanes that are defined.
704 DefinedLanesMask = 0;
705 for (auto &SRP : SRs) {
706 const LiveInterval::SubRange &SR = *SRP.first;
707 LiveRange::const_iterator &I = SRP.second;
708 if (I == SR.end())
709 continue;
710 I = SR.advanceTo(I, RI->end);
711 if (I == SR.end() || I->start >= RI->end)
712 continue;
713 // I is overlapping RI
714 DefinedLanesMask |= SR.LaneMask;
715 }
716 } else
717 DefinedLanesMask = ~0u;
718
719 bool IsFullWrite = false;
720 for (const MachineOperand &MO : MI->operands()) {
721 if (!MO.isReg() || MO.getReg() != Reg)
722 continue;
723 if (MO.isUse()) {
724 // Reading any undefined lanes?
725 unsigned UseMask = TRI->getSubRegIndexLaneMask(MO.getSubReg());
726 if ((UseMask & ~DefinedLanesMask) != 0)
727 goto CancelKill;
728 } else if (MO.getSubReg() == 0) {
729 // Writing to the full register?
730 assert(MO.isDef());
731 IsFullWrite = true;
732 }
733 }
734
735 // If an instruction writes to a subregister, a new segment starts in
736 // the LiveInterval. But as this is only overriding part of the register
737 // adding kill-flags is not correct here after registers have been
738 // assigned.
739 if (!IsFullWrite) {
740 // Next segment has to be adjacent in the subregister write case.
741 LiveRange::const_iterator N = std::next(RI);
742 if (N != LI.end() && N->start == RI->end)
743 goto CancelKill;
744 }
745 }
746
747 MI->addRegisterKilled(Reg, nullptr);
748 continue;
749 CancelKill:
750 MI->clearRegisterKills(Reg, nullptr);
751 }
752 }
753 }
754
755 MachineBasicBlock*
intervalIsInOneMBB(const LiveInterval & LI) const756 LiveIntervals::intervalIsInOneMBB(const LiveInterval &LI) const {
757 // A local live range must be fully contained inside the block, meaning it is
758 // defined and killed at instructions, not at block boundaries. It is not
759 // live in or or out of any block.
760 //
761 // It is technically possible to have a PHI-defined live range identical to a
762 // single block, but we are going to return false in that case.
763
764 SlotIndex Start = LI.beginIndex();
765 if (Start.isBlock())
766 return nullptr;
767
768 SlotIndex Stop = LI.endIndex();
769 if (Stop.isBlock())
770 return nullptr;
771
772 // getMBBFromIndex doesn't need to search the MBB table when both indexes
773 // belong to proper instructions.
774 MachineBasicBlock *MBB1 = Indexes->getMBBFromIndex(Start);
775 MachineBasicBlock *MBB2 = Indexes->getMBBFromIndex(Stop);
776 return MBB1 == MBB2 ? MBB1 : nullptr;
777 }
778
779 bool
hasPHIKill(const LiveInterval & LI,const VNInfo * VNI) const780 LiveIntervals::hasPHIKill(const LiveInterval &LI, const VNInfo *VNI) const {
781 for (const VNInfo *PHI : LI.valnos) {
782 if (PHI->isUnused() || !PHI->isPHIDef())
783 continue;
784 const MachineBasicBlock *PHIMBB = getMBBFromIndex(PHI->def);
785 // Conservatively return true instead of scanning huge predecessor lists.
786 if (PHIMBB->pred_size() > 100)
787 return true;
788 for (MachineBasicBlock::const_pred_iterator
789 PI = PHIMBB->pred_begin(), PE = PHIMBB->pred_end(); PI != PE; ++PI)
790 if (VNI == LI.getVNInfoBefore(Indexes->getMBBEndIdx(*PI)))
791 return true;
792 }
793 return false;
794 }
795
796 float
getSpillWeight(bool isDef,bool isUse,const MachineBlockFrequencyInfo * MBFI,const MachineInstr * MI)797 LiveIntervals::getSpillWeight(bool isDef, bool isUse,
798 const MachineBlockFrequencyInfo *MBFI,
799 const MachineInstr *MI) {
800 BlockFrequency Freq = MBFI->getBlockFreq(MI->getParent());
801 const float Scale = 1.0f / MBFI->getEntryFreq();
802 return (isDef + isUse) * (Freq.getFrequency() * Scale);
803 }
804
805 LiveRange::Segment
addSegmentToEndOfBlock(unsigned reg,MachineInstr * startInst)806 LiveIntervals::addSegmentToEndOfBlock(unsigned reg, MachineInstr* startInst) {
807 LiveInterval& Interval = createEmptyInterval(reg);
808 VNInfo* VN = Interval.getNextValue(
809 SlotIndex(getInstructionIndex(startInst).getRegSlot()),
810 getVNInfoAllocator());
811 LiveRange::Segment S(
812 SlotIndex(getInstructionIndex(startInst).getRegSlot()),
813 getMBBEndIdx(startInst->getParent()), VN);
814 Interval.addSegment(S);
815
816 return S;
817 }
818
819
820 //===----------------------------------------------------------------------===//
821 // Register mask functions
822 //===----------------------------------------------------------------------===//
823
checkRegMaskInterference(LiveInterval & LI,BitVector & UsableRegs)824 bool LiveIntervals::checkRegMaskInterference(LiveInterval &LI,
825 BitVector &UsableRegs) {
826 if (LI.empty())
827 return false;
828 LiveInterval::iterator LiveI = LI.begin(), LiveE = LI.end();
829
830 // Use a smaller arrays for local live ranges.
831 ArrayRef<SlotIndex> Slots;
832 ArrayRef<const uint32_t*> Bits;
833 if (MachineBasicBlock *MBB = intervalIsInOneMBB(LI)) {
834 Slots = getRegMaskSlotsInBlock(MBB->getNumber());
835 Bits = getRegMaskBitsInBlock(MBB->getNumber());
836 } else {
837 Slots = getRegMaskSlots();
838 Bits = getRegMaskBits();
839 }
840
841 // We are going to enumerate all the register mask slots contained in LI.
842 // Start with a binary search of RegMaskSlots to find a starting point.
843 ArrayRef<SlotIndex>::iterator SlotI =
844 std::lower_bound(Slots.begin(), Slots.end(), LiveI->start);
845 ArrayRef<SlotIndex>::iterator SlotE = Slots.end();
846
847 // No slots in range, LI begins after the last call.
848 if (SlotI == SlotE)
849 return false;
850
851 bool Found = false;
852 for (;;) {
853 assert(*SlotI >= LiveI->start);
854 // Loop over all slots overlapping this segment.
855 while (*SlotI < LiveI->end) {
856 // *SlotI overlaps LI. Collect mask bits.
857 if (!Found) {
858 // This is the first overlap. Initialize UsableRegs to all ones.
859 UsableRegs.clear();
860 UsableRegs.resize(TRI->getNumRegs(), true);
861 Found = true;
862 }
863 // Remove usable registers clobbered by this mask.
864 UsableRegs.clearBitsNotInMask(Bits[SlotI-Slots.begin()]);
865 if (++SlotI == SlotE)
866 return Found;
867 }
868 // *SlotI is beyond the current LI segment.
869 LiveI = LI.advanceTo(LiveI, *SlotI);
870 if (LiveI == LiveE)
871 return Found;
872 // Advance SlotI until it overlaps.
873 while (*SlotI < LiveI->start)
874 if (++SlotI == SlotE)
875 return Found;
876 }
877 }
878
879 //===----------------------------------------------------------------------===//
880 // IntervalUpdate class.
881 //===----------------------------------------------------------------------===//
882
883 // HMEditor is a toolkit used by handleMove to trim or extend live intervals.
884 class LiveIntervals::HMEditor {
885 private:
886 LiveIntervals& LIS;
887 const MachineRegisterInfo& MRI;
888 const TargetRegisterInfo& TRI;
889 SlotIndex OldIdx;
890 SlotIndex NewIdx;
891 SmallPtrSet<LiveRange*, 8> Updated;
892 bool UpdateFlags;
893
894 public:
HMEditor(LiveIntervals & LIS,const MachineRegisterInfo & MRI,const TargetRegisterInfo & TRI,SlotIndex OldIdx,SlotIndex NewIdx,bool UpdateFlags)895 HMEditor(LiveIntervals& LIS, const MachineRegisterInfo& MRI,
896 const TargetRegisterInfo& TRI,
897 SlotIndex OldIdx, SlotIndex NewIdx, bool UpdateFlags)
898 : LIS(LIS), MRI(MRI), TRI(TRI), OldIdx(OldIdx), NewIdx(NewIdx),
899 UpdateFlags(UpdateFlags) {}
900
901 // FIXME: UpdateFlags is a workaround that creates live intervals for all
902 // physregs, even those that aren't needed for regalloc, in order to update
903 // kill flags. This is wasteful. Eventually, LiveVariables will strip all kill
904 // flags, and postRA passes will use a live register utility instead.
getRegUnitLI(unsigned Unit)905 LiveRange *getRegUnitLI(unsigned Unit) {
906 if (UpdateFlags)
907 return &LIS.getRegUnit(Unit);
908 return LIS.getCachedRegUnit(Unit);
909 }
910
911 /// Update all live ranges touched by MI, assuming a move from OldIdx to
912 /// NewIdx.
updateAllRanges(MachineInstr * MI)913 void updateAllRanges(MachineInstr *MI) {
914 DEBUG(dbgs() << "handleMove " << OldIdx << " -> " << NewIdx << ": " << *MI);
915 bool hasRegMask = false;
916 for (MIOperands MO(MI); MO.isValid(); ++MO) {
917 if (MO->isRegMask())
918 hasRegMask = true;
919 if (!MO->isReg())
920 continue;
921 // Aggressively clear all kill flags.
922 // They are reinserted by VirtRegRewriter.
923 if (MO->isUse())
924 MO->setIsKill(false);
925
926 unsigned Reg = MO->getReg();
927 if (!Reg)
928 continue;
929 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
930 LiveInterval &LI = LIS.getInterval(Reg);
931 if (LI.hasSubRanges()) {
932 unsigned SubReg = MO->getSubReg();
933 unsigned LaneMask = TRI.getSubRegIndexLaneMask(SubReg);
934 for (LiveInterval::SubRange &S : LI.subranges()) {
935 if ((S.LaneMask & LaneMask) == 0)
936 continue;
937 updateRange(S, Reg, S.LaneMask);
938 }
939 }
940 updateRange(LI, Reg, 0);
941 continue;
942 }
943
944 // For physregs, only update the regunits that actually have a
945 // precomputed live range.
946 for (MCRegUnitIterator Units(Reg, &TRI); Units.isValid(); ++Units)
947 if (LiveRange *LR = getRegUnitLI(*Units))
948 updateRange(*LR, *Units, 0);
949 }
950 if (hasRegMask)
951 updateRegMaskSlots();
952 }
953
954 private:
955 /// Update a single live range, assuming an instruction has been moved from
956 /// OldIdx to NewIdx.
updateRange(LiveRange & LR,unsigned Reg,unsigned LaneMask)957 void updateRange(LiveRange &LR, unsigned Reg, unsigned LaneMask) {
958 if (!Updated.insert(&LR).second)
959 return;
960 DEBUG({
961 dbgs() << " ";
962 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
963 dbgs() << PrintReg(Reg);
964 if (LaneMask != 0)
965 dbgs() << format(" L%04X", LaneMask);
966 } else {
967 dbgs() << PrintRegUnit(Reg, &TRI);
968 }
969 dbgs() << ":\t" << LR << '\n';
970 });
971 if (SlotIndex::isEarlierInstr(OldIdx, NewIdx))
972 handleMoveDown(LR);
973 else
974 handleMoveUp(LR, Reg, LaneMask);
975 DEBUG(dbgs() << " -->\t" << LR << '\n');
976 LR.verify();
977 }
978
979 /// Update LR to reflect an instruction has been moved downwards from OldIdx
980 /// to NewIdx.
981 ///
982 /// 1. Live def at OldIdx:
983 /// Move def to NewIdx, assert endpoint after NewIdx.
984 ///
985 /// 2. Live def at OldIdx, killed at NewIdx:
986 /// Change to dead def at NewIdx.
987 /// (Happens when bundling def+kill together).
988 ///
989 /// 3. Dead def at OldIdx:
990 /// Move def to NewIdx, possibly across another live value.
991 ///
992 /// 4. Def at OldIdx AND at NewIdx:
993 /// Remove segment [OldIdx;NewIdx) and value defined at OldIdx.
994 /// (Happens when bundling multiple defs together).
995 ///
996 /// 5. Value read at OldIdx, killed before NewIdx:
997 /// Extend kill to NewIdx.
998 ///
handleMoveDown(LiveRange & LR)999 void handleMoveDown(LiveRange &LR) {
1000 // First look for a kill at OldIdx.
1001 LiveRange::iterator I = LR.find(OldIdx.getBaseIndex());
1002 LiveRange::iterator E = LR.end();
1003 // Is LR even live at OldIdx?
1004 if (I == E || SlotIndex::isEarlierInstr(OldIdx, I->start))
1005 return;
1006
1007 // Handle a live-in value.
1008 if (!SlotIndex::isSameInstr(I->start, OldIdx)) {
1009 bool isKill = SlotIndex::isSameInstr(OldIdx, I->end);
1010 // If the live-in value already extends to NewIdx, there is nothing to do.
1011 if (!SlotIndex::isEarlierInstr(I->end, NewIdx))
1012 return;
1013 // Aggressively remove all kill flags from the old kill point.
1014 // Kill flags shouldn't be used while live intervals exist, they will be
1015 // reinserted by VirtRegRewriter.
1016 if (MachineInstr *KillMI = LIS.getInstructionFromIndex(I->end))
1017 for (MIBundleOperands MO(KillMI); MO.isValid(); ++MO)
1018 if (MO->isReg() && MO->isUse())
1019 MO->setIsKill(false);
1020 // Adjust I->end to reach NewIdx. This may temporarily make LR invalid by
1021 // overlapping ranges. Case 5 above.
1022 I->end = NewIdx.getRegSlot(I->end.isEarlyClobber());
1023 // If this was a kill, there may also be a def. Otherwise we're done.
1024 if (!isKill)
1025 return;
1026 ++I;
1027 }
1028
1029 // Check for a def at OldIdx.
1030 if (I == E || !SlotIndex::isSameInstr(OldIdx, I->start))
1031 return;
1032 // We have a def at OldIdx.
1033 VNInfo *DefVNI = I->valno;
1034 assert(DefVNI->def == I->start && "Inconsistent def");
1035 DefVNI->def = NewIdx.getRegSlot(I->start.isEarlyClobber());
1036 // If the defined value extends beyond NewIdx, just move the def down.
1037 // This is case 1 above.
1038 if (SlotIndex::isEarlierInstr(NewIdx, I->end)) {
1039 I->start = DefVNI->def;
1040 return;
1041 }
1042 // The remaining possibilities are now:
1043 // 2. Live def at OldIdx, killed at NewIdx: isSameInstr(I->end, NewIdx).
1044 // 3. Dead def at OldIdx: I->end = OldIdx.getDeadSlot().
1045 // In either case, it is possible that there is an existing def at NewIdx.
1046 assert((I->end == OldIdx.getDeadSlot() ||
1047 SlotIndex::isSameInstr(I->end, NewIdx)) &&
1048 "Cannot move def below kill");
1049 LiveRange::iterator NewI = LR.advanceTo(I, NewIdx.getRegSlot());
1050 if (NewI != E && SlotIndex::isSameInstr(NewI->start, NewIdx)) {
1051 // There is an existing def at NewIdx, case 4 above. The def at OldIdx is
1052 // coalesced into that value.
1053 assert(NewI->valno != DefVNI && "Multiple defs of value?");
1054 LR.removeValNo(DefVNI);
1055 return;
1056 }
1057 // There was no existing def at NewIdx. Turn *I into a dead def at NewIdx.
1058 // If the def at OldIdx was dead, we allow it to be moved across other LR
1059 // values. The new range should be placed immediately before NewI, move any
1060 // intermediate ranges up.
1061 assert(NewI != I && "Inconsistent iterators");
1062 std::copy(std::next(I), NewI, I);
1063 *std::prev(NewI)
1064 = LiveRange::Segment(DefVNI->def, NewIdx.getDeadSlot(), DefVNI);
1065 }
1066
1067 /// Update LR to reflect an instruction has been moved upwards from OldIdx
1068 /// to NewIdx.
1069 ///
1070 /// 1. Live def at OldIdx:
1071 /// Hoist def to NewIdx.
1072 ///
1073 /// 2. Dead def at OldIdx:
1074 /// Hoist def+end to NewIdx, possibly move across other values.
1075 ///
1076 /// 3. Dead def at OldIdx AND existing def at NewIdx:
1077 /// Remove value defined at OldIdx, coalescing it with existing value.
1078 ///
1079 /// 4. Live def at OldIdx AND existing def at NewIdx:
1080 /// Remove value defined at NewIdx, hoist OldIdx def to NewIdx.
1081 /// (Happens when bundling multiple defs together).
1082 ///
1083 /// 5. Value killed at OldIdx:
1084 /// Hoist kill to NewIdx, then scan for last kill between NewIdx and
1085 /// OldIdx.
1086 ///
handleMoveUp(LiveRange & LR,unsigned Reg,unsigned LaneMask)1087 void handleMoveUp(LiveRange &LR, unsigned Reg, unsigned LaneMask) {
1088 // First look for a kill at OldIdx.
1089 LiveRange::iterator I = LR.find(OldIdx.getBaseIndex());
1090 LiveRange::iterator E = LR.end();
1091 // Is LR even live at OldIdx?
1092 if (I == E || SlotIndex::isEarlierInstr(OldIdx, I->start))
1093 return;
1094
1095 // Handle a live-in value.
1096 if (!SlotIndex::isSameInstr(I->start, OldIdx)) {
1097 // If the live-in value isn't killed here, there is nothing to do.
1098 if (!SlotIndex::isSameInstr(OldIdx, I->end))
1099 return;
1100 // Adjust I->end to end at NewIdx. If we are hoisting a kill above
1101 // another use, we need to search for that use. Case 5 above.
1102 I->end = NewIdx.getRegSlot(I->end.isEarlyClobber());
1103 ++I;
1104 // If OldIdx also defines a value, there couldn't have been another use.
1105 if (I == E || !SlotIndex::isSameInstr(I->start, OldIdx)) {
1106 // No def, search for the new kill.
1107 // This can never be an early clobber kill since there is no def.
1108 std::prev(I)->end = findLastUseBefore(Reg, LaneMask).getRegSlot();
1109 return;
1110 }
1111 }
1112
1113 // Now deal with the def at OldIdx.
1114 assert(I != E && SlotIndex::isSameInstr(I->start, OldIdx) && "No def?");
1115 VNInfo *DefVNI = I->valno;
1116 assert(DefVNI->def == I->start && "Inconsistent def");
1117 DefVNI->def = NewIdx.getRegSlot(I->start.isEarlyClobber());
1118
1119 // Check for an existing def at NewIdx.
1120 LiveRange::iterator NewI = LR.find(NewIdx.getRegSlot());
1121 if (SlotIndex::isSameInstr(NewI->start, NewIdx)) {
1122 assert(NewI->valno != DefVNI && "Same value defined more than once?");
1123 // There is an existing def at NewIdx.
1124 if (I->end.isDead()) {
1125 // Case 3: Remove the dead def at OldIdx.
1126 LR.removeValNo(DefVNI);
1127 return;
1128 }
1129 // Case 4: Replace def at NewIdx with live def at OldIdx.
1130 I->start = DefVNI->def;
1131 LR.removeValNo(NewI->valno);
1132 return;
1133 }
1134
1135 // There is no existing def at NewIdx. Hoist DefVNI.
1136 if (!I->end.isDead()) {
1137 // Leave the end point of a live def.
1138 I->start = DefVNI->def;
1139 return;
1140 }
1141
1142 // DefVNI is a dead def. It may have been moved across other values in LR,
1143 // so move I up to NewI. Slide [NewI;I) down one position.
1144 std::copy_backward(NewI, I, std::next(I));
1145 *NewI = LiveRange::Segment(DefVNI->def, NewIdx.getDeadSlot(), DefVNI);
1146 }
1147
updateRegMaskSlots()1148 void updateRegMaskSlots() {
1149 SmallVectorImpl<SlotIndex>::iterator RI =
1150 std::lower_bound(LIS.RegMaskSlots.begin(), LIS.RegMaskSlots.end(),
1151 OldIdx);
1152 assert(RI != LIS.RegMaskSlots.end() && *RI == OldIdx.getRegSlot() &&
1153 "No RegMask at OldIdx.");
1154 *RI = NewIdx.getRegSlot();
1155 assert((RI == LIS.RegMaskSlots.begin() ||
1156 SlotIndex::isEarlierInstr(*std::prev(RI), *RI)) &&
1157 "Cannot move regmask instruction above another call");
1158 assert((std::next(RI) == LIS.RegMaskSlots.end() ||
1159 SlotIndex::isEarlierInstr(*RI, *std::next(RI))) &&
1160 "Cannot move regmask instruction below another call");
1161 }
1162
1163 // Return the last use of reg between NewIdx and OldIdx.
findLastUseBefore(unsigned Reg,unsigned LaneMask)1164 SlotIndex findLastUseBefore(unsigned Reg, unsigned LaneMask) {
1165
1166 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
1167 SlotIndex LastUse = NewIdx;
1168 for (MachineOperand &MO : MRI.use_nodbg_operands(Reg)) {
1169 unsigned SubReg = MO.getSubReg();
1170 if (SubReg != 0 && LaneMask != 0
1171 && (TRI.getSubRegIndexLaneMask(SubReg) & LaneMask) == 0)
1172 continue;
1173
1174 const MachineInstr *MI = MO.getParent();
1175 SlotIndex InstSlot = LIS.getSlotIndexes()->getInstructionIndex(MI);
1176 if (InstSlot > LastUse && InstSlot < OldIdx)
1177 LastUse = InstSlot;
1178 }
1179 return LastUse;
1180 }
1181
1182 // This is a regunit interval, so scanning the use list could be very
1183 // expensive. Scan upwards from OldIdx instead.
1184 assert(NewIdx < OldIdx && "Expected upwards move");
1185 SlotIndexes *Indexes = LIS.getSlotIndexes();
1186 MachineBasicBlock *MBB = Indexes->getMBBFromIndex(NewIdx);
1187
1188 // OldIdx may not correspond to an instruction any longer, so set MII to
1189 // point to the next instruction after OldIdx, or MBB->end().
1190 MachineBasicBlock::iterator MII = MBB->end();
1191 if (MachineInstr *MI = Indexes->getInstructionFromIndex(
1192 Indexes->getNextNonNullIndex(OldIdx)))
1193 if (MI->getParent() == MBB)
1194 MII = MI;
1195
1196 MachineBasicBlock::iterator Begin = MBB->begin();
1197 while (MII != Begin) {
1198 if ((--MII)->isDebugValue())
1199 continue;
1200 SlotIndex Idx = Indexes->getInstructionIndex(MII);
1201
1202 // Stop searching when NewIdx is reached.
1203 if (!SlotIndex::isEarlierInstr(NewIdx, Idx))
1204 return NewIdx;
1205
1206 // Check if MII uses Reg.
1207 for (MIBundleOperands MO(MII); MO.isValid(); ++MO)
1208 if (MO->isReg() &&
1209 TargetRegisterInfo::isPhysicalRegister(MO->getReg()) &&
1210 TRI.hasRegUnit(MO->getReg(), Reg))
1211 return Idx;
1212 }
1213 // Didn't reach NewIdx. It must be the first instruction in the block.
1214 return NewIdx;
1215 }
1216 };
1217
handleMove(MachineInstr * MI,bool UpdateFlags)1218 void LiveIntervals::handleMove(MachineInstr* MI, bool UpdateFlags) {
1219 assert(!MI->isBundled() && "Can't handle bundled instructions yet.");
1220 SlotIndex OldIndex = Indexes->getInstructionIndex(MI);
1221 Indexes->removeMachineInstrFromMaps(MI);
1222 SlotIndex NewIndex = Indexes->insertMachineInstrInMaps(MI);
1223 assert(getMBBStartIdx(MI->getParent()) <= OldIndex &&
1224 OldIndex < getMBBEndIdx(MI->getParent()) &&
1225 "Cannot handle moves across basic block boundaries.");
1226
1227 HMEditor HME(*this, *MRI, *TRI, OldIndex, NewIndex, UpdateFlags);
1228 HME.updateAllRanges(MI);
1229 }
1230
handleMoveIntoBundle(MachineInstr * MI,MachineInstr * BundleStart,bool UpdateFlags)1231 void LiveIntervals::handleMoveIntoBundle(MachineInstr* MI,
1232 MachineInstr* BundleStart,
1233 bool UpdateFlags) {
1234 SlotIndex OldIndex = Indexes->getInstructionIndex(MI);
1235 SlotIndex NewIndex = Indexes->getInstructionIndex(BundleStart);
1236 HMEditor HME(*this, *MRI, *TRI, OldIndex, NewIndex, UpdateFlags);
1237 HME.updateAllRanges(MI);
1238 }
1239
repairOldRegInRange(const MachineBasicBlock::iterator Begin,const MachineBasicBlock::iterator End,const SlotIndex endIdx,LiveRange & LR,const unsigned Reg,const unsigned LaneMask)1240 void LiveIntervals::repairOldRegInRange(const MachineBasicBlock::iterator Begin,
1241 const MachineBasicBlock::iterator End,
1242 const SlotIndex endIdx,
1243 LiveRange &LR, const unsigned Reg,
1244 const unsigned LaneMask) {
1245 LiveInterval::iterator LII = LR.find(endIdx);
1246 SlotIndex lastUseIdx;
1247 if (LII != LR.end() && LII->start < endIdx)
1248 lastUseIdx = LII->end;
1249 else
1250 --LII;
1251
1252 for (MachineBasicBlock::iterator I = End; I != Begin;) {
1253 --I;
1254 MachineInstr *MI = I;
1255 if (MI->isDebugValue())
1256 continue;
1257
1258 SlotIndex instrIdx = getInstructionIndex(MI);
1259 bool isStartValid = getInstructionFromIndex(LII->start);
1260 bool isEndValid = getInstructionFromIndex(LII->end);
1261
1262 // FIXME: This doesn't currently handle early-clobber or multiple removed
1263 // defs inside of the region to repair.
1264 for (MachineInstr::mop_iterator OI = MI->operands_begin(),
1265 OE = MI->operands_end(); OI != OE; ++OI) {
1266 const MachineOperand &MO = *OI;
1267 if (!MO.isReg() || MO.getReg() != Reg)
1268 continue;
1269
1270 unsigned SubReg = MO.getSubReg();
1271 unsigned Mask = TRI->getSubRegIndexLaneMask(SubReg);
1272 if ((Mask & LaneMask) == 0)
1273 continue;
1274
1275 if (MO.isDef()) {
1276 if (!isStartValid) {
1277 if (LII->end.isDead()) {
1278 SlotIndex prevStart;
1279 if (LII != LR.begin())
1280 prevStart = std::prev(LII)->start;
1281
1282 // FIXME: This could be more efficient if there was a
1283 // removeSegment method that returned an iterator.
1284 LR.removeSegment(*LII, true);
1285 if (prevStart.isValid())
1286 LII = LR.find(prevStart);
1287 else
1288 LII = LR.begin();
1289 } else {
1290 LII->start = instrIdx.getRegSlot();
1291 LII->valno->def = instrIdx.getRegSlot();
1292 if (MO.getSubReg() && !MO.isUndef())
1293 lastUseIdx = instrIdx.getRegSlot();
1294 else
1295 lastUseIdx = SlotIndex();
1296 continue;
1297 }
1298 }
1299
1300 if (!lastUseIdx.isValid()) {
1301 VNInfo *VNI = LR.getNextValue(instrIdx.getRegSlot(), VNInfoAllocator);
1302 LiveRange::Segment S(instrIdx.getRegSlot(),
1303 instrIdx.getDeadSlot(), VNI);
1304 LII = LR.addSegment(S);
1305 } else if (LII->start != instrIdx.getRegSlot()) {
1306 VNInfo *VNI = LR.getNextValue(instrIdx.getRegSlot(), VNInfoAllocator);
1307 LiveRange::Segment S(instrIdx.getRegSlot(), lastUseIdx, VNI);
1308 LII = LR.addSegment(S);
1309 }
1310
1311 if (MO.getSubReg() && !MO.isUndef())
1312 lastUseIdx = instrIdx.getRegSlot();
1313 else
1314 lastUseIdx = SlotIndex();
1315 } else if (MO.isUse()) {
1316 // FIXME: This should probably be handled outside of this branch,
1317 // either as part of the def case (for defs inside of the region) or
1318 // after the loop over the region.
1319 if (!isEndValid && !LII->end.isBlock())
1320 LII->end = instrIdx.getRegSlot();
1321 if (!lastUseIdx.isValid())
1322 lastUseIdx = instrIdx.getRegSlot();
1323 }
1324 }
1325 }
1326 }
1327
1328 void
repairIntervalsInRange(MachineBasicBlock * MBB,MachineBasicBlock::iterator Begin,MachineBasicBlock::iterator End,ArrayRef<unsigned> OrigRegs)1329 LiveIntervals::repairIntervalsInRange(MachineBasicBlock *MBB,
1330 MachineBasicBlock::iterator Begin,
1331 MachineBasicBlock::iterator End,
1332 ArrayRef<unsigned> OrigRegs) {
1333 // Find anchor points, which are at the beginning/end of blocks or at
1334 // instructions that already have indexes.
1335 while (Begin != MBB->begin() && !Indexes->hasIndex(Begin))
1336 --Begin;
1337 while (End != MBB->end() && !Indexes->hasIndex(End))
1338 ++End;
1339
1340 SlotIndex endIdx;
1341 if (End == MBB->end())
1342 endIdx = getMBBEndIdx(MBB).getPrevSlot();
1343 else
1344 endIdx = getInstructionIndex(End);
1345
1346 Indexes->repairIndexesInRange(MBB, Begin, End);
1347
1348 for (MachineBasicBlock::iterator I = End; I != Begin;) {
1349 --I;
1350 MachineInstr *MI = I;
1351 if (MI->isDebugValue())
1352 continue;
1353 for (MachineInstr::const_mop_iterator MOI = MI->operands_begin(),
1354 MOE = MI->operands_end(); MOI != MOE; ++MOI) {
1355 if (MOI->isReg() &&
1356 TargetRegisterInfo::isVirtualRegister(MOI->getReg()) &&
1357 !hasInterval(MOI->getReg())) {
1358 createAndComputeVirtRegInterval(MOI->getReg());
1359 }
1360 }
1361 }
1362
1363 for (unsigned i = 0, e = OrigRegs.size(); i != e; ++i) {
1364 unsigned Reg = OrigRegs[i];
1365 if (!TargetRegisterInfo::isVirtualRegister(Reg))
1366 continue;
1367
1368 LiveInterval &LI = getInterval(Reg);
1369 // FIXME: Should we support undefs that gain defs?
1370 if (!LI.hasAtLeastOneValue())
1371 continue;
1372
1373 for (LiveInterval::SubRange &S : LI.subranges()) {
1374 repairOldRegInRange(Begin, End, endIdx, S, Reg, S.LaneMask);
1375 }
1376 repairOldRegInRange(Begin, End, endIdx, LI, Reg);
1377 }
1378 }
1379