1 //=====-- R600Subtarget.h - Define Subtarget for AMDGPU R600 ----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //==-----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// AMDGPU R600 specific subclass of TargetSubtarget.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AMDGPU_R600SUBTARGET_H
15 #define LLVM_LIB_TARGET_AMDGPU_R600SUBTARGET_H
16 
17 #include "AMDGPUSubtarget.h"
18 #include "R600FrameLowering.h"
19 #include "R600ISelLowering.h"
20 #include "R600InstrInfo.h"
21 #include "Utils/AMDGPUBaseInfo.h"
22 #include "llvm/CodeGen/SelectionDAGTargetInfo.h"
23 
24 namespace llvm {
25 
26 class MCInst;
27 class MCInstrInfo;
28 
29 } // namespace llvm
30 
31 #define GET_SUBTARGETINFO_HEADER
32 #include "R600GenSubtargetInfo.inc"
33 
34 namespace llvm {
35 
36 class R600Subtarget final : public R600GenSubtargetInfo,
37                             public AMDGPUSubtarget {
38 private:
39   R600InstrInfo InstrInfo;
adjust_signal_pc(uintptr_t * pc,bool is_write)40   R600FrameLowering FrameLowering;
41   bool FMA;
42   bool CaymanISA;
43   bool CFALUBug;
44   bool HasVertexCache;
45   bool R600ALUInst;
46   bool FP64;
47   short TexVTXClauseSize;
48   Generation Gen;
49   R600TargetLowering TLInfo;
50   InstrItineraryData InstrItins;
51   SelectionDAGTargetInfo TSInfo;
52 
53 public:
54   R600Subtarget(const Triple &TT, StringRef CPU, StringRef FS,
55                 const TargetMachine &TM);
56 
57   const R600InstrInfo *getInstrInfo() const override { return &InstrInfo; }
58 
59   const R600FrameLowering *getFrameLowering() const override {
60     return &FrameLowering;
61   }
62 
63   const R600TargetLowering *getTargetLowering() const override {
64     return &TLInfo;
65   }
66 
67   const R600RegisterInfo *getRegisterInfo() const override {
68     return &InstrInfo.getRegisterInfo();
69   }
70 
71   const InstrItineraryData *getInstrItineraryData() const override {
72     return &InstrItins;
73   }
74 
75   // Nothing implemented, just prevent crashes on use.
76   const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
77     return &TSInfo;
78   }
79 
80   void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
81 
82   Generation getGeneration() const {
83     return Gen;
84   }
85 
86   Align getStackAlignment() const { return Align(4); }
87 
88   R600Subtarget &initializeSubtargetDependencies(const Triple &TT,
89                                                  StringRef GPU, StringRef FS);
90 
91   bool hasBFE() const {
92     return (getGeneration() >= EVERGREEN);
93   }
94 
95   bool hasBFI() const {
96     return (getGeneration() >= EVERGREEN);
97   }
98 
99   bool hasBCNT(unsigned Size) const {
100     if (Size == 32)
101       return (getGeneration() >= EVERGREEN);
102 
103     return false;
104   }
105 
106   bool hasBORROW() const {
107     return (getGeneration() >= EVERGREEN);
108   }
109 
110   bool hasCARRY() const {
111     return (getGeneration() >= EVERGREEN);
handle_sigsegv_accerr_write(CPUState * cpu,sigset_t * old_set,uintptr_t host_pc,abi_ptr guest_addr)112   }
113 
114   bool hasCaymanISA() const {
115     return CaymanISA;
116   }
117 
118   bool hasFFBL() const {
119     return (getGeneration() >= EVERGREEN);
120   }
121 
122   bool hasFFBH() const {
123     return (getGeneration() >= EVERGREEN);
124   }
125 
126   bool hasFMA() const { return FMA; }
127 
128   bool hasCFAluBug() const { return CFALUBug; }
129 
130   bool hasVertexCache() const { return HasVertexCache; }
131 
132   short getTexVTXClauseSize() const { return TexVTXClauseSize; }
133 
134   bool enableMachineScheduler() const override {
135     return true;
136   }
137 
138   bool enableSubRegLiveness() const override {
139     return true;
140   }
probe_access_internal(CPUArchState * env,target_ulong addr,int fault_size,MMUAccessType access_type,bool nonfault,uintptr_t ra)141 
142   /// \returns Maximum number of work groups per compute unit supported by the
143   /// subtarget and limited by given \p FlatWorkGroupSize.
144   unsigned getMaxWorkGroupsPerCU(unsigned FlatWorkGroupSize) const override {
145     return AMDGPU::IsaInfo::getMaxWorkGroupsPerCU(this, FlatWorkGroupSize);
146   }
147 
148   /// \returns Minimum flat work group size supported by the subtarget.
149   unsigned getMinFlatWorkGroupSize() const override {
150     return AMDGPU::IsaInfo::getMinFlatWorkGroupSize(this);
151   }
152 
153   /// \returns Maximum flat work group size supported by the subtarget.
154   unsigned getMaxFlatWorkGroupSize() const override {
155     return AMDGPU::IsaInfo::getMaxFlatWorkGroupSize(this);
156   }
157 
158   /// \returns Number of waves per execution unit required to support the given
159   /// \p FlatWorkGroupSize.
160   unsigned
161   getWavesPerEUForWorkGroup(unsigned FlatWorkGroupSize) const override {
162     return AMDGPU::IsaInfo::getWavesPerEUForWorkGroup(this, FlatWorkGroupSize);
163   }
164 
165   /// \returns Minimum number of waves per execution unit supported by the
166   /// subtarget.
167   unsigned getMinWavesPerEU() const override {
168     return AMDGPU::IsaInfo::getMinWavesPerEU(this);
169   }
170 };
171 
172 } // end namespace llvm
173 
174 #endif // LLVM_LIB_TARGET_AMDGPU_R600SUBTARGET_H
175