1 //===-- RISCVSubtarget.h - Define Subtarget for the RISCV -------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares the RISCV specific subclass of TargetSubtargetInfo.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_RISCV_RISCVSUBTARGET_H
14 #define LLVM_LIB_TARGET_RISCV_RISCVSUBTARGET_H
15 
16 #include "RISCVFrameLowering.h"
17 #include "RISCVISelLowering.h"
18 #include "RISCVInstrInfo.h"
19 #include "RISCVSelectionDAGInfo.h"
20 #include "Utils/RISCVBaseInfo.h"
21 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
22 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
23 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
24 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
25 #include "llvm/CodeGen/SelectionDAGTargetInfo.h"
26 #include "llvm/CodeGen/TargetSubtargetInfo.h"
27 #include "llvm/IR/DataLayout.h"
28 #include "llvm/Target/TargetMachine.h"
29 
30 #define GET_SUBTARGETINFO_HEADER
31 #include "RISCVGenSubtargetInfo.inc"
32 
33 namespace llvm {
34 class StringRef;
35 
36 class RISCVSubtarget : public RISCVGenSubtargetInfo {
37   virtual void anchor();
38   bool HasStdExtM = false;
39   bool HasStdExtA = false;
40   bool HasStdExtF = false;
41   bool HasStdExtD = false;
42   bool HasStdExtC = false;
43   bool HasStdExtB = false;
44   bool HasStdExtZbb = false;
45   bool HasStdExtZbc = false;
46   bool HasStdExtZbe = false;
47   bool HasStdExtZbf = false;
48   bool HasStdExtZbm = false;
49   bool HasStdExtZbp = false;
50   bool HasStdExtZbr = false;
51   bool HasStdExtZbs = false;
52   bool HasStdExtZbt = false;
53   bool HasStdExtZbproposedc = false;
54   bool HasStdExtV = false;
55   bool HasRV64 = false;
56   bool IsRV32E = false;
57   bool HasCheri = false;
58   bool IsCapMode = false;
59   bool EnableLinkerRelax = false;
60   bool EnableRVCHintInstrs = true;
61   bool EnableSaveRestore = false;
62   unsigned XLen = 32;
63   MVT XLenVT = MVT::i32;
64   RISCVABI::ABI TargetABI = RISCVABI::ABI_Unknown;
65   BitVector UserReservedRegister;
66   RISCVFrameLowering FrameLowering;
67   RISCVInstrInfo InstrInfo;
68   RISCVRegisterInfo RegInfo;
69   RISCVTargetLowering TLInfo;
70   RISCVSelectionDAGInfo TSInfo;
71 
72   /// Initializes using the passed in CPU and feature strings so that we can
73   /// use initializer lists for subtarget initialization.
74   RISCVSubtarget &initializeSubtargetDependencies(const Triple &TT,
75                                                   StringRef CPU, StringRef FS,
76                                                   StringRef ABIName);
77 
78 public:
79   // Initializes the data members to match that of the specified triple.
80   RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
81                  StringRef ABIName, const TargetMachine &TM);
82 
83   // Parses features string setting specified subtarget options. The
84   // definition of this function is auto-generated by tblgen.
85   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
86 
getFrameLowering()87   const RISCVFrameLowering *getFrameLowering() const override {
88     return &FrameLowering;
89   }
getInstrInfo()90   const RISCVInstrInfo *getInstrInfo() const override { return &InstrInfo; }
getRegisterInfo()91   const RISCVRegisterInfo *getRegisterInfo() const override {
92     return &RegInfo;
93   }
getTargetLowering()94   const RISCVTargetLowering *getTargetLowering() const override {
95     return &TLInfo;
96   }
getSelectionDAGInfo()97   const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
98     return &TSInfo;
99   }
enableMachineScheduler()100   bool enableMachineScheduler() const override { return true; }
hasStdExtM()101   bool hasStdExtM() const { return HasStdExtM; }
hasStdExtA()102   bool hasStdExtA() const { return HasStdExtA; }
hasStdExtF()103   bool hasStdExtF() const { return HasStdExtF; }
hasStdExtD()104   bool hasStdExtD() const { return HasStdExtD; }
hasStdExtC()105   bool hasStdExtC() const { return HasStdExtC; }
hasStdExtB()106   bool hasStdExtB() const { return HasStdExtB; }
hasStdExtZbb()107   bool hasStdExtZbb() const { return HasStdExtZbb; }
hasStdExtZbc()108   bool hasStdExtZbc() const { return HasStdExtZbc; }
hasStdExtZbe()109   bool hasStdExtZbe() const { return HasStdExtZbe; }
hasStdExtZbf()110   bool hasStdExtZbf() const { return HasStdExtZbf; }
hasStdExtZbm()111   bool hasStdExtZbm() const { return HasStdExtZbm; }
hasStdExtZbp()112   bool hasStdExtZbp() const { return HasStdExtZbp; }
hasStdExtZbr()113   bool hasStdExtZbr() const { return HasStdExtZbr; }
hasStdExtZbs()114   bool hasStdExtZbs() const { return HasStdExtZbs; }
hasStdExtZbt()115   bool hasStdExtZbt() const { return HasStdExtZbt; }
hasStdExtZbproposedc()116   bool hasStdExtZbproposedc() const { return HasStdExtZbproposedc; }
hasStdExtV()117   bool hasStdExtV() const { return HasStdExtV; }
is64Bit()118   bool is64Bit() const { return HasRV64; }
isRV32E()119   bool isRV32E() const { return IsRV32E; }
hasCheri()120   bool hasCheri() const { return HasCheri; }
isCapMode()121   bool isCapMode() const { return IsCapMode; }
enableLinkerRelax()122   bool enableLinkerRelax() const { return EnableLinkerRelax; }
enableRVCHintInstrs()123   bool enableRVCHintInstrs() const { return EnableRVCHintInstrs; }
enableSaveRestore()124   bool enableSaveRestore() const { return EnableSaveRestore; }
getXLenVT()125   MVT getXLenVT() const { return XLenVT; }
getXLen()126   unsigned getXLen() const { return XLen; }
getTargetABI()127   RISCVABI::ABI getTargetABI() const { return TargetABI; }
isRegisterReservedByUser(Register i)128   bool isRegisterReservedByUser(Register i) const {
129     assert(i < RISCV::NUM_TARGET_REGS && "Register out of range");
130     return UserReservedRegister[i];
131   }
typeForCapabilities()132   MVT typeForCapabilities() const {
133     assert(HasCheri && "Cannot get capability type for non-CHERI");
134     return is64Bit() ? MVT::iFATPTR128 : MVT::iFATPTR64;
135   }
136 
137 protected:
138   // GlobalISel related APIs.
139   std::unique_ptr<CallLowering> CallLoweringInfo;
140   std::unique_ptr<InstructionSelector> InstSelector;
141   std::unique_ptr<LegalizerInfo> Legalizer;
142   std::unique_ptr<RegisterBankInfo> RegBankInfo;
143 
144 public:
145   const CallLowering *getCallLowering() const override;
146   InstructionSelector *getInstructionSelector() const override;
147   const LegalizerInfo *getLegalizerInfo() const override;
148   const RegisterBankInfo *getRegBankInfo() const override;
149 };
150 } // End llvm namespace
151 
152 #endif
153