1 /* $NetBSD: cpu.h,v 1.124 2023/07/26 06:36:20 skrll Exp $ */
2
3 /*
4 * Copyright (C) 1999 Wolfgang Solfrank.
5 * Copyright (C) 1999 TooLs GmbH.
6 * Copyright (C) 1995-1997 Wolfgang Solfrank.
7 * Copyright (C) 1995-1997 TooLs GmbH.
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by TooLs GmbH.
21 * 4. The name of TooLs GmbH may not be used to endorse or promote products
22 * derived from this software without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
27 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
28 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
29 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
30 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
32 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
33 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 */
35
36 #ifndef _POWERPC_CPU_H_
37 #define _POWERPC_CPU_H_
38
39 struct cache_info {
40 int dcache_size;
41 int dcache_line_size;
42 int icache_size;
43 int icache_line_size;
44 };
45
46 #if defined(_KERNEL) || defined(_KMEMUSER)
47 #if defined(_KERNEL_OPT)
48 #include "opt_gprof.h"
49 #include "opt_modular.h"
50 #include "opt_multiprocessor.h"
51 #include "opt_ppcarch.h"
52 #include "opt_ppcopts.h"
53 #endif
54
55 #ifdef _KERNEL
56 #include <sys/intr.h>
57 #include <sys/device_if.h>
58 #include <sys/evcnt.h>
59 #include <sys/param.h>
60 #include <sys/kernel.h>
61 #endif
62
63 #include <sys/cpu_data.h>
64
65 #ifdef _KERNEL
66 #define CI_SAVETEMP (0*CPUSAVE_LEN)
67 #define CI_SAVEDDB (1*CPUSAVE_LEN)
68 #define CI_SAVEIPKDB (2*CPUSAVE_LEN) /* obsolete */
69 #define CI_SAVEMMU (3*CPUSAVE_LEN)
70 #define CI_SAVEMAX (4*CPUSAVE_LEN)
71 #define CPUSAVE_LEN 8
72 #if defined(PPC_BOOKE) && !defined(MODULAR) && !defined(_MODULE)
73 #define CPUSAVE_SIZE 128
74 #else
75 #define CPUSAVE_SIZE (CI_SAVEMAX*CPUSAVE_LEN)
76 CTASSERT(CPUSAVE_SIZE >= 128);
77 #endif
78 #define CPUSAVE_R28 0 /* where r28 gets saved */
79 #define CPUSAVE_R29 1 /* where r29 gets saved */
80 #define CPUSAVE_R30 2 /* where r30 gets saved */
81 #define CPUSAVE_R31 3 /* where r31 gets saved */
82 #define CPUSAVE_DEAR 4 /* where IBM4XX SPR_DEAR gets saved */
83 #define CPUSAVE_DAR 4 /* where OEA SPR_DAR gets saved */
84 #define CPUSAVE_ESR 5 /* where IBM4XX SPR_ESR gets saved */
85 #define CPUSAVE_DSISR 5 /* where OEA SPR_DSISR gets saved */
86 #define CPUSAVE_SRR0 6 /* where SRR0 gets saved */
87 #define CPUSAVE_SRR1 7 /* where SRR1 gets saved */
88 #endif /* _KERNEL */
89
90 struct cpu_info {
91 struct cpu_data ci_data; /* MI per-cpu data */
92 #ifdef _KERNEL
93 device_t ci_dev; /* device of corresponding cpu */
94 struct cpu_softc *ci_softc; /* private cpu info */
95 struct lwp *ci_curlwp; /* current owner of the processor */
96 struct lwp *ci_onproc; /* current user LWP / kthread */
97 struct pcb *ci_curpcb;
98 struct pmap *ci_curpm;
99 #if defined(PPC_OEA) || defined(PPC_OEA601) || defined(PPC_OEA64) || \
100 defined(PPC_OEA64_BRIDGE) || defined(MODULAR) || defined(_MODULE)
101 void *ci_battable; /* BAT table in use by this CPU */
102 #endif
103 struct lwp *ci_softlwps[SOFTINT_COUNT];
104 int ci_cpuid; /* from SPR_PIR */
105
106 int ci_want_resched;
107 volatile uint64_t ci_lastintr;
108 volatile u_long ci_lasttb;
109 volatile int ci_tickspending;
110 volatile int ci_cpl;
111 volatile int ci_iactive;
112 volatile int ci_idepth;
113 union {
114 #if !defined(PPC_BOOKE) && !defined(_MODULE)
115 volatile imask_t un1_ipending;
116 #define ci_ipending ci_un1.un1_ipending
117 #endif
118 uint64_t un1_pad64;
119 } ci_un1;
120 volatile uint32_t ci_pending_ipis;
121 int ci_mtx_oldspl;
122 int ci_mtx_count;
123 #if defined(PPC_IBM4XX) || \
124 ((defined(MODULAR) || defined(_MODULE)) && !defined(_LP64))
125 char *ci_intstk;
126 #endif
127
128 register_t ci_savearea[CPUSAVE_SIZE];
129 #if defined(PPC_BOOKE) || \
130 ((defined(MODULAR) || defined(_MODULE)) && !defined(_LP64))
131 uint32_t ci_pmap_asid_cur;
132 union pmap_segtab *ci_pmap_segtabs[2];
133 #define ci_pmap_kern_segtab ci_pmap_segtabs[0]
134 #define ci_pmap_user_segtab ci_pmap_segtabs[1]
135 struct pmap_tlb_info *ci_tlb_info;
136 #endif /* PPC_BOOKE || ((MODULAR || _MODULE) && !_LP64) */
137 struct cache_info ci_ci;
138 void *ci_sysmon_cookie;
139 void (*ci_idlespin)(void);
140 uint32_t ci_khz;
141 struct evcnt ci_ev_clock; /* clock intrs */
142 struct evcnt ci_ev_statclock; /* stat clock */
143 struct evcnt ci_ev_traps; /* calls to trap() */
144 struct evcnt ci_ev_kdsi; /* kernel DSI traps */
145 struct evcnt ci_ev_udsi; /* user DSI traps */
146 struct evcnt ci_ev_udsi_fatal; /* user DSI trap failures */
147 struct evcnt ci_ev_kisi; /* kernel ISI traps */
148 struct evcnt ci_ev_isi; /* user ISI traps */
149 struct evcnt ci_ev_isi_fatal; /* user ISI trap failures */
150 struct evcnt ci_ev_pgm; /* user PGM traps */
151 struct evcnt ci_ev_debug; /* user debug traps */
152 struct evcnt ci_ev_fpu; /* FPU traps */
153 struct evcnt ci_ev_fpusw; /* FPU context switch */
154 struct evcnt ci_ev_ali; /* Alignment traps */
155 struct evcnt ci_ev_ali_fatal; /* Alignment fatal trap */
156 struct evcnt ci_ev_scalls; /* system call traps */
157 struct evcnt ci_ev_vec; /* Altivec traps */
158 struct evcnt ci_ev_vecsw; /* Altivec context switches */
159 struct evcnt ci_ev_umchk; /* user MCHK events */
160 struct evcnt ci_ev_ipi; /* IPIs received */
161 struct evcnt ci_ev_tlbmiss_soft; /* tlb miss (no trap) */
162 struct evcnt ci_ev_dtlbmiss_hard; /* data tlb miss (trap) */
163 struct evcnt ci_ev_itlbmiss_hard; /* instruction tlb miss (trap) */
164 #if defined(GPROF) && defined(MULTIPROCESSOR)
165 struct gmonparam *ci_gmon; /* MI per-cpu GPROF */
166 #endif
167 #endif /* _KERNEL */
168 };
169 #endif /* _KERNEL || _KMEMUSER */
170
171 #ifdef _KERNEL
172
173 #if defined(MULTIPROCESSOR) && !defined(_MODULE)
174 struct cpu_hatch_data {
175 int hatch_running;
176 device_t hatch_self;
177 struct cpu_info *hatch_ci;
178 uint32_t hatch_tbu;
179 uint32_t hatch_tbl;
180 #if defined(PPC_OEA64_BRIDGE) || defined (_ARCH_PPC64)
181 uint64_t hatch_hid0;
182 uint64_t hatch_hid1;
183 uint64_t hatch_hid4;
184 uint64_t hatch_hid5;
185 #else
186 uint32_t hatch_hid0;
187 #endif
188 uint32_t hatch_pir;
189 #if defined(PPC_OEA) || defined(PPC_OEA64_BRIDGE)
190 uintptr_t hatch_asr;
191 uintptr_t hatch_sdr1;
192 uint32_t hatch_sr[16];
193 uintptr_t hatch_ibatu[8], hatch_ibatl[8];
194 uintptr_t hatch_dbatu[8], hatch_dbatl[8];
195 #endif
196 #if defined(PPC_BOOKE)
197 vaddr_t hatch_sp;
198 u_int hatch_tlbidx;
199 #endif
200 };
201
202 struct cpuset_info {
203 kcpuset_t *cpus_running;
204 kcpuset_t *cpus_hatched;
205 kcpuset_t *cpus_paused;
206 kcpuset_t *cpus_resumed;
207 kcpuset_t *cpus_halted;
208 };
209
210 extern struct cpuset_info cpuset_info;
211 #endif /* MULTIPROCESSOR && !_MODULE */
212
213 #if defined(MULTIPROCESSOR) || defined(_MODULE)
214 #define cpu_number() (curcpu()->ci_index + 0)
215
216 #define CPU_IS_PRIMARY(ci) ((ci)->ci_cpuid == 0)
217 #define CPU_INFO_ITERATOR int
218 #define CPU_INFO_FOREACH(cii, ci) \
219 cii = 0, ci = &cpu_info[0]; cii < (ncpu ? ncpu : 1); cii++, ci++
220
221 #else
222 #define cpu_number() 0
223
224 #define CPU_IS_PRIMARY(ci) true
225 #define CPU_INFO_ITERATOR int
226 #define CPU_INFO_FOREACH(cii, ci) \
227 (void)cii, ci = curcpu(); ci != NULL; ci = NULL
228
229 #endif /* MULTIPROCESSOR || _MODULE */
230
231 extern struct cpu_info cpu_info[];
232
233 static __inline struct cpu_info * curcpu(void) __pure;
234 static __inline __always_inline struct cpu_info *
curcpu(void)235 curcpu(void)
236 {
237 struct cpu_info *ci;
238
239 __asm volatile ("mfsprg0 %0" : "=r"(ci));
240 return ci;
241 }
242
243 register struct lwp *powerpc_curlwp __asm("r13");
244 #define curlwp powerpc_curlwp
245 #define curpcb (curcpu()->ci_curpcb)
246 #define curpm (curcpu()->ci_curpm)
247
248 static __inline register_t
mfmsr(void)249 mfmsr(void)
250 {
251 register_t msr;
252
253 __asm volatile ("mfmsr %0" : "=r"(msr));
254 return msr;
255 }
256
257 static __inline void
mtmsr(register_t msr)258 mtmsr(register_t msr)
259 {
260 //KASSERT(msr & PSL_CE);
261 //KASSERT(msr & PSL_DE);
262 __asm volatile ("mtmsr %0" : : "r"(msr));
263 }
264
265 #if !defined(_MODULE)
266 static __inline uint32_t
mftbl(void)267 mftbl(void)
268 {
269 uint32_t tbl;
270
271 __asm volatile (
272 #ifdef PPC_IBM403
273 " mftblo %[tbl]" "\n"
274 #elif defined(PPC_BOOKE)
275 " mfspr %[tbl],268" "\n"
276 #else
277 " mftbl %[tbl]" "\n"
278 #endif
279 : [tbl] "=r" (tbl));
280
281 return tbl;
282 }
283
284 static __inline uint64_t
mftb(void)285 mftb(void)
286 {
287 uint64_t tb;
288
289 #ifdef _ARCH_PPC64
290 __asm volatile ("mftb %0" : "=r"(tb));
291 #else
292 int tmp;
293
294 __asm volatile (
295 #ifdef PPC_IBM403
296 "1: mftbhi %[tb]" "\n"
297 " mftblo %L[tb]" "\n"
298 " mftbhi %[tmp]" "\n"
299 #elif defined(PPC_BOOKE)
300 "1: mfspr %[tb],269" "\n"
301 " mfspr %L[tb],268" "\n"
302 " mfspr %[tmp],269" "\n"
303 #else
304 "1: mftbu %[tb]" "\n"
305 " mftb %L[tb]" "\n"
306 " mftbu %[tmp]" "\n"
307 #endif
308 " cmplw %[tb],%[tmp]" "\n"
309 " bne- 1b" "\n"
310 : [tb] "=r" (tb), [tmp] "=r"(tmp)
311 :: "cr0");
312 #endif
313
314 return tb;
315 }
316
317 static __inline uint32_t
mfrtcl(void)318 mfrtcl(void)
319 {
320 uint32_t rtcl;
321
322 __asm volatile ("mfrtcl %0" : "=r"(rtcl));
323 return rtcl;
324 }
325
326 static __inline void
mfrtc(uint32_t * rtcp)327 mfrtc(uint32_t *rtcp)
328 {
329 uint32_t tmp;
330
331 __asm volatile (
332 "1: mfrtcu %[rtcu]" "\n"
333 " mfrtcl %[rtcl]" "\n"
334 " mfrtcu %[tmp]" "\n"
335 " cmplw %[rtcu],%[tmp]" "\n"
336 " bne- 1b"
337 : [rtcu] "=r"(rtcp[0]), [rtcl] "=r"(rtcp[1]), [tmp] "=r"(tmp)
338 :: "cr0");
339 }
340
341 static __inline uint64_t
rtc_nanosecs(void)342 rtc_nanosecs(void)
343 {
344 /*
345 * 601 RTC/DEC registers share clock of 7.8125 MHz, 128 ns per tick.
346 * DEC has max of 25 bits, FFFFFF => 2.14748352 seconds.
347 * RTCU is seconds, 32 bits.
348 * RTCL is nano-seconds, 23 bit counter from 0 - 999,999,872 (999,999,999 - 128 ns)
349 */
350 uint64_t cycles;
351 uint32_t tmp[2];
352
353 mfrtc(tmp);
354
355 cycles = tmp[0] * 1000000000;
356 cycles += (tmp[1] >> 7);
357
358 return cycles;
359 }
360 #endif /* !_MODULE */
361
362 static __inline uint32_t
mfpvr(void)363 mfpvr(void)
364 {
365 uint32_t pvr;
366
367 __asm volatile ("mfpvr %0" : "=r"(pvr));
368 return (pvr);
369 }
370
371 #ifdef _MODULE
372 extern const char __CPU_MAXNUM;
373 /*
374 * Make with 0xffff to force a R_PPC_ADDR16_LO without the
375 * corresponding R_PPC_ADDR16_HI relocation.
376 */
377 #define CPU_MAXNUM (((uintptr_t)&__CPU_MAXNUM)&0xffff)
378 #endif /* _MODULE */
379
380 #if !defined(_MODULE)
381 extern char *booted_kernel;
382 extern int powersave;
383 extern int cpu_timebase;
384 extern int cpu_printfataltraps;
385
386 struct cpu_info *
387 cpu_attach_common(device_t, int);
388 void cpu_setup(device_t, struct cpu_info *);
389 void cpu_identify(char *, size_t);
390 void cpu_probe_cache(void);
391
392 void dcache_wb_page(vaddr_t);
393 void dcache_wbinv_page(vaddr_t);
394 void dcache_inv_page(vaddr_t);
395 void dcache_zero_page(vaddr_t);
396 void icache_inv_page(vaddr_t);
397 void dcache_wb(vaddr_t, vsize_t);
398 void dcache_wbinv(vaddr_t, vsize_t);
399 void dcache_inv(vaddr_t, vsize_t);
400 void icache_inv(vaddr_t, vsize_t);
401
402 void * mapiodev(paddr_t, psize_t, bool);
403 void unmapiodev(vaddr_t, vsize_t);
404
405 int emulate_mxmsr(struct lwp *, struct trapframe *, uint32_t);
406
407 #ifdef MULTIPROCESSOR
408 int md_setup_trampoline(volatile struct cpu_hatch_data *,
409 struct cpu_info *);
410 void md_presync_timebase(volatile struct cpu_hatch_data *);
411 void md_start_timebase(volatile struct cpu_hatch_data *);
412 void md_sync_timebase(volatile struct cpu_hatch_data *);
413 void md_setup_interrupts(void);
414 int cpu_spinup(device_t, struct cpu_info *);
415 register_t
416 cpu_hatch(void);
417 void cpu_spinup_trampoline(void);
418 void cpu_boot_secondary_processors(void);
419 void cpu_halt(void);
420 void cpu_halt_others(void);
421 void cpu_pause(struct trapframe *);
422 void cpu_pause_others(void);
423 void cpu_resume(cpuid_t);
424 void cpu_resume_others(void);
425 int cpu_is_paused(int);
426 void cpu_debug_dump(void);
427 #endif /* MULTIPROCESSOR */
428 #endif /* !_MODULE */
429
430 #define cpu_proc_fork(p1, p2)
431
432 #ifndef __HIDE_DELAY
433 #define DELAY(n) delay(n)
434 void delay(unsigned int);
435 #endif /* __HIDE_DELAY */
436
437 #define CLKF_USERMODE(cf) cpu_clkf_usermode(cf)
438 #define CLKF_PC(cf) cpu_clkf_pc(cf)
439 #define CLKF_INTR(cf) cpu_clkf_intr(cf)
440
441 bool cpu_clkf_usermode(const struct clockframe *);
442 vaddr_t cpu_clkf_pc(const struct clockframe *);
443 bool cpu_clkf_intr(const struct clockframe *);
444
445 #define LWP_PC(l) cpu_lwp_pc(l)
446
447 vaddr_t cpu_lwp_pc(struct lwp *);
448
449 void cpu_ast(struct lwp *, struct cpu_info *);
450 void * cpu_uarea_alloc(bool);
451 bool cpu_uarea_free(void *);
452 void cpu_signotify(struct lwp *);
453 void cpu_need_proftick(struct lwp *);
454
455 void cpu_fixup_stubs(void);
456
457 #if !defined(PPC_IBM4XX) && !defined(PPC_BOOKE) && !defined(_MODULE)
458 int cpu_get_dfs(void);
459 void cpu_set_dfs(int);
460
461 void oea_init(void (*)(void));
462 void oea_startup(const char *);
463 void oea_dumpsys(void);
464 void oea_install_extint(void (*)(void));
465 paddr_t kvtop(void *);
466
467 extern paddr_t msgbuf_paddr;
468 extern int cpu_altivec;
469 #endif
470
471 #ifdef PPC_NO_UNALIGNED
472 bool fix_unaligned(struct trapframe *, ksiginfo_t *);
473 #endif
474
475 #endif /* _KERNEL */
476
477 /* XXX The below breaks unified pmap on ppc32 */
478
479 #if !defined(CACHELINESIZE) && !defined(_MODULE) \
480 && (defined(_KERNEL) || defined(_STANDALONE))
481 #if defined(PPC_IBM403)
482 #define CACHELINESIZE 16
483 #define MAXCACHELINESIZE 16
484 #elif defined (PPC_OEA64_BRIDGE)
485 #define CACHELINESIZE 128
486 #define MAXCACHELINESIZE 128
487 #else
488 #define CACHELINESIZE 32
489 #define MAXCACHELINESIZE 32
490 #endif /* PPC_OEA64_BRIDGE */
491 #endif
492
493 void __syncicache(void *, size_t);
494
495 /*
496 * CTL_MACHDEP definitions.
497 */
498 #define CPU_CACHELINE 1
499 #define CPU_TIMEBASE 2
500 #define CPU_CPUTEMP 3
501 #define CPU_PRINTFATALTRAPS 4
502 #define CPU_CACHEINFO 5
503 #define CPU_ALTIVEC 6
504 #define CPU_MODEL 7
505 #define CPU_POWERSAVE 8 /* int: use CPU powersave mode */
506 #define CPU_BOOTED_DEVICE 9 /* string: device we booted from */
507 #define CPU_BOOTED_KERNEL 10 /* string: kernel we booted */
508 #define CPU_EXECPROT 11 /* bool: PROT_EXEC works */
509 #define CPU_FPU 12
510 #define CPU_NO_UNALIGNED 13 /* No HW support for unaligned access */
511
512 #endif /* _POWERPC_CPU_H_ */
513