| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training.c | 337 u32 if_id; in hws_ddr3_tip_init_controller() local
1065 int ddr3_tip_bus_read(u32 dev_num, u32 if_id, in ddr3_tip_bus_read()
1094 u32 data_val = 0, if_id, start_if, end_if; in ddr3_tip_bus_read_modify_write() local
1806 u32 if_id; in ddr3_tip_write_mrs_cmd() local
1837 u32 if_id = 0; in ddr3_tip_reset_fifo_ptr() local
1876 u32 if_id, phy_id, cs; in ddr3_tip_ddr3_reset_phy_regs() local
1978 u32 if_id, phy_id; in ddr3_tip_adll_regs_bypass() local
2011 u32 if_id; in ddr3_tip_ddr3_training_main_flow() local
2474 u32 if_id, stage; in ddr3_tip_ddr3_auto_tune() local
2661 u32 hws_ddr3_get_device_width(u32 if_id) in hws_ddr3_get_device_width()
[all …]
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| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training.c | 337 u32 if_id; in hws_ddr3_tip_init_controller() local
1065 int ddr3_tip_bus_read(u32 dev_num, u32 if_id, in ddr3_tip_bus_read()
1094 u32 data_val = 0, if_id, start_if, end_if; in ddr3_tip_bus_read_modify_write() local
1806 u32 if_id; in ddr3_tip_write_mrs_cmd() local
1837 u32 if_id = 0; in ddr3_tip_reset_fifo_ptr() local
1876 u32 if_id, phy_id, cs; in ddr3_tip_ddr3_reset_phy_regs() local
1978 u32 if_id, phy_id; in ddr3_tip_adll_regs_bypass() local
2011 u32 if_id; in ddr3_tip_ddr3_training_main_flow() local
2474 u32 if_id, stage; in ddr3_tip_ddr3_auto_tune() local
2661 u32 hws_ddr3_get_device_width(u32 if_id) in hws_ddr3_get_device_width()
[all …]
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| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training.c | 340 u32 if_id; in hws_ddr3_tip_init_controller() local
1068 int ddr3_tip_bus_read(u32 dev_num, u32 if_id, in ddr3_tip_bus_read()
1097 u32 data_val = 0, if_id, start_if, end_if; in ddr3_tip_bus_read_modify_write() local
1811 u32 if_id; in ddr3_tip_write_mrs_cmd() local
1842 u32 if_id = 0; in ddr3_tip_reset_fifo_ptr() local
1881 u32 if_id, phy_id, cs; in ddr3_tip_ddr3_reset_phy_regs() local
1983 u32 if_id, phy_id; in ddr3_tip_adll_regs_bypass() local
2014 u32 if_id; in ddr3_tip_ddr3_training_main_flow() local
2475 u32 if_id, stage; in ddr3_tip_ddr3_auto_tune() local
2662 u32 hws_ddr3_get_device_width(u32 if_id) in hws_ddr3_get_device_width()
[all …]
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| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training.c | 340 u32 if_id; in hws_ddr3_tip_init_controller() local
1068 int ddr3_tip_bus_read(u32 dev_num, u32 if_id, in ddr3_tip_bus_read()
1097 u32 data_val = 0, if_id, start_if, end_if; in ddr3_tip_bus_read_modify_write() local
1811 u32 if_id; in ddr3_tip_write_mrs_cmd() local
1842 u32 if_id = 0; in ddr3_tip_reset_fifo_ptr() local
1881 u32 if_id, phy_id, cs; in ddr3_tip_ddr3_reset_phy_regs() local
1983 u32 if_id, phy_id; in ddr3_tip_adll_regs_bypass() local
2014 u32 if_id; in ddr3_tip_ddr3_training_main_flow() local
2475 u32 if_id, stage; in ddr3_tip_ddr3_auto_tune() local
2662 u32 hws_ddr3_get_device_width(u32 if_id) in hws_ddr3_get_device_width()
[all …]
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| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training.c | 340 u32 if_id; in hws_ddr3_tip_init_controller() local
1068 int ddr3_tip_bus_read(u32 dev_num, u32 if_id, in ddr3_tip_bus_read()
1097 u32 data_val = 0, if_id, start_if, end_if; in ddr3_tip_bus_read_modify_write() local
1811 u32 if_id; in ddr3_tip_write_mrs_cmd() local
1842 u32 if_id = 0; in ddr3_tip_reset_fifo_ptr() local
1881 u32 if_id, phy_id, cs; in ddr3_tip_ddr3_reset_phy_regs() local
1983 u32 if_id, phy_id; in ddr3_tip_adll_regs_bypass() local
2014 u32 if_id; in ddr3_tip_ddr3_training_main_flow() local
2475 u32 if_id, stage; in ddr3_tip_ddr3_auto_tune() local
2662 u32 hws_ddr3_get_device_width(u32 if_id) in hws_ddr3_get_device_width()
[all …]
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| /dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training.c | 340 u32 if_id; in hws_ddr3_tip_init_controller() local
1068 int ddr3_tip_bus_read(u32 dev_num, u32 if_id, in ddr3_tip_bus_read()
1097 u32 data_val = 0, if_id, start_if, end_if; in ddr3_tip_bus_read_modify_write() local
1811 u32 if_id; in ddr3_tip_write_mrs_cmd() local
1842 u32 if_id = 0; in ddr3_tip_reset_fifo_ptr() local
1881 u32 if_id, phy_id, cs; in ddr3_tip_ddr3_reset_phy_regs() local
1983 u32 if_id, phy_id; in ddr3_tip_adll_regs_bypass() local
2014 u32 if_id; in ddr3_tip_ddr3_training_main_flow() local
2475 u32 if_id, stage; in ddr3_tip_ddr3_auto_tune() local
2662 u32 hws_ddr3_get_device_width(u32 if_id) in hws_ddr3_get_device_width()
[all …]
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| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training.c | 337 u32 if_id; in hws_ddr3_tip_init_controller() local
1065 int ddr3_tip_bus_read(u32 dev_num, u32 if_id, in ddr3_tip_bus_read()
1094 u32 data_val = 0, if_id, start_if, end_if; in ddr3_tip_bus_read_modify_write() local
1806 u32 if_id; in ddr3_tip_write_mrs_cmd() local
1837 u32 if_id = 0; in ddr3_tip_reset_fifo_ptr() local
1876 u32 if_id, phy_id, cs; in ddr3_tip_ddr3_reset_phy_regs() local
1978 u32 if_id, phy_id; in ddr3_tip_adll_regs_bypass() local
2011 u32 if_id; in ddr3_tip_ddr3_training_main_flow() local
2474 u32 if_id, stage; in ddr3_tip_ddr3_auto_tune() local
2661 u32 hws_ddr3_get_device_width(u32 if_id) in hws_ddr3_get_device_width()
[all …]
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| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training.c | 340 u32 if_id; in hws_ddr3_tip_init_controller() local
1068 int ddr3_tip_bus_read(u32 dev_num, u32 if_id, in ddr3_tip_bus_read()
1097 u32 data_val = 0, if_id, start_if, end_if; in ddr3_tip_bus_read_modify_write() local
1811 u32 if_id; in ddr3_tip_write_mrs_cmd() local
1842 u32 if_id = 0; in ddr3_tip_reset_fifo_ptr() local
1881 u32 if_id, phy_id, cs; in ddr3_tip_ddr3_reset_phy_regs() local
1983 u32 if_id, phy_id; in ddr3_tip_adll_regs_bypass() local
2014 u32 if_id; in ddr3_tip_ddr3_training_main_flow() local
2475 u32 if_id, stage; in ddr3_tip_ddr3_auto_tune() local
2662 u32 hws_ddr3_get_device_width(u32 if_id) in hws_ddr3_get_device_width()
[all …]
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| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training.c | 340 u32 if_id; in hws_ddr3_tip_init_controller() local
1068 int ddr3_tip_bus_read(u32 dev_num, u32 if_id, in ddr3_tip_bus_read()
1097 u32 data_val = 0, if_id, start_if, end_if; in ddr3_tip_bus_read_modify_write() local
1811 u32 if_id; in ddr3_tip_write_mrs_cmd() local
1842 u32 if_id = 0; in ddr3_tip_reset_fifo_ptr() local
1881 u32 if_id, phy_id, cs; in ddr3_tip_ddr3_reset_phy_regs() local
1983 u32 if_id, phy_id; in ddr3_tip_adll_regs_bypass() local
2014 u32 if_id; in ddr3_tip_ddr3_training_main_flow() local
2475 u32 if_id, stage; in ddr3_tip_ddr3_auto_tune() local
2662 u32 hws_ddr3_get_device_width(u32 if_id) in hws_ddr3_get_device_width()
[all …]
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| /dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training.c | 340 u32 if_id; in hws_ddr3_tip_init_controller() local
1068 int ddr3_tip_bus_read(u32 dev_num, u32 if_id, in ddr3_tip_bus_read()
1097 u32 data_val = 0, if_id, start_if, end_if; in ddr3_tip_bus_read_modify_write() local
1811 u32 if_id; in ddr3_tip_write_mrs_cmd() local
1842 u32 if_id = 0; in ddr3_tip_reset_fifo_ptr() local
1881 u32 if_id, phy_id, cs; in ddr3_tip_ddr3_reset_phy_regs() local
1983 u32 if_id, phy_id; in ddr3_tip_adll_regs_bypass() local
2014 u32 if_id; in ddr3_tip_ddr3_training_main_flow() local
2475 u32 if_id, stage; in ddr3_tip_ddr3_auto_tune() local
2662 u32 hws_ddr3_get_device_width(u32 if_id) in hws_ddr3_get_device_width()
[all …]
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| /dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training.c | 340 u32 if_id; in hws_ddr3_tip_init_controller() local
1068 int ddr3_tip_bus_read(u32 dev_num, u32 if_id, in ddr3_tip_bus_read()
1097 u32 data_val = 0, if_id, start_if, end_if; in ddr3_tip_bus_read_modify_write() local
1811 u32 if_id; in ddr3_tip_write_mrs_cmd() local
1842 u32 if_id = 0; in ddr3_tip_reset_fifo_ptr() local
1881 u32 if_id, phy_id, cs; in ddr3_tip_ddr3_reset_phy_regs() local
1983 u32 if_id, phy_id; in ddr3_tip_adll_regs_bypass() local
2014 u32 if_id; in ddr3_tip_ddr3_training_main_flow() local
2475 u32 if_id, stage; in ddr3_tip_ddr3_auto_tune() local
2662 u32 hws_ddr3_get_device_width(u32 if_id) in hws_ddr3_get_device_width()
[all …]
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| /dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training.c | 340 u32 if_id; in hws_ddr3_tip_init_controller() local
1068 int ddr3_tip_bus_read(u32 dev_num, u32 if_id, in ddr3_tip_bus_read()
1097 u32 data_val = 0, if_id, start_if, end_if; in ddr3_tip_bus_read_modify_write() local
1811 u32 if_id; in ddr3_tip_write_mrs_cmd() local
1842 u32 if_id = 0; in ddr3_tip_reset_fifo_ptr() local
1881 u32 if_id, phy_id, cs; in ddr3_tip_ddr3_reset_phy_regs() local
1983 u32 if_id, phy_id; in ddr3_tip_adll_regs_bypass() local
2014 u32 if_id; in ddr3_tip_ddr3_training_main_flow() local
2475 u32 if_id, stage; in ddr3_tip_ddr3_auto_tune() local
2662 u32 hws_ddr3_get_device_width(u32 if_id) in hws_ddr3_get_device_width()
[all …]
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| /dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training.c | 340 u32 if_id; in hws_ddr3_tip_init_controller() local
1068 int ddr3_tip_bus_read(u32 dev_num, u32 if_id, in ddr3_tip_bus_read()
1097 u32 data_val = 0, if_id, start_if, end_if; in ddr3_tip_bus_read_modify_write() local
1811 u32 if_id; in ddr3_tip_write_mrs_cmd() local
1842 u32 if_id = 0; in ddr3_tip_reset_fifo_ptr() local
1881 u32 if_id, phy_id, cs; in ddr3_tip_ddr3_reset_phy_regs() local
1983 u32 if_id, phy_id; in ddr3_tip_adll_regs_bypass() local
2014 u32 if_id; in ddr3_tip_ddr3_training_main_flow() local
2475 u32 if_id, stage; in ddr3_tip_ddr3_auto_tune() local
2662 u32 hws_ddr3_get_device_width(u32 if_id) in hws_ddr3_get_device_width()
[all …]
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| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training.c | 340 u32 if_id; in hws_ddr3_tip_init_controller() local
1068 int ddr3_tip_bus_read(u32 dev_num, u32 if_id, in ddr3_tip_bus_read()
1097 u32 data_val = 0, if_id, start_if, end_if; in ddr3_tip_bus_read_modify_write() local
1811 u32 if_id; in ddr3_tip_write_mrs_cmd() local
1842 u32 if_id = 0; in ddr3_tip_reset_fifo_ptr() local
1881 u32 if_id, phy_id, cs; in ddr3_tip_ddr3_reset_phy_regs() local
1983 u32 if_id, phy_id; in ddr3_tip_adll_regs_bypass() local
2014 u32 if_id; in ddr3_tip_ddr3_training_main_flow() local
2475 u32 if_id, stage; in ddr3_tip_ddr3_auto_tune() local
2662 u32 hws_ddr3_get_device_width(u32 if_id) in hws_ddr3_get_device_width()
[all …]
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| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training.c | 340 u32 if_id; in hws_ddr3_tip_init_controller() local
1068 int ddr3_tip_bus_read(u32 dev_num, u32 if_id, in ddr3_tip_bus_read()
1097 u32 data_val = 0, if_id, start_if, end_if; in ddr3_tip_bus_read_modify_write() local
1811 u32 if_id; in ddr3_tip_write_mrs_cmd() local
1842 u32 if_id = 0; in ddr3_tip_reset_fifo_ptr() local
1881 u32 if_id, phy_id, cs; in ddr3_tip_ddr3_reset_phy_regs() local
1983 u32 if_id, phy_id; in ddr3_tip_adll_regs_bypass() local
2014 u32 if_id; in ddr3_tip_ddr3_training_main_flow() local
2475 u32 if_id, stage; in ddr3_tip_ddr3_auto_tune() local
2662 u32 hws_ddr3_get_device_width(u32 if_id) in hws_ddr3_get_device_width()
[all …]
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| /dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training.c | 340 u32 if_id; in hws_ddr3_tip_init_controller() local
1068 int ddr3_tip_bus_read(u32 dev_num, u32 if_id, in ddr3_tip_bus_read()
1097 u32 data_val = 0, if_id, start_if, end_if; in ddr3_tip_bus_read_modify_write() local
1811 u32 if_id; in ddr3_tip_write_mrs_cmd() local
1842 u32 if_id = 0; in ddr3_tip_reset_fifo_ptr() local
1881 u32 if_id, phy_id, cs; in ddr3_tip_ddr3_reset_phy_regs() local
1983 u32 if_id, phy_id; in ddr3_tip_adll_regs_bypass() local
2014 u32 if_id; in ddr3_tip_ddr3_training_main_flow() local
2475 u32 if_id, stage; in ddr3_tip_ddr3_auto_tune() local
2662 u32 hws_ddr3_get_device_width(u32 if_id) in hws_ddr3_get_device_width()
[all …]
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| /dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training.c | 340 u32 if_id; in hws_ddr3_tip_init_controller() local
1068 int ddr3_tip_bus_read(u32 dev_num, u32 if_id, in ddr3_tip_bus_read()
1097 u32 data_val = 0, if_id, start_if, end_if; in ddr3_tip_bus_read_modify_write() local
1811 u32 if_id; in ddr3_tip_write_mrs_cmd() local
1842 u32 if_id = 0; in ddr3_tip_reset_fifo_ptr() local
1881 u32 if_id, phy_id, cs; in ddr3_tip_ddr3_reset_phy_regs() local
1983 u32 if_id, phy_id; in ddr3_tip_adll_regs_bypass() local
2014 u32 if_id; in ddr3_tip_ddr3_training_main_flow() local
2475 u32 if_id, stage; in ddr3_tip_ddr3_auto_tune() local
2662 u32 hws_ddr3_get_device_width(u32 if_id) in hws_ddr3_get_device_width()
[all …]
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| /dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training.c | 340 u32 if_id; in hws_ddr3_tip_init_controller() local
1068 int ddr3_tip_bus_read(u32 dev_num, u32 if_id, in ddr3_tip_bus_read()
1097 u32 data_val = 0, if_id, start_if, end_if; in ddr3_tip_bus_read_modify_write() local
1811 u32 if_id; in ddr3_tip_write_mrs_cmd() local
1842 u32 if_id = 0; in ddr3_tip_reset_fifo_ptr() local
1881 u32 if_id, phy_id, cs; in ddr3_tip_ddr3_reset_phy_regs() local
1983 u32 if_id, phy_id; in ddr3_tip_adll_regs_bypass() local
2014 u32 if_id; in ddr3_tip_ddr3_training_main_flow() local
2475 u32 if_id, stage; in ddr3_tip_ddr3_auto_tune() local
2662 u32 hws_ddr3_get_device_width(u32 if_id) in hws_ddr3_get_device_width()
[all …]
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| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training.c | 340 u32 if_id; in hws_ddr3_tip_init_controller() local
1068 int ddr3_tip_bus_read(u32 dev_num, u32 if_id, in ddr3_tip_bus_read()
1097 u32 data_val = 0, if_id, start_if, end_if; in ddr3_tip_bus_read_modify_write() local
1811 u32 if_id; in ddr3_tip_write_mrs_cmd() local
1842 u32 if_id = 0; in ddr3_tip_reset_fifo_ptr() local
1881 u32 if_id, phy_id, cs; in ddr3_tip_ddr3_reset_phy_regs() local
1983 u32 if_id, phy_id; in ddr3_tip_adll_regs_bypass() local
2014 u32 if_id; in ddr3_tip_ddr3_training_main_flow() local
2475 u32 if_id, stage; in ddr3_tip_ddr3_auto_tune() local
2662 u32 hws_ddr3_get_device_width(u32 if_id) in hws_ddr3_get_device_width()
[all …]
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| /dports/sysutils/u-boot-wandboard/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training.c | 340 u32 if_id; in hws_ddr3_tip_init_controller() local
1068 int ddr3_tip_bus_read(u32 dev_num, u32 if_id, in ddr3_tip_bus_read()
1097 u32 data_val = 0, if_id, start_if, end_if; in ddr3_tip_bus_read_modify_write() local
1811 u32 if_id; in ddr3_tip_write_mrs_cmd() local
1842 u32 if_id = 0; in ddr3_tip_reset_fifo_ptr() local
1881 u32 if_id, phy_id, cs; in ddr3_tip_ddr3_reset_phy_regs() local
1983 u32 if_id, phy_id; in ddr3_tip_adll_regs_bypass() local
2014 u32 if_id; in ddr3_tip_ddr3_training_main_flow() local
2475 u32 if_id, stage; in ddr3_tip_ddr3_auto_tune() local
2662 u32 hws_ddr3_get_device_width(u32 if_id) in hws_ddr3_get_device_width()
[all …]
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| /dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training.c | 340 u32 if_id; in hws_ddr3_tip_init_controller() local
1068 int ddr3_tip_bus_read(u32 dev_num, u32 if_id, in ddr3_tip_bus_read()
1097 u32 data_val = 0, if_id, start_if, end_if; in ddr3_tip_bus_read_modify_write() local
1811 u32 if_id; in ddr3_tip_write_mrs_cmd() local
1842 u32 if_id = 0; in ddr3_tip_reset_fifo_ptr() local
1881 u32 if_id, phy_id, cs; in ddr3_tip_ddr3_reset_phy_regs() local
1983 u32 if_id, phy_id; in ddr3_tip_adll_regs_bypass() local
2014 u32 if_id; in ddr3_tip_ddr3_training_main_flow() local
2475 u32 if_id, stage; in ddr3_tip_ddr3_auto_tune() local
2662 u32 hws_ddr3_get_device_width(u32 if_id) in hws_ddr3_get_device_width()
[all …]
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| /dports/sysutils/u-boot-beaglebone/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training.c | 340 u32 if_id; in hws_ddr3_tip_init_controller() local
1068 int ddr3_tip_bus_read(u32 dev_num, u32 if_id, in ddr3_tip_bus_read()
1097 u32 data_val = 0, if_id, start_if, end_if; in ddr3_tip_bus_read_modify_write() local
1811 u32 if_id; in ddr3_tip_write_mrs_cmd() local
1842 u32 if_id = 0; in ddr3_tip_reset_fifo_ptr() local
1881 u32 if_id, phy_id, cs; in ddr3_tip_ddr3_reset_phy_regs() local
1983 u32 if_id, phy_id; in ddr3_tip_adll_regs_bypass() local
2014 u32 if_id; in ddr3_tip_ddr3_training_main_flow() local
2475 u32 if_id, stage; in ddr3_tip_ddr3_auto_tune() local
2662 u32 hws_ddr3_get_device_width(u32 if_id) in hws_ddr3_get_device_width()
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| /dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training.c | 337 u32 if_id; in hws_ddr3_tip_init_controller() local
1065 int ddr3_tip_bus_read(u32 dev_num, u32 if_id, in ddr3_tip_bus_read()
1094 u32 data_val = 0, if_id, start_if, end_if; in ddr3_tip_bus_read_modify_write() local
1806 u32 if_id; in ddr3_tip_write_mrs_cmd() local
1837 u32 if_id = 0; in ddr3_tip_reset_fifo_ptr() local
1876 u32 if_id, phy_id, cs; in ddr3_tip_ddr3_reset_phy_regs() local
1978 u32 if_id, phy_id; in ddr3_tip_adll_regs_bypass() local
2011 u32 if_id; in ddr3_tip_ddr3_training_main_flow() local
2474 u32 if_id, stage; in ddr3_tip_ddr3_auto_tune() local
2661 u32 hws_ddr3_get_device_width(u32 if_id) in hws_ddr3_get_device_width()
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| /dports/sysutils/u-boot-clearfog/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training.c | 340 u32 if_id; in hws_ddr3_tip_init_controller() local
1068 int ddr3_tip_bus_read(u32 dev_num, u32 if_id, in ddr3_tip_bus_read()
1097 u32 data_val = 0, if_id, start_if, end_if; in ddr3_tip_bus_read_modify_write() local
1811 u32 if_id; in ddr3_tip_write_mrs_cmd() local
1842 u32 if_id = 0; in ddr3_tip_reset_fifo_ptr() local
1881 u32 if_id, phy_id, cs; in ddr3_tip_ddr3_reset_phy_regs() local
1983 u32 if_id, phy_id; in ddr3_tip_adll_regs_bypass() local
2014 u32 if_id; in ddr3_tip_ddr3_training_main_flow() local
2475 u32 if_id, stage; in ddr3_tip_ddr3_auto_tune() local
2662 u32 hws_ddr3_get_device_width(u32 if_id) in hws_ddr3_get_device_width()
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| /dports/sysutils/u-boot-cubieboard/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training.c | 340 u32 if_id; in hws_ddr3_tip_init_controller() local
1068 int ddr3_tip_bus_read(u32 dev_num, u32 if_id, in ddr3_tip_bus_read()
1097 u32 data_val = 0, if_id, start_if, end_if; in ddr3_tip_bus_read_modify_write() local
1811 u32 if_id; in ddr3_tip_write_mrs_cmd() local
1842 u32 if_id = 0; in ddr3_tip_reset_fifo_ptr() local
1881 u32 if_id, phy_id, cs; in ddr3_tip_ddr3_reset_phy_regs() local
1983 u32 if_id, phy_id; in ddr3_tip_adll_regs_bypass() local
2014 u32 if_id; in ddr3_tip_ddr3_training_main_flow() local
2475 u32 if_id, stage; in ddr3_tip_ddr3_auto_tune() local
2662 u32 hws_ddr3_get_device_width(u32 if_id) in hws_ddr3_get_device_width()
[all …]
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