1 /*-
2 * Copyright 2021 Intel Corp
3 * Copyright 2021 Rubicon Communications, LLC (Netgate)
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <sys/cdefs.h>
8 #include "igc_api.h"
9
10 static s32 igc_wait_autoneg(struct igc_hw *hw);
11
12 /**
13 * igc_init_phy_ops_generic - Initialize PHY function pointers
14 * @hw: pointer to the HW structure
15 *
16 * Setups up the function pointers to no-op functions
17 **/
igc_init_phy_ops_generic(struct igc_hw * hw)18 void igc_init_phy_ops_generic(struct igc_hw *hw)
19 {
20 struct igc_phy_info *phy = &hw->phy;
21 DEBUGFUNC("igc_init_phy_ops_generic");
22
23 /* Initialize function pointers */
24 phy->ops.init_params = igc_null_ops_generic;
25 phy->ops.acquire = igc_null_ops_generic;
26 phy->ops.check_reset_block = igc_null_ops_generic;
27 phy->ops.force_speed_duplex = igc_null_ops_generic;
28 phy->ops.get_info = igc_null_ops_generic;
29 phy->ops.set_page = igc_null_set_page;
30 phy->ops.read_reg = igc_null_read_reg;
31 phy->ops.read_reg_locked = igc_null_read_reg;
32 phy->ops.read_reg_page = igc_null_read_reg;
33 phy->ops.release = igc_null_phy_generic;
34 phy->ops.reset = igc_null_ops_generic;
35 phy->ops.set_d0_lplu_state = igc_null_lplu_state;
36 phy->ops.set_d3_lplu_state = igc_null_lplu_state;
37 phy->ops.write_reg = igc_null_write_reg;
38 phy->ops.write_reg_locked = igc_null_write_reg;
39 phy->ops.write_reg_page = igc_null_write_reg;
40 phy->ops.power_up = igc_null_phy_generic;
41 phy->ops.power_down = igc_null_phy_generic;
42 }
43
44 /**
45 * igc_null_set_page - No-op function, return 0
46 * @hw: pointer to the HW structure
47 * @data: dummy variable
48 **/
igc_null_set_page(struct igc_hw IGC_UNUSEDARG * hw,u16 IGC_UNUSEDARG data)49 s32 igc_null_set_page(struct igc_hw IGC_UNUSEDARG *hw,
50 u16 IGC_UNUSEDARG data)
51 {
52 DEBUGFUNC("igc_null_set_page");
53 return IGC_SUCCESS;
54 }
55
56 /**
57 * igc_null_read_reg - No-op function, return 0
58 * @hw: pointer to the HW structure
59 * @offset: dummy variable
60 * @data: dummy variable
61 **/
igc_null_read_reg(struct igc_hw IGC_UNUSEDARG * hw,u32 IGC_UNUSEDARG offset,u16 IGC_UNUSEDARG * data)62 s32 igc_null_read_reg(struct igc_hw IGC_UNUSEDARG *hw,
63 u32 IGC_UNUSEDARG offset, u16 IGC_UNUSEDARG *data)
64 {
65 DEBUGFUNC("igc_null_read_reg");
66 return IGC_SUCCESS;
67 }
68
69 /**
70 * igc_null_phy_generic - No-op function, return void
71 * @hw: pointer to the HW structure
72 **/
igc_null_phy_generic(struct igc_hw IGC_UNUSEDARG * hw)73 void igc_null_phy_generic(struct igc_hw IGC_UNUSEDARG *hw)
74 {
75 DEBUGFUNC("igc_null_phy_generic");
76 return;
77 }
78
79 /**
80 * igc_null_lplu_state - No-op function, return 0
81 * @hw: pointer to the HW structure
82 * @active: dummy variable
83 **/
igc_null_lplu_state(struct igc_hw IGC_UNUSEDARG * hw,bool IGC_UNUSEDARG active)84 s32 igc_null_lplu_state(struct igc_hw IGC_UNUSEDARG *hw,
85 bool IGC_UNUSEDARG active)
86 {
87 DEBUGFUNC("igc_null_lplu_state");
88 return IGC_SUCCESS;
89 }
90
91 /**
92 * igc_null_write_reg - No-op function, return 0
93 * @hw: pointer to the HW structure
94 * @offset: dummy variable
95 * @data: dummy variable
96 **/
igc_null_write_reg(struct igc_hw IGC_UNUSEDARG * hw,u32 IGC_UNUSEDARG offset,u16 IGC_UNUSEDARG data)97 s32 igc_null_write_reg(struct igc_hw IGC_UNUSEDARG *hw,
98 u32 IGC_UNUSEDARG offset, u16 IGC_UNUSEDARG data)
99 {
100 DEBUGFUNC("igc_null_write_reg");
101 return IGC_SUCCESS;
102 }
103
104 /**
105 * igc_check_reset_block_generic - Check if PHY reset is blocked
106 * @hw: pointer to the HW structure
107 *
108 * Read the PHY management control register and check whether a PHY reset
109 * is blocked. If a reset is not blocked return IGC_SUCCESS, otherwise
110 * return IGC_BLK_PHY_RESET (12).
111 **/
igc_check_reset_block_generic(struct igc_hw * hw)112 s32 igc_check_reset_block_generic(struct igc_hw *hw)
113 {
114 u32 manc;
115
116 DEBUGFUNC("igc_check_reset_block");
117
118 manc = IGC_READ_REG(hw, IGC_MANC);
119
120 return (manc & IGC_MANC_BLK_PHY_RST_ON_IDE) ?
121 IGC_BLK_PHY_RESET : IGC_SUCCESS;
122 }
123
124 /**
125 * igc_get_phy_id - Retrieve the PHY ID and revision
126 * @hw: pointer to the HW structure
127 *
128 * Reads the PHY registers and stores the PHY ID and possibly the PHY
129 * revision in the hardware structure.
130 **/
igc_get_phy_id(struct igc_hw * hw)131 s32 igc_get_phy_id(struct igc_hw *hw)
132 {
133 struct igc_phy_info *phy = &hw->phy;
134 s32 ret_val = IGC_SUCCESS;
135 u16 phy_id;
136
137 DEBUGFUNC("igc_get_phy_id");
138
139 if (!phy->ops.read_reg)
140 return IGC_SUCCESS;
141
142 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
143 if (ret_val)
144 return ret_val;
145
146 phy->id = (u32)(phy_id << 16);
147 usec_delay(200);
148 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
149 if (ret_val)
150 return ret_val;
151
152 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
153 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
154
155 return IGC_SUCCESS;
156 }
157
158 /**
159 * igc_read_phy_reg_mdic - Read MDI control register
160 * @hw: pointer to the HW structure
161 * @offset: register offset to be read
162 * @data: pointer to the read data
163 *
164 * Reads the MDI control register in the PHY at offset and stores the
165 * information read to data.
166 **/
igc_read_phy_reg_mdic(struct igc_hw * hw,u32 offset,u16 * data)167 s32 igc_read_phy_reg_mdic(struct igc_hw *hw, u32 offset, u16 *data)
168 {
169 struct igc_phy_info *phy = &hw->phy;
170 u32 i, mdic = 0;
171
172 DEBUGFUNC("igc_read_phy_reg_mdic");
173
174 if (offset > MAX_PHY_REG_ADDRESS) {
175 DEBUGOUT1("PHY Address %d is out of range\n", offset);
176 return -IGC_ERR_PARAM;
177 }
178
179 /* Set up Op-code, Phy Address, and register offset in the MDI
180 * Control register. The MAC will take care of interfacing with the
181 * PHY to retrieve the desired data.
182 */
183 mdic = ((offset << IGC_MDIC_REG_SHIFT) |
184 (phy->addr << IGC_MDIC_PHY_SHIFT) |
185 (IGC_MDIC_OP_READ));
186
187 IGC_WRITE_REG(hw, IGC_MDIC, mdic);
188
189 /* Poll the ready bit to see if the MDI read completed
190 * Increasing the time out as testing showed failures with
191 * the lower time out
192 */
193 for (i = 0; i < (IGC_GEN_POLL_TIMEOUT * 3); i++) {
194 usec_delay_irq(50);
195 mdic = IGC_READ_REG(hw, IGC_MDIC);
196 if (mdic & IGC_MDIC_READY)
197 break;
198 }
199 if (!(mdic & IGC_MDIC_READY)) {
200 DEBUGOUT("MDI Read did not complete\n");
201 return -IGC_ERR_PHY;
202 }
203 if (mdic & IGC_MDIC_ERROR) {
204 DEBUGOUT("MDI Error\n");
205 return -IGC_ERR_PHY;
206 }
207 if (((mdic & IGC_MDIC_REG_MASK) >> IGC_MDIC_REG_SHIFT) != offset) {
208 DEBUGOUT2("MDI Read offset error - requested %d, returned %d\n",
209 offset,
210 (mdic & IGC_MDIC_REG_MASK) >> IGC_MDIC_REG_SHIFT);
211 return -IGC_ERR_PHY;
212 }
213 *data = (u16) mdic;
214
215 return IGC_SUCCESS;
216 }
217
218 /**
219 * igc_write_phy_reg_mdic - Write MDI control register
220 * @hw: pointer to the HW structure
221 * @offset: register offset to write to
222 * @data: data to write to register at offset
223 *
224 * Writes data to MDI control register in the PHY at offset.
225 **/
igc_write_phy_reg_mdic(struct igc_hw * hw,u32 offset,u16 data)226 s32 igc_write_phy_reg_mdic(struct igc_hw *hw, u32 offset, u16 data)
227 {
228 struct igc_phy_info *phy = &hw->phy;
229 u32 i, mdic = 0;
230
231 DEBUGFUNC("igc_write_phy_reg_mdic");
232
233 if (offset > MAX_PHY_REG_ADDRESS) {
234 DEBUGOUT1("PHY Address %d is out of range\n", offset);
235 return -IGC_ERR_PARAM;
236 }
237
238 /* Set up Op-code, Phy Address, and register offset in the MDI
239 * Control register. The MAC will take care of interfacing with the
240 * PHY to retrieve the desired data.
241 */
242 mdic = (((u32)data) |
243 (offset << IGC_MDIC_REG_SHIFT) |
244 (phy->addr << IGC_MDIC_PHY_SHIFT) |
245 (IGC_MDIC_OP_WRITE));
246
247 IGC_WRITE_REG(hw, IGC_MDIC, mdic);
248
249 /* Poll the ready bit to see if the MDI read completed
250 * Increasing the time out as testing showed failures with
251 * the lower time out
252 */
253 for (i = 0; i < (IGC_GEN_POLL_TIMEOUT * 3); i++) {
254 usec_delay_irq(50);
255 mdic = IGC_READ_REG(hw, IGC_MDIC);
256 if (mdic & IGC_MDIC_READY)
257 break;
258 }
259 if (!(mdic & IGC_MDIC_READY)) {
260 DEBUGOUT("MDI Write did not complete\n");
261 return -IGC_ERR_PHY;
262 }
263 if (mdic & IGC_MDIC_ERROR) {
264 DEBUGOUT("MDI Error\n");
265 return -IGC_ERR_PHY;
266 }
267 if (((mdic & IGC_MDIC_REG_MASK) >> IGC_MDIC_REG_SHIFT) != offset) {
268 DEBUGOUT2("MDI Write offset error - requested %d, returned %d\n",
269 offset,
270 (mdic & IGC_MDIC_REG_MASK) >> IGC_MDIC_REG_SHIFT);
271 return -IGC_ERR_PHY;
272 }
273
274 return IGC_SUCCESS;
275 }
276
277 /**
278 * igc_phy_setup_autoneg - Configure PHY for auto-negotiation
279 * @hw: pointer to the HW structure
280 *
281 * Reads the MII auto-neg advertisement register and/or the 1000T control
282 * register and if the PHY is already setup for auto-negotiation, then
283 * return successful. Otherwise, setup advertisement and flow control to
284 * the appropriate values for the wanted auto-negotiation.
285 **/
igc_phy_setup_autoneg(struct igc_hw * hw)286 static s32 igc_phy_setup_autoneg(struct igc_hw *hw)
287 {
288 struct igc_phy_info *phy = &hw->phy;
289 s32 ret_val;
290 u16 mii_autoneg_adv_reg;
291 u16 mii_1000t_ctrl_reg = 0;
292 u16 aneg_multigbt_an_ctrl = 0;
293
294 DEBUGFUNC("igc_phy_setup_autoneg");
295
296 phy->autoneg_advertised &= phy->autoneg_mask;
297
298 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
299 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
300 if (ret_val)
301 return ret_val;
302
303 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
304 /* Read the MII 1000Base-T Control Register (Address 9). */
305 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
306 &mii_1000t_ctrl_reg);
307 if (ret_val)
308 return ret_val;
309 }
310
311 if (phy->autoneg_mask & ADVERTISE_2500_FULL) {
312 /* Read the MULTI GBT AN Control Register - reg 7.32 */
313 ret_val = phy->ops.read_reg(hw, (STANDARD_AN_REG_MASK <<
314 MMD_DEVADDR_SHIFT) |
315 ANEG_MULTIGBT_AN_CTRL,
316 &aneg_multigbt_an_ctrl);
317
318 if (ret_val)
319 return ret_val;
320 }
321
322 /* Need to parse both autoneg_advertised and fc and set up
323 * the appropriate PHY registers. First we will parse for
324 * autoneg_advertised software override. Since we can advertise
325 * a plethora of combinations, we need to check each bit
326 * individually.
327 */
328
329 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
330 * Advertisement Register (Address 4) and the 1000 mb speed bits in
331 * the 1000Base-T Control Register (Address 9).
332 */
333 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
334 NWAY_AR_100TX_HD_CAPS |
335 NWAY_AR_10T_FD_CAPS |
336 NWAY_AR_10T_HD_CAPS);
337 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
338
339 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised);
340
341 /* Do we want to advertise 10 Mb Half Duplex? */
342 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
343 DEBUGOUT("Advertise 10mb Half duplex\n");
344 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
345 }
346
347 /* Do we want to advertise 10 Mb Full Duplex? */
348 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
349 DEBUGOUT("Advertise 10mb Full duplex\n");
350 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
351 }
352
353 /* Do we want to advertise 100 Mb Half Duplex? */
354 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
355 DEBUGOUT("Advertise 100mb Half duplex\n");
356 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
357 }
358
359 /* Do we want to advertise 100 Mb Full Duplex? */
360 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
361 DEBUGOUT("Advertise 100mb Full duplex\n");
362 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
363 }
364
365 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
366 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
367 DEBUGOUT("Advertise 1000mb Half duplex request denied!\n");
368
369 /* Do we want to advertise 1000 Mb Full Duplex? */
370 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
371 DEBUGOUT("Advertise 1000mb Full duplex\n");
372 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
373 }
374
375 /* We do not allow the Phy to advertise 2500 Mb Half Duplex */
376 if (phy->autoneg_advertised & ADVERTISE_2500_HALF)
377 DEBUGOUT("Advertise 2500mb Half duplex request denied!\n");
378
379 /* Do we want to advertise 2500 Mb Full Duplex? */
380 if (phy->autoneg_advertised & ADVERTISE_2500_FULL) {
381 DEBUGOUT("Advertise 2500mb Full duplex\n");
382 aneg_multigbt_an_ctrl |= CR_2500T_FD_CAPS;
383 } else {
384 aneg_multigbt_an_ctrl &= ~CR_2500T_FD_CAPS;
385 }
386
387 /* Check for a software override of the flow control settings, and
388 * setup the PHY advertisement registers accordingly. If
389 * auto-negotiation is enabled, then software will have to set the
390 * "PAUSE" bits to the correct value in the Auto-Negotiation
391 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
392 * negotiation.
393 *
394 * The possible values of the "fc" parameter are:
395 * 0: Flow control is completely disabled
396 * 1: Rx flow control is enabled (we can receive pause frames
397 * but not send pause frames).
398 * 2: Tx flow control is enabled (we can send pause frames
399 * but we do not support receiving pause frames).
400 * 3: Both Rx and Tx flow control (symmetric) are enabled.
401 * other: No software override. The flow control configuration
402 * in the EEPROM is used.
403 */
404 switch (hw->fc.current_mode) {
405 case igc_fc_none:
406 /* Flow control (Rx & Tx) is completely disabled by a
407 * software over-ride.
408 */
409 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
410 break;
411 case igc_fc_rx_pause:
412 /* Rx Flow control is enabled, and Tx Flow control is
413 * disabled, by a software over-ride.
414 *
415 * Since there really isn't a way to advertise that we are
416 * capable of Rx Pause ONLY, we will advertise that we
417 * support both symmetric and asymmetric Rx PAUSE. Later
418 * (in igc_config_fc_after_link_up) we will disable the
419 * hw's ability to send PAUSE frames.
420 */
421 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
422 break;
423 case igc_fc_tx_pause:
424 /* Tx Flow control is enabled, and Rx Flow control is
425 * disabled, by a software over-ride.
426 */
427 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
428 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
429 break;
430 case igc_fc_full:
431 /* Flow control (both Rx and Tx) is enabled by a software
432 * over-ride.
433 */
434 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
435 break;
436 default:
437 DEBUGOUT("Flow control param set incorrectly\n");
438 return -IGC_ERR_CONFIG;
439 }
440
441 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
442 if (ret_val)
443 return ret_val;
444
445 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
446
447 if (phy->autoneg_mask & ADVERTISE_1000_FULL)
448 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL,
449 mii_1000t_ctrl_reg);
450
451 if (phy->autoneg_mask & ADVERTISE_2500_FULL)
452 ret_val = phy->ops.write_reg(hw,
453 (STANDARD_AN_REG_MASK <<
454 MMD_DEVADDR_SHIFT) |
455 ANEG_MULTIGBT_AN_CTRL,
456 aneg_multigbt_an_ctrl);
457
458 return ret_val;
459 }
460
461 /**
462 * igc_copper_link_autoneg - Setup/Enable autoneg for copper link
463 * @hw: pointer to the HW structure
464 *
465 * Performs initial bounds checking on autoneg advertisement parameter, then
466 * configure to advertise the full capability. Setup the PHY to autoneg
467 * and restart the negotiation process between the link partner. If
468 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
469 **/
igc_copper_link_autoneg(struct igc_hw * hw)470 static s32 igc_copper_link_autoneg(struct igc_hw *hw)
471 {
472 struct igc_phy_info *phy = &hw->phy;
473 s32 ret_val;
474 u16 phy_ctrl;
475
476 DEBUGFUNC("igc_copper_link_autoneg");
477
478 /* Perform some bounds checking on the autoneg advertisement
479 * parameter.
480 */
481 phy->autoneg_advertised &= phy->autoneg_mask;
482
483 /* If autoneg_advertised is zero, we assume it was not defaulted
484 * by the calling code so we set to advertise full capability.
485 */
486 if (!phy->autoneg_advertised)
487 phy->autoneg_advertised = phy->autoneg_mask;
488
489 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
490 ret_val = igc_phy_setup_autoneg(hw);
491 if (ret_val) {
492 DEBUGOUT("Error Setting up Auto-Negotiation\n");
493 return ret_val;
494 }
495 DEBUGOUT("Restarting Auto-Neg\n");
496
497 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
498 * the Auto Neg Restart bit in the PHY control register.
499 */
500 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
501 if (ret_val)
502 return ret_val;
503
504 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
505 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
506 if (ret_val)
507 return ret_val;
508
509 /* Does the user want to wait for Auto-Neg to complete here, or
510 * check at a later time (for example, callback routine).
511 */
512 if (phy->autoneg_wait_to_complete) {
513 ret_val = igc_wait_autoneg(hw);
514 if (ret_val) {
515 DEBUGOUT("Error while waiting for autoneg to complete\n");
516 return ret_val;
517 }
518 }
519
520 hw->mac.get_link_status = true;
521
522 return ret_val;
523 }
524
525 /**
526 * igc_setup_copper_link_generic - Configure copper link settings
527 * @hw: pointer to the HW structure
528 *
529 * Calls the appropriate function to configure the link for auto-neg or forced
530 * speed and duplex. Then we check for link, once link is established calls
531 * to configure collision distance and flow control are called. If link is
532 * not established, we return -IGC_ERR_PHY (-2).
533 **/
igc_setup_copper_link_generic(struct igc_hw * hw)534 s32 igc_setup_copper_link_generic(struct igc_hw *hw)
535 {
536 s32 ret_val;
537 bool link;
538
539 DEBUGFUNC("igc_setup_copper_link_generic");
540
541 if (hw->mac.autoneg) {
542 /* Setup autoneg and flow control advertisement and perform
543 * autonegotiation.
544 */
545 ret_val = igc_copper_link_autoneg(hw);
546 if (ret_val)
547 return ret_val;
548 } else {
549 /* PHY will be set to 10H, 10F, 100H or 100F
550 * depending on user settings.
551 */
552 DEBUGOUT("Forcing Speed and Duplex\n");
553 ret_val = hw->phy.ops.force_speed_duplex(hw);
554 if (ret_val) {
555 DEBUGOUT("Error Forcing Speed and Duplex\n");
556 return ret_val;
557 }
558 }
559
560 /* Check link status. Wait up to 100 microseconds for link to become
561 * valid.
562 */
563 ret_val = igc_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,
564 &link);
565 if (ret_val)
566 return ret_val;
567
568 if (link) {
569 DEBUGOUT("Valid link established!!!\n");
570 hw->mac.ops.config_collision_dist(hw);
571 ret_val = igc_config_fc_after_link_up_generic(hw);
572 } else {
573 DEBUGOUT("Unable to establish link!!!\n");
574 }
575
576 return ret_val;
577 }
578
579 /**
580 * igc_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
581 * @hw: pointer to the HW structure
582 * @phy_ctrl: pointer to current value of PHY_CONTROL
583 *
584 * Forces speed and duplex on the PHY by doing the following: disable flow
585 * control, force speed/duplex on the MAC, disable auto speed detection,
586 * disable auto-negotiation, configure duplex, configure speed, configure
587 * the collision distance, write configuration to CTRL register. The
588 * caller must write to the PHY_CONTROL register for these settings to
589 * take effect.
590 **/
igc_phy_force_speed_duplex_setup(struct igc_hw * hw,u16 * phy_ctrl)591 void igc_phy_force_speed_duplex_setup(struct igc_hw *hw, u16 *phy_ctrl)
592 {
593 struct igc_mac_info *mac = &hw->mac;
594 u32 ctrl;
595
596 DEBUGFUNC("igc_phy_force_speed_duplex_setup");
597
598 /* Turn off flow control when forcing speed/duplex */
599 hw->fc.current_mode = igc_fc_none;
600
601 /* Force speed/duplex on the mac */
602 ctrl = IGC_READ_REG(hw, IGC_CTRL);
603 ctrl |= (IGC_CTRL_FRCSPD | IGC_CTRL_FRCDPX);
604 ctrl &= ~IGC_CTRL_SPD_SEL;
605
606 /* Disable Auto Speed Detection */
607 ctrl &= ~IGC_CTRL_ASDE;
608
609 /* Disable autoneg on the phy */
610 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
611
612 /* Forcing Full or Half Duplex? */
613 if (mac->forced_speed_duplex & IGC_ALL_HALF_DUPLEX) {
614 ctrl &= ~IGC_CTRL_FD;
615 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
616 DEBUGOUT("Half Duplex\n");
617 } else {
618 ctrl |= IGC_CTRL_FD;
619 *phy_ctrl |= MII_CR_FULL_DUPLEX;
620 DEBUGOUT("Full Duplex\n");
621 }
622
623 /* Forcing 10mb or 100mb? */
624 if (mac->forced_speed_duplex & IGC_ALL_100_SPEED) {
625 ctrl |= IGC_CTRL_SPD_100;
626 *phy_ctrl |= MII_CR_SPEED_100;
627 *phy_ctrl &= ~MII_CR_SPEED_1000;
628 DEBUGOUT("Forcing 100mb\n");
629 } else {
630 ctrl &= ~(IGC_CTRL_SPD_1000 | IGC_CTRL_SPD_100);
631 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
632 DEBUGOUT("Forcing 10mb\n");
633 }
634
635 hw->mac.ops.config_collision_dist(hw);
636
637 IGC_WRITE_REG(hw, IGC_CTRL, ctrl);
638 }
639
640 /**
641 * igc_set_d3_lplu_state_generic - Sets low power link up state for D3
642 * @hw: pointer to the HW structure
643 * @active: boolean used to enable/disable lplu
644 *
645 * Success returns 0, Failure returns 1
646 *
647 * The low power link up (lplu) state is set to the power management level D3
648 * and SmartSpeed is disabled when active is true, else clear lplu for D3
649 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
650 * is used during Dx states where the power conservation is most important.
651 * During driver activity, SmartSpeed should be enabled so performance is
652 * maintained.
653 **/
igc_set_d3_lplu_state_generic(struct igc_hw * hw,bool active)654 s32 igc_set_d3_lplu_state_generic(struct igc_hw *hw, bool active)
655 {
656 struct igc_phy_info *phy = &hw->phy;
657 s32 ret_val;
658 u16 data;
659
660 DEBUGFUNC("igc_set_d3_lplu_state_generic");
661
662 if (!hw->phy.ops.read_reg)
663 return IGC_SUCCESS;
664
665 ret_val = phy->ops.read_reg(hw, IGP02IGC_PHY_POWER_MGMT, &data);
666 if (ret_val)
667 return ret_val;
668
669 if (!active) {
670 data &= ~IGP02IGC_PM_D3_LPLU;
671 ret_val = phy->ops.write_reg(hw, IGP02IGC_PHY_POWER_MGMT,
672 data);
673 if (ret_val)
674 return ret_val;
675 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
676 * during Dx states where the power conservation is most
677 * important. During driver activity we should enable
678 * SmartSpeed, so performance is maintained.
679 */
680 if (phy->smart_speed == igc_smart_speed_on) {
681 ret_val = phy->ops.read_reg(hw,
682 IGP01IGC_PHY_PORT_CONFIG,
683 &data);
684 if (ret_val)
685 return ret_val;
686
687 data |= IGP01IGC_PSCFR_SMART_SPEED;
688 ret_val = phy->ops.write_reg(hw,
689 IGP01IGC_PHY_PORT_CONFIG,
690 data);
691 if (ret_val)
692 return ret_val;
693 } else if (phy->smart_speed == igc_smart_speed_off) {
694 ret_val = phy->ops.read_reg(hw,
695 IGP01IGC_PHY_PORT_CONFIG,
696 &data);
697 if (ret_val)
698 return ret_val;
699
700 data &= ~IGP01IGC_PSCFR_SMART_SPEED;
701 ret_val = phy->ops.write_reg(hw,
702 IGP01IGC_PHY_PORT_CONFIG,
703 data);
704 if (ret_val)
705 return ret_val;
706 }
707 } else if ((phy->autoneg_advertised == IGC_ALL_SPEED_DUPLEX) ||
708 (phy->autoneg_advertised == IGC_ALL_NOT_GIG) ||
709 (phy->autoneg_advertised == IGC_ALL_10_SPEED)) {
710 data |= IGP02IGC_PM_D3_LPLU;
711 ret_val = phy->ops.write_reg(hw, IGP02IGC_PHY_POWER_MGMT,
712 data);
713 if (ret_val)
714 return ret_val;
715
716 /* When LPLU is enabled, we should disable SmartSpeed */
717 ret_val = phy->ops.read_reg(hw, IGP01IGC_PHY_PORT_CONFIG,
718 &data);
719 if (ret_val)
720 return ret_val;
721
722 data &= ~IGP01IGC_PSCFR_SMART_SPEED;
723 ret_val = phy->ops.write_reg(hw, IGP01IGC_PHY_PORT_CONFIG,
724 data);
725 }
726
727 return ret_val;
728 }
729
730 /**
731 * igc_check_downshift_generic - Checks whether a downshift in speed occurred
732 * @hw: pointer to the HW structure
733 *
734 * Success returns 0, Failure returns 1
735 *
736 * A downshift is detected by querying the PHY link health.
737 **/
igc_check_downshift_generic(struct igc_hw * hw)738 s32 igc_check_downshift_generic(struct igc_hw *hw)
739 {
740 struct igc_phy_info *phy = &hw->phy;
741 s32 ret_val;
742
743 DEBUGFUNC("igc_check_downshift_generic");
744
745 switch (phy->type) {
746 case igc_phy_i225:
747 default:
748 /* speed downshift not supported */
749 phy->speed_downgraded = false;
750 return IGC_SUCCESS;
751 }
752
753 return ret_val;
754 }
755
756 /**
757 * igc_wait_autoneg - Wait for auto-neg completion
758 * @hw: pointer to the HW structure
759 *
760 * Waits for auto-negotiation to complete or for the auto-negotiation time
761 * limit to expire, which ever happens first.
762 **/
igc_wait_autoneg(struct igc_hw * hw)763 static s32 igc_wait_autoneg(struct igc_hw *hw)
764 {
765 s32 ret_val = IGC_SUCCESS;
766 u16 i, phy_status;
767
768 DEBUGFUNC("igc_wait_autoneg");
769
770 if (!hw->phy.ops.read_reg)
771 return IGC_SUCCESS;
772
773 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
774 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
775 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
776 if (ret_val)
777 break;
778 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
779 if (ret_val)
780 break;
781 if (phy_status & MII_SR_AUTONEG_COMPLETE)
782 break;
783 msec_delay(100);
784 }
785
786 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
787 * has completed.
788 */
789 return ret_val;
790 }
791
792 /**
793 * igc_phy_has_link_generic - Polls PHY for link
794 * @hw: pointer to the HW structure
795 * @iterations: number of times to poll for link
796 * @usec_interval: delay between polling attempts
797 * @success: pointer to whether polling was successful or not
798 *
799 * Polls the PHY status register for link, 'iterations' number of times.
800 **/
igc_phy_has_link_generic(struct igc_hw * hw,u32 iterations,u32 usec_interval,bool * success)801 s32 igc_phy_has_link_generic(struct igc_hw *hw, u32 iterations,
802 u32 usec_interval, bool *success)
803 {
804 s32 ret_val = IGC_SUCCESS;
805 u16 i, phy_status;
806
807 DEBUGFUNC("igc_phy_has_link_generic");
808
809 if (!hw->phy.ops.read_reg)
810 return IGC_SUCCESS;
811
812 for (i = 0; i < iterations; i++) {
813 /* Some PHYs require the PHY_STATUS register to be read
814 * twice due to the link bit being sticky. No harm doing
815 * it across the board.
816 */
817 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
818 if (ret_val) {
819 /* If the first read fails, another entity may have
820 * ownership of the resources, wait and try again to
821 * see if they have relinquished the resources yet.
822 */
823 if (usec_interval >= 1000)
824 msec_delay(usec_interval/1000);
825 else
826 usec_delay(usec_interval);
827 }
828 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
829 if (ret_val)
830 break;
831 if (phy_status & MII_SR_LINK_STATUS)
832 break;
833 if (usec_interval >= 1000)
834 msec_delay(usec_interval/1000);
835 else
836 usec_delay(usec_interval);
837 }
838
839 *success = (i < iterations);
840
841 return ret_val;
842 }
843
844 /**
845 * igc_phy_hw_reset_generic - PHY hardware reset
846 * @hw: pointer to the HW structure
847 *
848 * Verify the reset block is not blocking us from resetting. Acquire
849 * semaphore (if necessary) and read/set/write the device control reset
850 * bit in the PHY. Wait the appropriate delay time for the device to
851 * reset and release the semaphore (if necessary).
852 **/
igc_phy_hw_reset_generic(struct igc_hw * hw)853 s32 igc_phy_hw_reset_generic(struct igc_hw *hw)
854 {
855 struct igc_phy_info *phy = &hw->phy;
856 s32 ret_val;
857 u32 ctrl, timeout = 10000, phpm = 0;
858
859 DEBUGFUNC("igc_phy_hw_reset_generic");
860
861 if (phy->ops.check_reset_block) {
862 ret_val = phy->ops.check_reset_block(hw);
863 if (ret_val)
864 return IGC_SUCCESS;
865 }
866
867 ret_val = phy->ops.acquire(hw);
868 if (ret_val)
869 return ret_val;
870
871 phpm = IGC_READ_REG(hw, IGC_I225_PHPM);
872
873 ctrl = IGC_READ_REG(hw, IGC_CTRL);
874 IGC_WRITE_REG(hw, IGC_CTRL, ctrl | IGC_CTRL_PHY_RST);
875 IGC_WRITE_FLUSH(hw);
876
877 usec_delay(phy->reset_delay_us);
878
879 IGC_WRITE_REG(hw, IGC_CTRL, ctrl);
880 IGC_WRITE_FLUSH(hw);
881
882 usec_delay(150);
883
884 do {
885 phpm = IGC_READ_REG(hw, IGC_I225_PHPM);
886 timeout--;
887 usec_delay(1);
888 } while (!(phpm & IGC_I225_PHPM_RST_COMPL) && timeout);
889
890 if (!timeout)
891 DEBUGOUT("Timeout expired after a phy reset\n");
892
893 phy->ops.release(hw);
894
895 return ret_val;
896 }
897
898 /**
899 * igc_power_up_phy_copper - Restore copper link in case of PHY power down
900 * @hw: pointer to the HW structure
901 *
902 * In the case of a PHY power down to save power, or to turn off link during a
903 * driver unload, or wake on lan is not enabled, restore the link to previous
904 * settings.
905 **/
igc_power_up_phy_copper(struct igc_hw * hw)906 void igc_power_up_phy_copper(struct igc_hw *hw)
907 {
908 u16 mii_reg = 0;
909
910 /* The PHY will retain its settings across a power down/up cycle */
911 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
912 mii_reg &= ~MII_CR_POWER_DOWN;
913 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
914 usec_delay(300);
915 }
916
917 /**
918 * igc_power_down_phy_copper - Restore copper link in case of PHY power down
919 * @hw: pointer to the HW structure
920 *
921 * In the case of a PHY power down to save power, or to turn off link during a
922 * driver unload, or wake on lan is not enabled, restore the link to previous
923 * settings.
924 **/
igc_power_down_phy_copper(struct igc_hw * hw)925 void igc_power_down_phy_copper(struct igc_hw *hw)
926 {
927 u16 mii_reg = 0;
928
929 /* The PHY will retain its settings across a power down/up cycle */
930 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
931 mii_reg |= MII_CR_POWER_DOWN;
932 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
933 msec_delay(1);
934 }
935 /**
936 * igc_write_phy_reg_gpy - Write GPY PHY register
937 * @hw: pointer to the HW structure
938 * @offset: register offset to write to
939 * @data: data to write at register offset
940 *
941 * Acquires semaphore, if necessary, then writes the data to PHY register
942 * at the offset. Release any acquired semaphores before exiting.
943 **/
igc_write_phy_reg_gpy(struct igc_hw * hw,u32 offset,u16 data)944 s32 igc_write_phy_reg_gpy(struct igc_hw *hw, u32 offset, u16 data)
945 {
946 s32 ret_val;
947 u8 dev_addr = (offset & GPY_MMD_MASK) >> GPY_MMD_SHIFT;
948
949 DEBUGFUNC("igc_write_phy_reg_gpy");
950
951 offset = offset & GPY_REG_MASK;
952
953 if (!dev_addr) {
954 ret_val = hw->phy.ops.acquire(hw);
955 if (ret_val)
956 return ret_val;
957 ret_val = igc_write_phy_reg_mdic(hw, offset, data);
958 if (ret_val)
959 return ret_val;
960 hw->phy.ops.release(hw);
961 } else {
962 ret_val = igc_write_xmdio_reg(hw, (u16)offset, dev_addr,
963 data);
964 }
965 return ret_val;
966 }
967
968 /**
969 * igc_read_phy_reg_gpy - Read GPY PHY register
970 * @hw: pointer to the HW structure
971 * @offset: lower half is register offset to read to
972 * upper half is MMD to use.
973 * @data: data to read at register offset
974 *
975 * Acquires semaphore, if necessary, then reads the data in the PHY register
976 * at the offset. Release any acquired semaphores before exiting.
977 **/
igc_read_phy_reg_gpy(struct igc_hw * hw,u32 offset,u16 * data)978 s32 igc_read_phy_reg_gpy(struct igc_hw *hw, u32 offset, u16 *data)
979 {
980 s32 ret_val;
981 u8 dev_addr = (offset & GPY_MMD_MASK) >> GPY_MMD_SHIFT;
982
983 DEBUGFUNC("igc_read_phy_reg_gpy");
984
985 offset = offset & GPY_REG_MASK;
986
987 if (!dev_addr) {
988 ret_val = hw->phy.ops.acquire(hw);
989 if (ret_val)
990 return ret_val;
991 ret_val = igc_read_phy_reg_mdic(hw, offset, data);
992 if (ret_val)
993 return ret_val;
994 hw->phy.ops.release(hw);
995 } else {
996 ret_val = igc_read_xmdio_reg(hw, (u16)offset, dev_addr,
997 data);
998 }
999 return ret_val;
1000 }
1001
1002
1003 /**
1004 * __igc_access_xmdio_reg - Read/write XMDIO register
1005 * @hw: pointer to the HW structure
1006 * @address: XMDIO address to program
1007 * @dev_addr: device address to program
1008 * @data: pointer to value to read/write from/to the XMDIO address
1009 * @read: boolean flag to indicate read or write
1010 **/
__igc_access_xmdio_reg(struct igc_hw * hw,u16 address,u8 dev_addr,u16 * data,bool read)1011 static s32 __igc_access_xmdio_reg(struct igc_hw *hw, u16 address,
1012 u8 dev_addr, u16 *data, bool read)
1013 {
1014 s32 ret_val;
1015
1016 DEBUGFUNC("__igc_access_xmdio_reg");
1017
1018 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, dev_addr);
1019 if (ret_val)
1020 return ret_val;
1021
1022 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAAD, address);
1023 if (ret_val)
1024 return ret_val;
1025
1026 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, IGC_MMDAC_FUNC_DATA |
1027 dev_addr);
1028 if (ret_val)
1029 return ret_val;
1030
1031 if (read)
1032 ret_val = hw->phy.ops.read_reg(hw, IGC_MMDAAD, data);
1033 else
1034 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAAD, *data);
1035 if (ret_val)
1036 return ret_val;
1037
1038 /* Recalibrate the device back to 0 */
1039 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, 0);
1040 if (ret_val)
1041 return ret_val;
1042
1043 return ret_val;
1044 }
1045
1046 /**
1047 * igc_read_xmdio_reg - Read XMDIO register
1048 * @hw: pointer to the HW structure
1049 * @addr: XMDIO address to program
1050 * @dev_addr: device address to program
1051 * @data: value to be read from the EMI address
1052 **/
igc_read_xmdio_reg(struct igc_hw * hw,u16 addr,u8 dev_addr,u16 * data)1053 s32 igc_read_xmdio_reg(struct igc_hw *hw, u16 addr, u8 dev_addr, u16 *data)
1054 {
1055 DEBUGFUNC("igc_read_xmdio_reg");
1056
1057 return __igc_access_xmdio_reg(hw, addr, dev_addr, data, true);
1058 }
1059
1060 /**
1061 * igc_write_xmdio_reg - Write XMDIO register
1062 * @hw: pointer to the HW structure
1063 * @addr: XMDIO address to program
1064 * @dev_addr: device address to program
1065 * @data: value to be written to the XMDIO address
1066 **/
igc_write_xmdio_reg(struct igc_hw * hw,u16 addr,u8 dev_addr,u16 data)1067 s32 igc_write_xmdio_reg(struct igc_hw *hw, u16 addr, u8 dev_addr, u16 data)
1068 {
1069 DEBUGFUNC("igc_write_xmdio_reg");
1070
1071 return __igc_access_xmdio_reg(hw, addr, dev_addr, &data, false);
1072 }
1073