1 /* $OpenBSD: igc_mac.c,v 1.1 2021/10/31 14:52:57 patrick Exp $ */
2 /*-
3 * Copyright 2021 Intel Corp
4 * Copyright 2021 Rubicon Communications, LLC (Netgate)
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include <dev/pci/igc_api.h>
9
10 /**
11 * igc_init_mac_ops_generic - Initialize MAC function pointers
12 * @hw: pointer to the HW structure
13 *
14 * Setups up the function pointers to no-op functions
15 **/
16 void
igc_init_mac_ops_generic(struct igc_hw * hw)17 igc_init_mac_ops_generic(struct igc_hw *hw)
18 {
19 struct igc_mac_info *mac = &hw->mac;
20 DEBUGFUNC("igc_init_mac_ops_generic");
21
22 /* General Setup */
23 mac->ops.init_params = igc_null_ops_generic;
24 mac->ops.config_collision_dist = igc_config_collision_dist_generic;
25 mac->ops.rar_set = igc_rar_set_generic;
26 }
27
28 /**
29 * igc_null_ops_generic - No-op function, returns 0
30 * @hw: pointer to the HW structure
31 **/
32 int
igc_null_ops_generic(struct igc_hw IGC_UNUSEDARG * hw)33 igc_null_ops_generic(struct igc_hw IGC_UNUSEDARG *hw)
34 {
35 DEBUGFUNC("igc_null_ops_generic");
36 return IGC_SUCCESS;
37 }
38
39 /**
40 * igc_write_vfta_generic - Write value to VLAN filter table
41 * @hw: pointer to the HW structure
42 * @offset: register offset in VLAN filter table
43 * @value: register value written to VLAN filter table
44 *
45 * Writes value at the given offset in the register array which stores
46 * the VLAN filter table.
47 **/
48 void
igc_write_vfta_generic(struct igc_hw * hw,uint32_t offset,uint32_t value)49 igc_write_vfta_generic(struct igc_hw *hw, uint32_t offset, uint32_t value)
50 {
51 DEBUGFUNC("igc_write_vfta_generic");
52
53 IGC_WRITE_REG_ARRAY(hw, IGC_VFTA, offset, value);
54 IGC_WRITE_FLUSH(hw);
55 }
56
57 /**
58 * igc_init_rx_addrs_generic - Initialize receive address's
59 * @hw: pointer to the HW structure
60 * @rar_count: receive address registers
61 *
62 * Setup the receive address registers by setting the base receive address
63 * register to the devices MAC address and clearing all the other receive
64 * address registers to 0.
65 **/
66 void
igc_init_rx_addrs_generic(struct igc_hw * hw,uint16_t rar_count)67 igc_init_rx_addrs_generic(struct igc_hw *hw, uint16_t rar_count)
68 {
69 uint32_t i;
70 uint8_t mac_addr[ETHER_ADDR_LEN] = {0};
71
72 DEBUGFUNC("igc_init_rx_addrs_generic");
73
74 /* Setup the receive address */
75 DEBUGOUT("Programming MAC Address into RAR[0]\n");
76
77 hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
78
79 /* Zero out the other (rar_entry_count - 1) receive addresses */
80 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1);
81 for (i = 1; i < rar_count; i++)
82 hw->mac.ops.rar_set(hw, mac_addr, i);
83 }
84
85 /**
86 * igc_check_alt_mac_addr_generic - Check for alternate MAC addr
87 * @hw: pointer to the HW structure
88 *
89 * Checks the nvm for an alternate MAC address. An alternate MAC address
90 * can be setup by pre-boot software and must be treated like a permanent
91 * address and must override the actual permanent MAC address. If an
92 * alternate MAC address is found it is programmed into RAR0, replacing
93 * the permanent address that was installed into RAR0 by the Si on reset.
94 * This function will return SUCCESS unless it encounters an error while
95 * reading the EEPROM.
96 **/
97 int
igc_check_alt_mac_addr_generic(struct igc_hw * hw)98 igc_check_alt_mac_addr_generic(struct igc_hw *hw)
99 {
100 uint32_t i;
101 int ret_val;
102 uint16_t offset, nvm_alt_mac_addr_offset, nvm_data;
103 uint8_t alt_mac_addr[ETHER_ADDR_LEN];
104
105 DEBUGFUNC("igc_check_alt_mac_addr_generic");
106
107 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &nvm_data);
108 if (ret_val)
109 return ret_val;
110
111 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1,
112 &nvm_alt_mac_addr_offset);
113 if (ret_val) {
114 DEBUGOUT("NVM Read Error\n");
115 return ret_val;
116 }
117
118 if ((nvm_alt_mac_addr_offset == 0xFFFF) ||
119 (nvm_alt_mac_addr_offset == 0x0000))
120 /* There is no Alternate MAC Address */
121 return IGC_SUCCESS;
122
123 if (hw->bus.func == IGC_FUNC_1)
124 nvm_alt_mac_addr_offset += IGC_ALT_MAC_ADDRESS_OFFSET_LAN1;
125 for (i = 0; i < ETHER_ADDR_LEN; i += 2) {
126 offset = nvm_alt_mac_addr_offset + (i >> 1);
127 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
128 if (ret_val) {
129 DEBUGOUT("NVM Read Error\n");
130 return ret_val;
131 }
132
133 alt_mac_addr[i] = (uint8_t)(nvm_data & 0xFF);
134 alt_mac_addr[i + 1] = (uint8_t)(nvm_data >> 8);
135 }
136
137 /* if multicast bit is set, the alternate address will not be used */
138 if (alt_mac_addr[0] & 0x01) {
139 DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n");
140 return IGC_SUCCESS;
141 }
142
143 /* We have a valid alternate MAC address, and we want to treat it the
144 * same as the normal permanent MAC address stored by the HW into the
145 * RAR. Do this by mapping this address into RAR0.
146 */
147 hw->mac.ops.rar_set(hw, alt_mac_addr, 0);
148
149 return IGC_SUCCESS;
150 }
151
152 /**
153 * igc_rar_set_generic - Set receive address register
154 * @hw: pointer to the HW structure
155 * @addr: pointer to the receive address
156 * @index: receive address array register
157 *
158 * Sets the receive address array register at index to the address passed
159 * in by addr.
160 **/
161 int
igc_rar_set_generic(struct igc_hw * hw,uint8_t * addr,uint32_t index)162 igc_rar_set_generic(struct igc_hw *hw, uint8_t *addr, uint32_t index)
163 {
164 uint32_t rar_low, rar_high;
165
166 DEBUGFUNC("igc_rar_set_generic");
167
168 /* HW expects these in little endian so we reverse the byte order
169 * from network order (big endian) to little endian
170 */
171 rar_low = ((uint32_t) addr[0] | ((uint32_t) addr[1] << 8) |
172 ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24));
173
174 rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8));
175
176 /* If MAC address zero, no need to set the AV bit */
177 if (rar_low || rar_high)
178 rar_high |= IGC_RAH_AV;
179
180 /* Some bridges will combine consecutive 32-bit writes into
181 * a single burst write, which will malfunction on some parts.
182 * The flushes avoid this.
183 */
184 IGC_WRITE_REG(hw, IGC_RAL(index), rar_low);
185 IGC_WRITE_FLUSH(hw);
186 IGC_WRITE_REG(hw, IGC_RAH(index), rar_high);
187 IGC_WRITE_FLUSH(hw);
188
189 return IGC_SUCCESS;
190 }
191
192 /**
193 * igc_hash_mc_addr_generic - Generate a multicast hash value
194 * @hw: pointer to the HW structure
195 * @mc_addr: pointer to a multicast address
196 *
197 * Generates a multicast address hash value which is used to determine
198 * the multicast filter table array address and new table value.
199 **/
200 int
igc_hash_mc_addr_generic(struct igc_hw * hw,uint8_t * mc_addr)201 igc_hash_mc_addr_generic(struct igc_hw *hw, uint8_t *mc_addr)
202 {
203 uint32_t hash_value, hash_mask;
204 uint8_t bit_shift = 0;
205
206 DEBUGFUNC("igc_hash_mc_addr_generic");
207
208 /* Register count multiplied by bits per register */
209 hash_mask = (hw->mac.mta_reg_count * 32) - 1;
210
211 /* For a mc_filter_type of 0, bit_shift is the number of left-shifts
212 * where 0xFF would still fall within the hash mask.
213 */
214 while (hash_mask >> bit_shift != 0xFF)
215 bit_shift++;
216
217 /* The portion of the address that is used for the hash table
218 * is determined by the mc_filter_type setting.
219 * The algorithm is such that there is a total of 8 bits of shifting.
220 * The bit_shift for a mc_filter_type of 0 represents the number of
221 * left-shifts where the MSB of mc_addr[5] would still fall within
222 * the hash_mask. Case 0 does this exactly. Since there are a total
223 * of 8 bits of shifting, then mc_addr[4] will shift right the
224 * remaining number of bits. Thus 8 - bit_shift. The rest of the
225 * cases are a variation of this algorithm...essentially raising the
226 * number of bits to shift mc_addr[5] left, while still keeping the
227 * 8-bit shifting total.
228 *
229 * For example, given the following Destination MAC Address and an
230 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
231 * we can see that the bit_shift for case 0 is 4. These are the hash
232 * values resulting from each mc_filter_type...
233 * [0] [1] [2] [3] [4] [5]
234 * 01 AA 00 12 34 56
235 * LSB MSB
236 *
237 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
238 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
239 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
240 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
241 */
242 switch (hw->mac.mc_filter_type) {
243 default:
244 case 0:
245 break;
246 case 1:
247 bit_shift += 1;
248 break;
249 case 2:
250 bit_shift += 2;
251 break;
252 case 3:
253 bit_shift += 4;
254 break;
255 }
256
257 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
258 (((uint16_t) mc_addr[5]) << bit_shift)));
259
260 return hash_value;
261 }
262
263 /**
264 * igc_update_mc_addr_list_generic - Update Multicast addresses
265 * @hw: pointer to the HW structure
266 * @mc_addr_list: array of multicast addresses to program
267 * @mc_addr_count: number of multicast addresses to program
268 *
269 * Updates entire Multicast Table Array.
270 * The caller must have a packed mc_addr_list of multicast addresses.
271 **/
272 void
igc_update_mc_addr_list_generic(struct igc_hw * hw,uint8_t * mc_addr_list,uint32_t mc_addr_count)273 igc_update_mc_addr_list_generic(struct igc_hw *hw, uint8_t *mc_addr_list,
274 uint32_t mc_addr_count)
275 {
276 uint32_t hash_value, hash_bit, hash_reg;
277 int i;
278
279 DEBUGFUNC("igc_update_mc_addr_list_generic");
280
281 /* clear mta_shadow */
282 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
283
284 /* update mta_shadow from mc_addr_list */
285 for (i = 0; (uint32_t)i < mc_addr_count; i++) {
286 hash_value = igc_hash_mc_addr_generic(hw, mc_addr_list);
287
288 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
289 hash_bit = hash_value & 0x1F;
290
291 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit);
292 mc_addr_list += (ETHER_ADDR_LEN);
293 }
294
295 /* replace the entire MTA table */
296 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)
297 IGC_WRITE_REG_ARRAY(hw, IGC_MTA, i, hw->mac.mta_shadow[i]);
298 IGC_WRITE_FLUSH(hw);
299 }
300
301 /**
302 * igc_clear_hw_cntrs_base_generic - Clear base hardware counters
303 * @hw: pointer to the HW structure
304 *
305 * Clears the base hardware counters by reading the counter registers.
306 **/
307 void
igc_clear_hw_cntrs_base_generic(struct igc_hw * hw)308 igc_clear_hw_cntrs_base_generic(struct igc_hw *hw)
309 {
310 DEBUGFUNC("igc_clear_hw_cntrs_base_generic");
311
312 IGC_READ_REG(hw, IGC_CRCERRS);
313 IGC_READ_REG(hw, IGC_MPC);
314 IGC_READ_REG(hw, IGC_SCC);
315 IGC_READ_REG(hw, IGC_ECOL);
316 IGC_READ_REG(hw, IGC_MCC);
317 IGC_READ_REG(hw, IGC_LATECOL);
318 IGC_READ_REG(hw, IGC_COLC);
319 IGC_READ_REG(hw, IGC_RERC);
320 IGC_READ_REG(hw, IGC_DC);
321 IGC_READ_REG(hw, IGC_RLEC);
322 IGC_READ_REG(hw, IGC_XONRXC);
323 IGC_READ_REG(hw, IGC_XONTXC);
324 IGC_READ_REG(hw, IGC_XOFFRXC);
325 IGC_READ_REG(hw, IGC_XOFFTXC);
326 IGC_READ_REG(hw, IGC_FCRUC);
327 IGC_READ_REG(hw, IGC_GPRC);
328 IGC_READ_REG(hw, IGC_BPRC);
329 IGC_READ_REG(hw, IGC_MPRC);
330 IGC_READ_REG(hw, IGC_GPTC);
331 IGC_READ_REG(hw, IGC_GORCL);
332 IGC_READ_REG(hw, IGC_GORCH);
333 IGC_READ_REG(hw, IGC_GOTCL);
334 IGC_READ_REG(hw, IGC_GOTCH);
335 IGC_READ_REG(hw, IGC_RNBC);
336 IGC_READ_REG(hw, IGC_RUC);
337 IGC_READ_REG(hw, IGC_RFC);
338 IGC_READ_REG(hw, IGC_ROC);
339 IGC_READ_REG(hw, IGC_RJC);
340 IGC_READ_REG(hw, IGC_TORL);
341 IGC_READ_REG(hw, IGC_TORH);
342 IGC_READ_REG(hw, IGC_TOTL);
343 IGC_READ_REG(hw, IGC_TOTH);
344 IGC_READ_REG(hw, IGC_TPR);
345 IGC_READ_REG(hw, IGC_TPT);
346 IGC_READ_REG(hw, IGC_MPTC);
347 IGC_READ_REG(hw, IGC_BPTC);
348 IGC_READ_REG(hw, IGC_TLPIC);
349 IGC_READ_REG(hw, IGC_RLPIC);
350 IGC_READ_REG(hw, IGC_RXDMTC);
351 }
352
353 /**
354 * igc_setup_link_generic - Setup flow control and link settings
355 * @hw: pointer to the HW structure
356 *
357 * Determines which flow control settings to use, then configures flow
358 * control. Calls the appropriate media-specific link configuration
359 * function. Assuming the adapter has a valid link partner, a valid link
360 * should be established. Assumes the hardware has previously been reset
361 * and the transmitter and receiver are not enabled.
362 **/
363 int
igc_setup_link_generic(struct igc_hw * hw)364 igc_setup_link_generic(struct igc_hw *hw)
365 {
366 int ret_val;
367
368 DEBUGFUNC("igc_setup_link_generic");
369
370 /* In the case of the phy reset being blocked, we already have a link.
371 * We do not need to set it up again.
372 */
373 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))
374 return IGC_SUCCESS;
375
376 /* If requested flow control is set to default, set flow control
377 * for both 'rx' and 'tx' pause frames.
378 */
379 if (hw->fc.requested_mode == igc_fc_default) {
380 hw->fc.requested_mode = igc_fc_full;
381 }
382
383 /* Save off the requested flow control mode for use later. Depending
384 * on the link partner's capabilities, we may or may not use this mode.
385 */
386 hw->fc.current_mode = hw->fc.requested_mode;
387
388 DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
389 hw->fc.current_mode);
390
391 /* Call the necessary media_type subroutine to configure the link. */
392 ret_val = hw->mac.ops.setup_physical_interface(hw);
393 if (ret_val)
394 return ret_val;
395
396 /* Initialize the flow control address, type, and PAUSE timer
397 * registers to their default values. This is done even if flow
398 * control is disabled, because it does not hurt anything to
399 * initialize these registers.
400 */
401 IGC_WRITE_REG(hw, IGC_FCT, FLOW_CONTROL_TYPE);
402 IGC_WRITE_REG(hw, IGC_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
403 IGC_WRITE_REG(hw, IGC_FCAL, FLOW_CONTROL_ADDRESS_LOW);
404
405 IGC_WRITE_REG(hw, IGC_FCTTV, hw->fc.pause_time);
406
407 return igc_set_fc_watermarks_generic(hw);
408 }
409
410 /**
411 * igc_config_collision_dist_generic - Configure collision distance
412 * @hw: pointer to the HW structure
413 *
414 * Configures the collision distance to the default value and is used
415 * during link setup.
416 **/
417 void
igc_config_collision_dist_generic(struct igc_hw * hw)418 igc_config_collision_dist_generic(struct igc_hw *hw)
419 {
420 uint32_t tctl;
421
422 DEBUGFUNC("igc_config_collision_dist_generic");
423
424 tctl = IGC_READ_REG(hw, IGC_TCTL);
425
426 tctl &= ~IGC_TCTL_COLD;
427 tctl |= IGC_COLLISION_DISTANCE << IGC_COLD_SHIFT;
428
429 IGC_WRITE_REG(hw, IGC_TCTL, tctl);
430 IGC_WRITE_FLUSH(hw);
431 }
432
433 /**
434 * igc_set_fc_watermarks_generic - Set flow control high/low watermarks
435 * @hw: pointer to the HW structure
436 *
437 * Sets the flow control high/low threshold (watermark) registers. If
438 * flow control XON frame transmission is enabled, then set XON frame
439 * transmission as well.
440 **/
441 int
igc_set_fc_watermarks_generic(struct igc_hw * hw)442 igc_set_fc_watermarks_generic(struct igc_hw *hw)
443 {
444 uint32_t fcrtl = 0, fcrth = 0;
445
446 DEBUGFUNC("igc_set_fc_watermarks_generic");
447
448 /* Set the flow control receive threshold registers. Normally,
449 * these registers will be set to a default threshold that may be
450 * adjusted later by the driver's runtime code. However, if the
451 * ability to transmit pause frames is not enabled, then these
452 * registers will be set to 0.
453 */
454 if (hw->fc.current_mode & igc_fc_tx_pause) {
455 /* We need to set up the Receive Threshold high and low water
456 * marks as well as (optionally) enabling the transmission of
457 * XON frames.
458 */
459 fcrtl = hw->fc.low_water;
460 if (hw->fc.send_xon)
461 fcrtl |= IGC_FCRTL_XONE;
462
463 fcrth = hw->fc.high_water;
464 }
465 IGC_WRITE_REG(hw, IGC_FCRTL, fcrtl);
466 IGC_WRITE_REG(hw, IGC_FCRTH, fcrth);
467
468 return IGC_SUCCESS;
469 }
470
471 /**
472 * igc_force_mac_fc_generic - Force the MAC's flow control settings
473 * @hw: pointer to the HW structure
474 *
475 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
476 * device control register to reflect the adapter settings. TFCE and RFCE
477 * need to be explicitly set by software when a copper PHY is used because
478 * autonegotiation is managed by the PHY rather than the MAC. Software must
479 * also configure these bits when link is forced on a fiber connection.
480 **/
481 int
igc_force_mac_fc_generic(struct igc_hw * hw)482 igc_force_mac_fc_generic(struct igc_hw *hw)
483 {
484 uint32_t ctrl;
485
486 DEBUGFUNC("igc_force_mac_fc_generic");
487
488 ctrl = IGC_READ_REG(hw, IGC_CTRL);
489
490 /* Because we didn't get link via the internal auto-negotiation
491 * mechanism (we either forced link or we got link via PHY
492 * auto-neg), we have to manually enable/disable transmit an
493 * receive flow control.
494 *
495 * The "Case" statement below enables/disable flow control
496 * according to the "hw->fc.current_mode" parameter.
497 *
498 * The possible values of the "fc" parameter are:
499 * 0: Flow control is completely disabled
500 * 1: Rx flow control is enabled (we can receive pause
501 * frames but not send pause frames).
502 * 2: Tx flow control is enabled (we can send pause frames
503 * frames but we do not receive pause frames).
504 * 3: Both Rx and Tx flow control (symmetric) is enabled.
505 * other: No other values should be possible at this point.
506 */
507 DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode);
508
509 switch (hw->fc.current_mode) {
510 case igc_fc_none:
511 ctrl &= (~(IGC_CTRL_TFCE | IGC_CTRL_RFCE));
512 break;
513 case igc_fc_rx_pause:
514 ctrl &= (~IGC_CTRL_TFCE);
515 ctrl |= IGC_CTRL_RFCE;
516 break;
517 case igc_fc_tx_pause:
518 ctrl &= (~IGC_CTRL_RFCE);
519 ctrl |= IGC_CTRL_TFCE;
520 break;
521 case igc_fc_full:
522 ctrl |= (IGC_CTRL_TFCE | IGC_CTRL_RFCE);
523 break;
524 default:
525 DEBUGOUT("Flow control param set incorrectly\n");
526 return -IGC_ERR_CONFIG;
527 }
528
529 IGC_WRITE_REG(hw, IGC_CTRL, ctrl);
530
531 return IGC_SUCCESS;
532 }
533
534 /**
535 * igc_config_fc_after_link_up_generic - Configures flow control after link
536 * @hw: pointer to the HW structure
537 *
538 * Checks the status of auto-negotiation after link up to ensure that the
539 * speed and duplex were not forced. If the link needed to be forced, then
540 * flow control needs to be forced also. If auto-negotiation is enabled
541 * and did not fail, then we configure flow control based on our link
542 * partner.
543 **/
544 int
igc_config_fc_after_link_up_generic(struct igc_hw * hw)545 igc_config_fc_after_link_up_generic(struct igc_hw *hw)
546 {
547 struct igc_mac_info *mac = &hw->mac;
548 uint16_t mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
549 uint16_t speed, duplex;
550 int ret_val = IGC_SUCCESS;
551
552 DEBUGFUNC("igc_config_fc_after_link_up_generic");
553
554 if (ret_val) {
555 DEBUGOUT("Error forcing flow control settings\n");
556 return ret_val;
557 }
558
559 /* Check for the case where we have copper media and auto-neg is
560 * enabled. In this case, we need to check and see if Auto-Neg
561 * has completed, and if so, how the PHY and link partner has
562 * flow control configured.
563 */
564 if (mac->autoneg) {
565 /* Read the MII Status Register and check to see if AutoNeg
566 * has completed. We read this twice because this reg has
567 * some "sticky" (latched) bits.
568 */
569 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
570 if (ret_val)
571 return ret_val;
572 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
573 if (ret_val)
574 return ret_val;
575
576 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE))
577 return ret_val;
578
579 /* The AutoNeg process has completed, so we now need to
580 * read both the Auto Negotiation Advertisement
581 * Register (Address 4) and the Auto_Negotiation Base
582 * Page Ability Register (Address 5) to determine how
583 * flow control was negotiated.
584 */
585 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV,
586 &mii_nway_adv_reg);
587 if (ret_val)
588 return ret_val;
589 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY,
590 &mii_nway_lp_ability_reg);
591 if (ret_val)
592 return ret_val;
593
594 /* Two bits in the Auto Negotiation Advertisement Register
595 * (Address 4) and two bits in the Auto Negotiation Base
596 * Page Ability Register (Address 5) determine flow control
597 * for both the PHY and the link partner. The following
598 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
599 * 1999, describes these PAUSE resolution bits and how flow
600 * control is determined based upon these settings.
601 * NOTE: DC = Don't Care
602 *
603 * LOCAL DEVICE | LINK PARTNER
604 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
605 *-------|---------|-------|---------|--------------------
606 * 0 | 0 | DC | DC | igc_fc_none
607 * 0 | 1 | 0 | DC | igc_fc_none
608 * 0 | 1 | 1 | 0 | igc_fc_none
609 * 0 | 1 | 1 | 1 | igc_fc_tx_pause
610 * 1 | 0 | 0 | DC | igc_fc_none
611 * 1 | DC | 1 | DC | igc_fc_full
612 * 1 | 1 | 0 | 0 | igc_fc_none
613 * 1 | 1 | 0 | 1 | igc_fc_rx_pause
614 *
615 * Are both PAUSE bits set to 1? If so, this implies
616 * Symmetric Flow Control is enabled at both ends. The
617 * ASM_DIR bits are irrelevant per the spec.
618 *
619 * For Symmetric Flow Control:
620 *
621 * LOCAL DEVICE | LINK PARTNER
622 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
623 *-------|---------|-------|---------|--------------------
624 * 1 | DC | 1 | DC | IGC_fc_full
625 *
626 */
627 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
628 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
629 /* Now we need to check if the user selected Rx ONLY
630 * of pause frames. In this case, we had to advertise
631 * FULL flow control because we could not advertise Rx
632 * ONLY. Hence, we must now check to see if we need to
633 * turn OFF the TRANSMISSION of PAUSE frames.
634 */
635 if (hw->fc.requested_mode == igc_fc_full)
636 hw->fc.current_mode = igc_fc_full;
637 else
638 hw->fc.current_mode = igc_fc_rx_pause;
639 }
640 /* For receiving PAUSE frames ONLY.
641 *
642 * LOCAL DEVICE | LINK PARTNER
643 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
644 *-------|---------|-------|---------|--------------------
645 * 0 | 1 | 1 | 1 | igc_fc_tx_pause
646 */
647 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
648 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
649 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
650 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
651 hw->fc.current_mode = igc_fc_tx_pause;
652 }
653 /* For transmitting PAUSE frames ONLY.
654 *
655 * LOCAL DEVICE | LINK PARTNER
656 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
657 *-------|---------|-------|---------|--------------------
658 * 1 | 1 | 0 | 1 | igc_fc_rx_pause
659 */
660 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
661 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
662 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
663 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
664 hw->fc.current_mode = igc_fc_rx_pause;
665 } else {
666 /* Per the IEEE spec, at this point flow control
667 * should be disabled.
668 */
669 hw->fc.current_mode = igc_fc_none;
670 DEBUGOUT("Flow Control = NONE.\n");
671 }
672
673 /* Now we need to do one last check... If we auto-
674 * negotiated to HALF DUPLEX, flow control should not be
675 * enabled per IEEE 802.3 spec.
676 */
677 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
678 if (ret_val) {
679 DEBUGOUT("Error getting link speed and duplex\n");
680 return ret_val;
681 }
682
683 if (duplex == HALF_DUPLEX)
684 hw->fc.current_mode = igc_fc_none;
685
686 /* Now we call a subroutine to actually force the MAC
687 * controller to use the correct flow control settings.
688 */
689 ret_val = igc_force_mac_fc_generic(hw);
690 if (ret_val) {
691 DEBUGOUT("Error forcing flow control settings\n");
692 return ret_val;
693 }
694 }
695
696 return IGC_SUCCESS;
697 }
698
699 /**
700 * igc_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex
701 * @hw: pointer to the HW structure
702 * @speed: stores the current speed
703 * @duplex: stores the current duplex
704 *
705 * Read the status register for the current speed/duplex and store the current
706 * speed and duplex for copper connections.
707 **/
708 int
igc_get_speed_and_duplex_copper_generic(struct igc_hw * hw,uint16_t * speed,uint16_t * duplex)709 igc_get_speed_and_duplex_copper_generic(struct igc_hw *hw, uint16_t *speed,
710 uint16_t *duplex)
711 {
712 uint32_t status;
713
714 DEBUGFUNC("igc_get_speed_and_duplex_copper_generic");
715
716 status = IGC_READ_REG(hw, IGC_STATUS);
717 if (status & IGC_STATUS_SPEED_1000) {
718 /* For I225, STATUS will indicate 1G speed in both 1 Gbps
719 * and 2.5 Gbps link modes. An additional bit is used
720 * to differentiate between 1 Gbps and 2.5 Gbps.
721 */
722 if ((hw->mac.type == igc_i225) &&
723 (status & IGC_STATUS_SPEED_2500)) {
724 *speed = SPEED_2500;
725 DEBUGOUT("2500 Mbs, ");
726 } else {
727 *speed = SPEED_1000;
728 DEBUGOUT("1000 Mbs, ");
729 }
730 } else if (status & IGC_STATUS_SPEED_100) {
731 *speed = SPEED_100;
732 DEBUGOUT("100 Mbs, ");
733 } else {
734 *speed = SPEED_10;
735 DEBUGOUT("10 Mbs, ");
736 }
737
738 if (status & IGC_STATUS_FD) {
739 *duplex = FULL_DUPLEX;
740 DEBUGOUT("Full Duplex\n");
741 } else {
742 *duplex = HALF_DUPLEX;
743 DEBUGOUT("Half Duplex\n");
744 }
745
746 return IGC_SUCCESS;
747 }
748
749 /**
750 * igc_put_hw_semaphore_generic - Release hardware semaphore
751 * @hw: pointer to the HW structure
752 *
753 * Release hardware semaphore used to access the PHY or NVM
754 **/
755 void
igc_put_hw_semaphore_generic(struct igc_hw * hw)756 igc_put_hw_semaphore_generic(struct igc_hw *hw)
757 {
758 uint32_t swsm;
759
760 DEBUGFUNC("igc_put_hw_semaphore_generic");
761
762 swsm = IGC_READ_REG(hw, IGC_SWSM);
763 swsm &= ~(IGC_SWSM_SMBI | IGC_SWSM_SWESMBI);
764
765 IGC_WRITE_REG(hw, IGC_SWSM, swsm);
766 }
767
768 /**
769 * igc_get_auto_rd_done_generic - Check for auto read completion
770 * @hw: pointer to the HW structure
771 *
772 * Check EEPROM for Auto Read done bit.
773 **/
774 int
igc_get_auto_rd_done_generic(struct igc_hw * hw)775 igc_get_auto_rd_done_generic(struct igc_hw *hw)
776 {
777 int i = 0;
778
779 DEBUGFUNC("igc_get_auto_rd_done_generic");
780
781 while (i < AUTO_READ_DONE_TIMEOUT) {
782 if (IGC_READ_REG(hw, IGC_EECD) & IGC_EECD_AUTO_RD)
783 break;
784 msec_delay(1);
785 i++;
786 }
787
788 if (i == AUTO_READ_DONE_TIMEOUT) {
789 DEBUGOUT("Auto read by HW from NVM has not completed.\n");
790 return -IGC_ERR_RESET;
791 }
792
793 return IGC_SUCCESS;
794 }
795
796 /**
797 * igc_disable_pcie_master_generic - Disables PCI-express master access
798 * @hw: pointer to the HW structure
799 *
800 * Returns IGC_SUCCESS if successful, else returns -10
801 * (-IGC_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
802 * the master requests to be disabled.
803 *
804 * Disables PCI-Express master access and verifies there are no pending
805 * requests.
806 **/
807 int
igc_disable_pcie_master_generic(struct igc_hw * hw)808 igc_disable_pcie_master_generic(struct igc_hw *hw)
809 {
810 uint32_t ctrl;
811 int timeout = MASTER_DISABLE_TIMEOUT;
812
813 DEBUGFUNC("igc_disable_pcie_master_generic");
814
815 ctrl = IGC_READ_REG(hw, IGC_CTRL);
816 ctrl |= IGC_CTRL_GIO_MASTER_DISABLE;
817 IGC_WRITE_REG(hw, IGC_CTRL, ctrl);
818
819 while (timeout) {
820 if (!(IGC_READ_REG(hw, IGC_STATUS) &
821 IGC_STATUS_GIO_MASTER_ENABLE))
822 break;
823 DELAY(100);
824 timeout--;
825 }
826
827 if (!timeout) {
828 DEBUGOUT("Master requests are pending.\n");
829 return -IGC_ERR_MASTER_REQUESTS_PENDING;
830 }
831
832 return IGC_SUCCESS;
833 }
834