1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24 #include <linux/firmware.h>
25 #include "i915_drv.h"
26 #include "i915_reg.h"
27
28 /**
29 * DOC: csr support for dmc
30 *
31 * Display Context Save and Restore (CSR) firmware support added from gen9
32 * onwards to drive newly added DMC (Display microcontroller) in display
33 * engine to save and restore the state of display engine when it enter into
34 * low-power state and comes back to normal.
35 */
36
37 #define I915_CSR_GLK "i915/glk_dmc_ver1_04.bin"
38 #define GLK_CSR_VERSION_REQUIRED CSR_VERSION(1, 4)
39
40 #define I915_CSR_CNL "i915/cnl_dmc_ver1_04.bin"
41 #define CNL_CSR_VERSION_REQUIRED CSR_VERSION(1, 4)
42
43 #define I915_CSR_KBL "i915/kbl_dmc_ver1_01.bin"
44 MODULE_FIRMWARE(I915_CSR_KBL);
45 #define KBL_CSR_VERSION_REQUIRED CSR_VERSION(1, 1)
46
47 #define I915_CSR_SKL "i915/skl_dmc_ver1_26.bin"
48 MODULE_FIRMWARE(I915_CSR_SKL);
49 #define SKL_CSR_VERSION_REQUIRED CSR_VERSION(1, 26)
50
51 #define I915_CSR_BXT "i915/bxt_dmc_ver1_07.bin"
52 MODULE_FIRMWARE(I915_CSR_BXT);
53 #define BXT_CSR_VERSION_REQUIRED CSR_VERSION(1, 7)
54
55
56 #define CSR_MAX_FW_SIZE 0x2FFF
57 #define CSR_DEFAULT_FW_OFFSET 0xFFFFFFFF
58
59 struct intel_css_header {
60 /* 0x09 for DMC */
61 uint32_t module_type;
62
63 /* Includes the DMC specific header in dwords */
64 uint32_t header_len;
65
66 /* always value would be 0x10000 */
67 uint32_t header_ver;
68
69 /* Not used */
70 uint32_t module_id;
71
72 /* Not used */
73 uint32_t module_vendor;
74
75 /* in YYYYMMDD format */
76 uint32_t date;
77
78 /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */
79 uint32_t size;
80
81 /* Not used */
82 uint32_t key_size;
83
84 /* Not used */
85 uint32_t modulus_size;
86
87 /* Not used */
88 uint32_t exponent_size;
89
90 /* Not used */
91 uint32_t reserved1[12];
92
93 /* Major Minor */
94 uint32_t version;
95
96 /* Not used */
97 uint32_t reserved2[8];
98
99 /* Not used */
100 uint32_t kernel_header_info;
101 } __packed;
102
103 struct intel_fw_info {
104 uint16_t reserved1;
105
106 /* Stepping (A, B, C, ..., *). * is a wildcard */
107 char stepping;
108
109 /* Sub-stepping (0, 1, ..., *). * is a wildcard */
110 char substepping;
111
112 uint32_t offset;
113 uint32_t reserved2;
114 } __packed;
115
116 struct intel_package_header {
117 /* DMC container header length in dwords */
118 unsigned char header_len;
119
120 /* always value would be 0x01 */
121 unsigned char header_ver;
122
123 unsigned char reserved[10];
124
125 /* Number of valid entries in the FWInfo array below */
126 uint32_t num_entries;
127
128 struct intel_fw_info fw_info[20];
129 } __packed;
130
131 struct intel_dmc_header {
132 /* always value would be 0x40403E3E */
133 uint32_t signature;
134
135 /* DMC binary header length */
136 unsigned char header_len;
137
138 /* 0x01 */
139 unsigned char header_ver;
140
141 /* Reserved */
142 uint16_t dmcc_ver;
143
144 /* Major, Minor */
145 uint32_t project;
146
147 /* Firmware program size (excluding header) in dwords */
148 uint32_t fw_size;
149
150 /* Major Minor version */
151 uint32_t fw_version;
152
153 /* Number of valid MMIO cycles present. */
154 uint32_t mmio_count;
155
156 /* MMIO address */
157 uint32_t mmioaddr[8];
158
159 /* MMIO data */
160 uint32_t mmiodata[8];
161
162 /* FW filename */
163 unsigned char dfile[32];
164
165 uint32_t reserved1[2];
166 } __packed;
167
168 struct stepping_info {
169 char stepping;
170 char substepping;
171 };
172
173 static const struct stepping_info skl_stepping_info[] = {
174 {'A', '0'}, {'B', '0'}, {'C', '0'},
175 {'D', '0'}, {'E', '0'}, {'F', '0'},
176 {'G', '0'}, {'H', '0'}, {'I', '0'},
177 {'J', '0'}, {'K', '0'}
178 };
179
180 static const struct stepping_info bxt_stepping_info[] = {
181 {'A', '0'}, {'A', '1'}, {'A', '2'},
182 {'B', '0'}, {'B', '1'}, {'B', '2'}
183 };
184
185 static const struct stepping_info no_stepping_info = { '*', '*' };
186
187 static const struct stepping_info *
intel_get_stepping_info(struct drm_i915_private * dev_priv)188 intel_get_stepping_info(struct drm_i915_private *dev_priv)
189 {
190 const struct stepping_info *si;
191 unsigned int size;
192
193 if (IS_SKYLAKE(dev_priv)) {
194 size = ARRAY_SIZE(skl_stepping_info);
195 si = skl_stepping_info;
196 } else if (IS_BROXTON(dev_priv)) {
197 size = ARRAY_SIZE(bxt_stepping_info);
198 si = bxt_stepping_info;
199 } else {
200 size = 0;
201 }
202
203 if (INTEL_REVID(dev_priv) < size)
204 return si + INTEL_REVID(dev_priv);
205
206 return &no_stepping_info;
207 }
208
gen9_set_dc_state_debugmask(struct drm_i915_private * dev_priv)209 static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
210 {
211 uint32_t val, mask;
212
213 mask = DC_STATE_DEBUG_MASK_MEMORY_UP;
214
215 if (IS_GEN9_LP(dev_priv))
216 mask |= DC_STATE_DEBUG_MASK_CORES;
217
218 /* The below bit doesn't need to be cleared ever afterwards */
219 val = I915_READ(DC_STATE_DEBUG);
220 if ((val & mask) != mask) {
221 val |= mask;
222 I915_WRITE(DC_STATE_DEBUG, val);
223 POSTING_READ(DC_STATE_DEBUG);
224 }
225 }
226
227 /**
228 * intel_csr_load_program() - write the firmware from memory to register.
229 * @dev_priv: i915 drm device.
230 *
231 * CSR firmware is read from a .bin file and kept in internal memory one time.
232 * Everytime display comes back from low power state this function is called to
233 * copy the firmware from internal memory to registers.
234 */
intel_csr_load_program(struct drm_i915_private * dev_priv)235 void intel_csr_load_program(struct drm_i915_private *dev_priv)
236 {
237 u32 *payload = dev_priv->csr.dmc_payload;
238 uint32_t i, fw_size;
239
240 if (!HAS_CSR(dev_priv)) {
241 DRM_ERROR("No CSR support available for this platform\n");
242 return;
243 }
244
245 if (!dev_priv->csr.dmc_payload) {
246 DRM_ERROR("Tried to program CSR with empty payload\n");
247 return;
248 }
249
250 fw_size = dev_priv->csr.dmc_fw_size;
251 assert_rpm_wakelock_held(dev_priv);
252
253 preempt_disable();
254
255 for (i = 0; i < fw_size; i++)
256 I915_WRITE_FW(CSR_PROGRAM(i), payload[i]);
257
258 preempt_enable();
259
260 for (i = 0; i < dev_priv->csr.mmio_count; i++) {
261 I915_WRITE(dev_priv->csr.mmioaddr[i],
262 dev_priv->csr.mmiodata[i]);
263 }
264
265 dev_priv->csr.dc_state = 0;
266
267 gen9_set_dc_state_debugmask(dev_priv);
268 }
269
parse_csr_fw(struct drm_i915_private * dev_priv,const struct firmware * fw)270 static uint32_t *parse_csr_fw(struct drm_i915_private *dev_priv,
271 const struct firmware *fw)
272 {
273 struct intel_css_header *css_header;
274 struct intel_package_header *package_header;
275 struct intel_dmc_header *dmc_header;
276 struct intel_csr *csr = &dev_priv->csr;
277 const struct stepping_info *si = intel_get_stepping_info(dev_priv);
278 uint32_t dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes;
279 uint32_t i;
280 uint32_t *dmc_payload;
281 uint32_t required_version;
282
283 if (!fw)
284 return NULL;
285
286 /* Extract CSS Header information*/
287 css_header = (struct intel_css_header *)fw->data;
288 if (sizeof(struct intel_css_header) !=
289 (css_header->header_len * 4)) {
290 DRM_ERROR("DMC firmware has wrong CSS header length "
291 "(%u bytes)\n",
292 (css_header->header_len * 4));
293 return NULL;
294 }
295
296 csr->version = css_header->version;
297
298 if (IS_CANNONLAKE(dev_priv)) {
299 required_version = CNL_CSR_VERSION_REQUIRED;
300 } else if (IS_GEMINILAKE(dev_priv)) {
301 required_version = GLK_CSR_VERSION_REQUIRED;
302 } else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
303 required_version = KBL_CSR_VERSION_REQUIRED;
304 } else if (IS_SKYLAKE(dev_priv)) {
305 required_version = SKL_CSR_VERSION_REQUIRED;
306 } else if (IS_BROXTON(dev_priv)) {
307 required_version = BXT_CSR_VERSION_REQUIRED;
308 } else {
309 MISSING_CASE(INTEL_REVID(dev_priv));
310 required_version = 0;
311 }
312
313 if (csr->version != required_version) {
314 DRM_INFO("Refusing to load DMC firmware v%u.%u,"
315 " please use v%u.%u\n",
316 CSR_VERSION_MAJOR(csr->version),
317 CSR_VERSION_MINOR(csr->version),
318 CSR_VERSION_MAJOR(required_version),
319 CSR_VERSION_MINOR(required_version));
320 return NULL;
321 }
322
323 readcount += sizeof(struct intel_css_header);
324
325 /* Extract Package Header information*/
326 package_header = (struct intel_package_header *)
327 &fw->data[readcount];
328 if (sizeof(struct intel_package_header) !=
329 (package_header->header_len * 4)) {
330 DRM_ERROR("DMC firmware has wrong package header length "
331 "(%u bytes)\n",
332 (package_header->header_len * 4));
333 return NULL;
334 }
335 readcount += sizeof(struct intel_package_header);
336
337 /* Search for dmc_offset to find firware binary. */
338 for (i = 0; i < package_header->num_entries; i++) {
339 if (package_header->fw_info[i].substepping == '*' &&
340 si->stepping == package_header->fw_info[i].stepping) {
341 dmc_offset = package_header->fw_info[i].offset;
342 break;
343 } else if (si->stepping == package_header->fw_info[i].stepping &&
344 si->substepping == package_header->fw_info[i].substepping) {
345 dmc_offset = package_header->fw_info[i].offset;
346 break;
347 } else if (package_header->fw_info[i].stepping == '*' &&
348 package_header->fw_info[i].substepping == '*')
349 dmc_offset = package_header->fw_info[i].offset;
350 }
351 if (dmc_offset == CSR_DEFAULT_FW_OFFSET) {
352 DRM_ERROR("DMC firmware not supported for %c stepping\n",
353 si->stepping);
354 return NULL;
355 }
356 readcount += dmc_offset;
357
358 /* Extract dmc_header information. */
359 dmc_header = (struct intel_dmc_header *)&fw->data[readcount];
360 if (sizeof(struct intel_dmc_header) != (dmc_header->header_len)) {
361 DRM_ERROR("DMC firmware has wrong dmc header length "
362 "(%u bytes)\n",
363 (dmc_header->header_len));
364 return NULL;
365 }
366 readcount += sizeof(struct intel_dmc_header);
367
368 /* Cache the dmc header info. */
369 if (dmc_header->mmio_count > ARRAY_SIZE(csr->mmioaddr)) {
370 DRM_ERROR("DMC firmware has wrong mmio count %u\n",
371 dmc_header->mmio_count);
372 return NULL;
373 }
374 csr->mmio_count = dmc_header->mmio_count;
375 for (i = 0; i < dmc_header->mmio_count; i++) {
376 if (dmc_header->mmioaddr[i] < CSR_MMIO_START_RANGE ||
377 dmc_header->mmioaddr[i] > CSR_MMIO_END_RANGE) {
378 DRM_ERROR("DMC firmware has wrong mmio address 0x%x\n",
379 dmc_header->mmioaddr[i]);
380 return NULL;
381 }
382 csr->mmioaddr[i] = _MMIO(dmc_header->mmioaddr[i]);
383 csr->mmiodata[i] = dmc_header->mmiodata[i];
384 }
385
386 /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */
387 nbytes = dmc_header->fw_size * 4;
388 if (nbytes > CSR_MAX_FW_SIZE) {
389 DRM_ERROR("DMC firmware too big (%u bytes)\n", nbytes);
390 return NULL;
391 }
392 csr->dmc_fw_size = dmc_header->fw_size;
393
394 dmc_payload = kmalloc(nbytes, M_DRM, GFP_KERNEL);
395 if (!dmc_payload) {
396 DRM_ERROR("Memory allocation failed for dmc payload\n");
397 return NULL;
398 }
399
400 return memcpy(dmc_payload, &fw->data[readcount], nbytes);
401 }
402
csr_load_work_fn(struct work_struct * work)403 static void csr_load_work_fn(struct work_struct *work)
404 {
405 struct drm_i915_private *dev_priv;
406 struct intel_csr *csr;
407 const struct firmware *fw = NULL;
408
409 dev_priv = container_of(work, typeof(*dev_priv), csr.work);
410 csr = &dev_priv->csr;
411
412 request_firmware(&fw, dev_priv->csr.fw_path, &dev_priv->drm.pdev->dev);
413 if (fw)
414 dev_priv->csr.dmc_payload = parse_csr_fw(dev_priv, fw);
415
416 if (dev_priv->csr.dmc_payload) {
417 intel_csr_load_program(dev_priv);
418
419 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
420
421 DRM_INFO("Finished loading DMC firmware %s (v%u.%u)\n",
422 dev_priv->csr.fw_path,
423 CSR_VERSION_MAJOR(csr->version),
424 CSR_VERSION_MINOR(csr->version));
425 } else {
426 dev_notice(dev_priv->drm.dev,
427 "Failed to load DMC firmware %s."
428 " Disabling runtime power management.\n",
429 csr->fw_path);
430 dev_notice(dev_priv->drm.dev, "DMC firmware homepage: %s",
431 INTEL_UC_FIRMWARE_URL);
432 }
433
434 release_firmware(fw);
435 }
436
437 /**
438 * intel_csr_ucode_init() - initialize the firmware loading.
439 * @dev_priv: i915 drm device.
440 *
441 * This function is called at the time of loading the display driver to read
442 * firmware from a .bin file and copied into a internal memory.
443 */
intel_csr_ucode_init(struct drm_i915_private * dev_priv)444 void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
445 {
446 struct intel_csr *csr = &dev_priv->csr;
447
448 INIT_WORK(&dev_priv->csr.work, csr_load_work_fn);
449
450 if (!HAS_CSR(dev_priv))
451 return;
452
453 if (IS_CANNONLAKE(dev_priv))
454 csr->fw_path = I915_CSR_CNL;
455 else if (IS_GEMINILAKE(dev_priv))
456 csr->fw_path = I915_CSR_GLK;
457 else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
458 csr->fw_path = I915_CSR_KBL;
459 else if (IS_SKYLAKE(dev_priv))
460 csr->fw_path = I915_CSR_SKL;
461 else if (IS_BROXTON(dev_priv))
462 csr->fw_path = I915_CSR_BXT;
463 else {
464 DRM_ERROR("Unexpected: no known CSR firmware for platform\n");
465 return;
466 }
467
468 DRM_DEBUG_KMS("Loading %s\n", csr->fw_path);
469
470 /*
471 * Obtain a runtime pm reference, until CSR is loaded,
472 * to avoid entering runtime-suspend.
473 */
474 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
475
476 schedule_work(&dev_priv->csr.work);
477 }
478
479 /**
480 * intel_csr_ucode_suspend() - prepare CSR firmware before system suspend
481 * @dev_priv: i915 drm device
482 *
483 * Prepare the DMC firmware before entering system suspend. This includes
484 * flushing pending work items and releasing any resources acquired during
485 * init.
486 */
intel_csr_ucode_suspend(struct drm_i915_private * dev_priv)487 void intel_csr_ucode_suspend(struct drm_i915_private *dev_priv)
488 {
489 if (!HAS_CSR(dev_priv))
490 return;
491
492 flush_work(&dev_priv->csr.work);
493
494 /* Drop the reference held in case DMC isn't loaded. */
495 if (!dev_priv->csr.dmc_payload)
496 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
497 }
498
499 /**
500 * intel_csr_ucode_resume() - init CSR firmware during system resume
501 * @dev_priv: i915 drm device
502 *
503 * Reinitialize the DMC firmware during system resume, reacquiring any
504 * resources released in intel_csr_ucode_suspend().
505 */
intel_csr_ucode_resume(struct drm_i915_private * dev_priv)506 void intel_csr_ucode_resume(struct drm_i915_private *dev_priv)
507 {
508 if (!HAS_CSR(dev_priv))
509 return;
510
511 /*
512 * Reacquire the reference to keep RPM disabled in case DMC isn't
513 * loaded.
514 */
515 if (!dev_priv->csr.dmc_payload)
516 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
517 }
518
519 /**
520 * intel_csr_ucode_fini() - unload the CSR firmware.
521 * @dev_priv: i915 drm device.
522 *
523 * Firmmware unloading includes freeing the internal memory and reset the
524 * firmware loading status.
525 */
intel_csr_ucode_fini(struct drm_i915_private * dev_priv)526 void intel_csr_ucode_fini(struct drm_i915_private *dev_priv)
527 {
528 if (!HAS_CSR(dev_priv))
529 return;
530
531 intel_csr_ucode_suspend(dev_priv);
532
533 kfree(dev_priv->csr.dmc_payload);
534 }
535