1 /* $NetBSD: intel_display_types.h,v 1.4 2021/12/19 11:38:26 riastradh Exp $ */
2
3 /*
4 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
5 * Copyright (c) 2007-2008 Intel Corporation
6 * Jesse Barnes <jesse.barnes@intel.com>
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef __INTEL_DISPLAY_TYPES_H__
29 #define __INTEL_DISPLAY_TYPES_H__
30
31 #include <linux/async.h>
32 #include <linux/i2c.h>
33 #include <linux/sched/clock.h>
34
35 #include <drm/drm_atomic.h>
36 #include <drm/drm_crtc.h>
37 #include <drm/drm_dp_dual_mode_helper.h>
38 #include <drm/drm_dp_mst_helper.h>
39 #include <drm/drm_encoder.h>
40 #include <drm/drm_fb_helper.h>
41 #include <drm/drm_probe_helper.h>
42 #include <drm/drm_rect.h>
43 #include <drm/drm_vblank.h>
44 #include <drm/i915_drm.h>
45 #include <drm/i915_mei_hdcp_interface.h>
46 #include <media/cec-notifier.h>
47
48 #include "i915_drv.h"
49
50 struct drm_printer;
51
52 /*
53 * Display related stuff
54 */
55
56 /* these are outputs from the chip - integrated only
57 external chips are via DVO or SDVO output */
58 enum intel_output_type {
59 INTEL_OUTPUT_UNUSED = 0,
60 INTEL_OUTPUT_ANALOG = 1,
61 INTEL_OUTPUT_DVO = 2,
62 INTEL_OUTPUT_SDVO = 3,
63 INTEL_OUTPUT_LVDS = 4,
64 INTEL_OUTPUT_TVOUT = 5,
65 INTEL_OUTPUT_HDMI = 6,
66 INTEL_OUTPUT_DP = 7,
67 INTEL_OUTPUT_EDP = 8,
68 INTEL_OUTPUT_DSI = 9,
69 INTEL_OUTPUT_DDI = 10,
70 INTEL_OUTPUT_DP_MST = 11,
71 };
72
73 enum hdmi_force_audio {
74 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
75 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
76 HDMI_AUDIO_AUTO, /* trust EDID */
77 HDMI_AUDIO_ON, /* force turn on HDMI audio */
78 };
79
80 /* "Broadcast RGB" property */
81 enum intel_broadcast_rgb {
82 INTEL_BROADCAST_RGB_AUTO,
83 INTEL_BROADCAST_RGB_FULL,
84 INTEL_BROADCAST_RGB_LIMITED,
85 };
86
87 struct intel_framebuffer {
88 struct drm_framebuffer base;
89 struct intel_frontbuffer *frontbuffer;
90 struct intel_rotation_info rot_info;
91
92 /* for each plane in the normal GTT view */
93 struct {
94 unsigned int x, y;
95 } normal[4];
96 /* for each plane in the rotated GTT view for no-CCS formats */
97 struct {
98 unsigned int x, y;
99 unsigned int pitch; /* pixels */
100 } rotated[2];
101 };
102
103 struct intel_fbdev {
104 struct drm_fb_helper helper;
105 struct intel_framebuffer *fb;
106 struct i915_vma *vma;
107 unsigned long vma_flags;
108 async_cookie_t cookie;
109 int preferred_bpp;
110
111 /* Whether or not fbdev hpd processing is temporarily suspended */
112 bool hpd_suspended : 1;
113 /* Set when a hotplug was received while HPD processing was
114 * suspended
115 */
116 bool hpd_waiting : 1;
117
118 /* Protects hpd_suspended */
119 struct mutex hpd_lock;
120 };
121
122 enum intel_hotplug_state {
123 INTEL_HOTPLUG_UNCHANGED,
124 INTEL_HOTPLUG_CHANGED,
125 INTEL_HOTPLUG_RETRY,
126 };
127
128 struct intel_encoder {
129 struct drm_encoder base;
130
131 enum intel_output_type type;
132 enum port port;
133 u16 cloneable;
134 u8 pipe_mask;
135 enum intel_hotplug_state (*hotplug)(struct intel_encoder *encoder,
136 struct intel_connector *connector,
137 bool irq_received);
138 enum intel_output_type (*compute_output_type)(struct intel_encoder *,
139 struct intel_crtc_state *,
140 struct drm_connector_state *);
141 int (*compute_config)(struct intel_encoder *,
142 struct intel_crtc_state *,
143 struct drm_connector_state *);
144 void (*update_prepare)(struct intel_atomic_state *,
145 struct intel_encoder *,
146 struct intel_crtc *);
147 void (*pre_pll_enable)(struct intel_encoder *,
148 const struct intel_crtc_state *,
149 const struct drm_connector_state *);
150 void (*pre_enable)(struct intel_encoder *,
151 const struct intel_crtc_state *,
152 const struct drm_connector_state *);
153 void (*enable)(struct intel_encoder *,
154 const struct intel_crtc_state *,
155 const struct drm_connector_state *);
156 void (*update_complete)(struct intel_atomic_state *,
157 struct intel_encoder *,
158 struct intel_crtc *);
159 void (*disable)(struct intel_encoder *,
160 const struct intel_crtc_state *,
161 const struct drm_connector_state *);
162 void (*post_disable)(struct intel_encoder *,
163 const struct intel_crtc_state *,
164 const struct drm_connector_state *);
165 void (*post_pll_disable)(struct intel_encoder *,
166 const struct intel_crtc_state *,
167 const struct drm_connector_state *);
168 void (*update_pipe)(struct intel_encoder *,
169 const struct intel_crtc_state *,
170 const struct drm_connector_state *);
171 /* Read out the current hw state of this connector, returning true if
172 * the encoder is active. If the encoder is enabled it also set the pipe
173 * it is connected to in the pipe parameter. */
174 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
175 /* Reconstructs the equivalent mode flags for the current hardware
176 * state. This must be called _after_ display->get_pipe_config has
177 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
178 * be set correctly before calling this function. */
179 void (*get_config)(struct intel_encoder *,
180 struct intel_crtc_state *pipe_config);
181 /*
182 * Acquires the power domains needed for an active encoder during
183 * hardware state readout.
184 */
185 void (*get_power_domains)(struct intel_encoder *encoder,
186 struct intel_crtc_state *crtc_state);
187 /*
188 * Called during system suspend after all pending requests for the
189 * encoder are flushed (for example for DP AUX transactions) and
190 * device interrupts are disabled.
191 */
192 void (*suspend)(struct intel_encoder *);
193 enum hpd_pin hpd_pin;
194 enum intel_display_power_domain power_domain;
195 /* for communication with audio component; protected by av_mutex */
196 const struct drm_connector *audio_connector;
197 };
198
199 struct intel_panel {
200 struct drm_display_mode *fixed_mode;
201 struct drm_display_mode *downclock_mode;
202
203 /* backlight */
204 struct {
205 bool present;
206 u32 level;
207 u32 min;
208 u32 max;
209 bool enabled;
210 bool combination_mode; /* gen 2/4 only */
211 bool active_low_pwm;
212 bool alternate_pwm_increment; /* lpt+ */
213
214 /* PWM chip */
215 bool util_pin_active_low; /* bxt+ */
216 u8 controller; /* bxt+ only */
217 struct pwm_device *pwm;
218
219 struct backlight_device *device;
220
221 /* Connector and platform specific backlight functions */
222 int (*setup)(struct intel_connector *connector, enum pipe pipe);
223 u32 (*get)(struct intel_connector *connector);
224 void (*set)(const struct drm_connector_state *conn_state, u32 level);
225 void (*disable)(const struct drm_connector_state *conn_state);
226 void (*enable)(const struct intel_crtc_state *crtc_state,
227 const struct drm_connector_state *conn_state);
228 u32 (*hz_to_pwm)(struct intel_connector *connector, u32 hz);
229 void (*power)(struct intel_connector *, bool enable);
230 } backlight;
231 };
232
233 struct intel_digital_port;
234
235 enum check_link_response {
236 HDCP_LINK_PROTECTED = 0,
237 HDCP_TOPOLOGY_CHANGE,
238 HDCP_LINK_INTEGRITY_FAILURE,
239 HDCP_REAUTH_REQUEST
240 };
241
242 /*
243 * This structure serves as a translation layer between the generic HDCP code
244 * and the bus-specific code. What that means is that HDCP over HDMI differs
245 * from HDCP over DP, so to account for these differences, we need to
246 * communicate with the receiver through this shim.
247 *
248 * For completeness, the 2 buses differ in the following ways:
249 * - DP AUX vs. DDC
250 * HDCP registers on the receiver are set via DP AUX for DP, and
251 * they are set via DDC for HDMI.
252 * - Receiver register offsets
253 * The offsets of the registers are different for DP vs. HDMI
254 * - Receiver register masks/offsets
255 * For instance, the ready bit for the KSV fifo is in a different
256 * place on DP vs HDMI
257 * - Receiver register names
258 * Seriously. In the DP spec, the 16-bit register containing
259 * downstream information is called BINFO, on HDMI it's called
260 * BSTATUS. To confuse matters further, DP has a BSTATUS register
261 * with a completely different definition.
262 * - KSV FIFO
263 * On HDMI, the ksv fifo is read all at once, whereas on DP it must
264 * be read 3 keys at a time
265 * - Aksv output
266 * Since Aksv is hidden in hardware, there's different procedures
267 * to send it over DP AUX vs DDC
268 */
269 struct intel_hdcp_shim {
270 /* Outputs the transmitter's An and Aksv values to the receiver. */
271 int (*write_an_aksv)(struct intel_digital_port *intel_dig_port, u8 *an);
272
273 /* Reads the receiver's key selection vector */
274 int (*read_bksv)(struct intel_digital_port *intel_dig_port, u8 *bksv);
275
276 /*
277 * Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The
278 * definitions are the same in the respective specs, but the names are
279 * different. Call it BSTATUS since that's the name the HDMI spec
280 * uses and it was there first.
281 */
282 int (*read_bstatus)(struct intel_digital_port *intel_dig_port,
283 u8 *bstatus);
284
285 /* Determines whether a repeater is present downstream */
286 int (*repeater_present)(struct intel_digital_port *intel_dig_port,
287 bool *repeater_present);
288
289 /* Reads the receiver's Ri' value */
290 int (*read_ri_prime)(struct intel_digital_port *intel_dig_port, u8 *ri);
291
292 /* Determines if the receiver's KSV FIFO is ready for consumption */
293 int (*read_ksv_ready)(struct intel_digital_port *intel_dig_port,
294 bool *ksv_ready);
295
296 /* Reads the ksv fifo for num_downstream devices */
297 int (*read_ksv_fifo)(struct intel_digital_port *intel_dig_port,
298 int num_downstream, u8 *ksv_fifo);
299
300 /* Reads a 32-bit part of V' from the receiver */
301 int (*read_v_prime_part)(struct intel_digital_port *intel_dig_port,
302 int i, u32 *part);
303
304 /* Enables HDCP signalling on the port */
305 int (*toggle_signalling)(struct intel_digital_port *intel_dig_port,
306 bool enable);
307
308 /* Ensures the link is still protected */
309 bool (*check_link)(struct intel_digital_port *intel_dig_port);
310
311 /* Detects panel's hdcp capability. This is optional for HDMI. */
312 int (*hdcp_capable)(struct intel_digital_port *intel_dig_port,
313 bool *hdcp_capable);
314
315 /* HDCP adaptation(DP/HDMI) required on the port */
316 enum hdcp_wired_protocol protocol;
317
318 /* Detects whether sink is HDCP2.2 capable */
319 int (*hdcp_2_2_capable)(struct intel_digital_port *intel_dig_port,
320 bool *capable);
321
322 /* Write HDCP2.2 messages */
323 int (*write_2_2_msg)(struct intel_digital_port *intel_dig_port,
324 void *buf, size_t size);
325
326 /* Read HDCP2.2 messages */
327 int (*read_2_2_msg)(struct intel_digital_port *intel_dig_port,
328 u8 msg_id, void *buf, size_t size);
329
330 /*
331 * Implementation of DP HDCP2.2 Errata for the communication of stream
332 * type to Receivers. In DP HDCP2.2 Stream type is one of the input to
333 * the HDCP2.2 Cipher for En/De-Cryption. Not applicable for HDMI.
334 */
335 int (*config_stream_type)(struct intel_digital_port *intel_dig_port,
336 bool is_repeater, u8 type);
337
338 /* HDCP2.2 Link Integrity Check */
339 int (*check_2_2_link)(struct intel_digital_port *intel_dig_port);
340 };
341
342 struct intel_hdcp {
343 const struct intel_hdcp_shim *shim;
344 /* Mutex for hdcp state of the connector */
345 struct mutex mutex;
346 u64 value;
347 struct delayed_work check_work;
348 struct work_struct prop_work;
349
350 /* HDCP1.4 Encryption status */
351 bool hdcp_encrypted;
352
353 /* HDCP2.2 related definitions */
354 /* Flag indicates whether this connector supports HDCP2.2 or not. */
355 bool hdcp2_supported;
356
357 /* HDCP2.2 Encryption status */
358 bool hdcp2_encrypted;
359
360 /*
361 * Content Stream Type defined by content owner. TYPE0(0x0) content can
362 * flow in the link protected by HDCP2.2 or HDCP1.4, where as TYPE1(0x1)
363 * content can flow only through a link protected by HDCP2.2.
364 */
365 u8 content_type;
366 struct hdcp_port_data port_data;
367
368 bool is_paired;
369 bool is_repeater;
370
371 /*
372 * Count of ReceiverID_List received. Initialized to 0 at AKE_INIT.
373 * Incremented after processing the RepeaterAuth_Send_ReceiverID_List.
374 * When it rolls over re-auth has to be triggered.
375 */
376 u32 seq_num_v;
377
378 /*
379 * Count of RepeaterAuth_Stream_Manage msg propagated.
380 * Initialized to 0 on AKE_INIT. Incremented after every successful
381 * transmission of RepeaterAuth_Stream_Manage message. When it rolls
382 * over re-Auth has to be triggered.
383 */
384 u32 seq_num_m;
385
386 /*
387 * Work queue to signal the CP_IRQ. Used for the waiters to read the
388 * available information from HDCP DP sink.
389 */
390 spinlock_t cp_irq_lock;
391 drm_waitqueue_t cp_irq_queue;
392 atomic_t cp_irq_count;
393 int cp_irq_count_cached;
394
395 /*
396 * HDCP register access for gen12+ need the transcoder associated.
397 * Transcoder attached to the connector could be changed at modeset.
398 * Hence caching the transcoder here.
399 */
400 enum transcoder cpu_transcoder;
401 };
402
403 struct intel_connector {
404 struct drm_connector base;
405 /*
406 * The fixed encoder this connector is connected to.
407 */
408 struct intel_encoder *encoder;
409
410 /* ACPI device id for ACPI and driver cooperation */
411 u32 acpi_device_id;
412
413 /* Reads out the current hw, returning true if the connector is enabled
414 * and active (i.e. dpms ON state). */
415 bool (*get_hw_state)(struct intel_connector *);
416
417 /* Panel info for eDP and LVDS */
418 struct intel_panel panel;
419
420 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
421 struct edid *edid;
422 struct edid *detect_edid;
423
424 /* since POLL and HPD connectors may use the same HPD line keep the native
425 state of connector->polled in case hotplug storm detection changes it */
426 u8 polled;
427
428 void *port; /* store this opaque as its illegal to dereference it */
429
430 struct intel_dp *mst_port;
431
432 /* Work struct to schedule a uevent on link train failure */
433 struct work_struct modeset_retry_work;
434
435 struct intel_hdcp hdcp;
436 };
437
438 struct intel_digital_connector_state {
439 struct drm_connector_state base;
440
441 enum hdmi_force_audio force_audio;
442 int broadcast_rgb;
443 };
444
445 #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
446
447 struct dpll {
448 /* given values */
449 int n;
450 int m1, m2;
451 int p1, p2;
452 /* derived values */
453 int dot;
454 int vco;
455 int m;
456 int p;
457 };
458
459 struct intel_atomic_state {
460 struct drm_atomic_state base;
461
462 intel_wakeref_t wakeref;
463
464 struct {
465 /*
466 * Logical state of cdclk (used for all scaling, watermark,
467 * etc. calculations and checks). This is computed as if all
468 * enabled crtcs were active.
469 */
470 struct intel_cdclk_state logical;
471
472 /*
473 * Actual state of cdclk, can be different from the logical
474 * state only when all crtc's are DPMS off.
475 */
476 struct intel_cdclk_state actual;
477
478 int force_min_cdclk;
479 bool force_min_cdclk_changed;
480 /* pipe to which cd2x update is synchronized */
481 enum pipe pipe;
482 } cdclk;
483
484 bool dpll_set, modeset;
485
486 /*
487 * Does this transaction change the pipes that are active? This mask
488 * tracks which CRTC's have changed their active state at the end of
489 * the transaction (not counting the temporary disable during modesets).
490 * This mask should only be non-zero when intel_state->modeset is true,
491 * but the converse is not necessarily true; simply changing a mode may
492 * not flip the final active status of any CRTC's
493 */
494 u8 active_pipe_changes;
495
496 u8 active_pipes;
497 /* minimum acceptable cdclk for each pipe */
498 int min_cdclk[I915_MAX_PIPES];
499 /* minimum acceptable voltage level for each pipe */
500 u8 min_voltage_level[I915_MAX_PIPES];
501
502 struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
503
504 /*
505 * Current watermarks can't be trusted during hardware readout, so
506 * don't bother calculating intermediate watermarks.
507 */
508 bool skip_intermediate_wm;
509
510 bool rps_interactive;
511
512 /*
513 * active_pipes
514 * min_cdclk[]
515 * min_voltage_level[]
516 * cdclk.*
517 */
518 bool global_state_changed;
519
520 /* Gen9+ only */
521 struct skl_ddb_values wm_results;
522
523 struct i915_sw_fence commit_ready;
524
525 struct llist_node freed;
526 };
527
528 struct intel_plane_state {
529 struct drm_plane_state uapi;
530
531 /*
532 * actual hardware state, the state we program to the hardware.
533 * The following members are used to verify the hardware state:
534 * During initial hw readout, they need to be copied from uapi.
535 */
536 struct {
537 struct drm_crtc *crtc;
538 struct drm_framebuffer *fb;
539
540 u16 alpha;
541 uint16_t pixel_blend_mode;
542 unsigned int rotation;
543 enum drm_color_encoding color_encoding;
544 enum drm_color_range color_range;
545 } hw;
546
547 struct i915_ggtt_view view;
548 struct i915_vma *vma;
549 unsigned long flags;
550 #define PLANE_HAS_FENCE BIT(0)
551
552 struct {
553 u32 offset;
554 /*
555 * Plane stride in:
556 * bytes for 0/180 degree rotation
557 * pixels for 90/270 degree rotation
558 */
559 u32 stride;
560 int x, y;
561 } color_plane[4];
562
563 /* plane control register */
564 u32 ctl;
565
566 /* plane color control register */
567 u32 color_ctl;
568
569 /* chroma upsampler control register */
570 u32 cus_ctl;
571
572 /*
573 * scaler_id
574 * = -1 : not using a scaler
575 * >= 0 : using a scalers
576 *
577 * plane requiring a scaler:
578 * - During check_plane, its bit is set in
579 * crtc_state->scaler_state.scaler_users by calling helper function
580 * update_scaler_plane.
581 * - scaler_id indicates the scaler it got assigned.
582 *
583 * plane doesn't require a scaler:
584 * - this can happen when scaling is no more required or plane simply
585 * got disabled.
586 * - During check_plane, corresponding bit is reset in
587 * crtc_state->scaler_state.scaler_users by calling helper function
588 * update_scaler_plane.
589 */
590 int scaler_id;
591
592 /*
593 * planar_linked_plane:
594 *
595 * ICL planar formats require 2 planes that are updated as pairs.
596 * This member is used to make sure the other plane is also updated
597 * when required, and for update_slave() to find the correct
598 * plane_state to pass as argument.
599 */
600 struct intel_plane *planar_linked_plane;
601
602 /*
603 * planar_slave:
604 * If set don't update use the linked plane's state for updating
605 * this plane during atomic commit with the update_slave() callback.
606 *
607 * It's also used by the watermark code to ignore wm calculations on
608 * this plane. They're calculated by the linked plane's wm code.
609 */
610 u32 planar_slave;
611
612 struct drm_intel_sprite_colorkey ckey;
613 };
614
615 struct intel_initial_plane_config {
616 struct intel_framebuffer *fb;
617 unsigned int tiling;
618 int size;
619 u32 base;
620 u8 rotation;
621 };
622
623 struct intel_scaler {
624 int in_use;
625 u32 mode;
626 };
627
628 struct intel_crtc_scaler_state {
629 #define SKL_NUM_SCALERS 2
630 struct intel_scaler scalers[SKL_NUM_SCALERS];
631
632 /*
633 * scaler_users: keeps track of users requesting scalers on this crtc.
634 *
635 * If a bit is set, a user is using a scaler.
636 * Here user can be a plane or crtc as defined below:
637 * bits 0-30 - plane (bit position is index from drm_plane_index)
638 * bit 31 - crtc
639 *
640 * Instead of creating a new index to cover planes and crtc, using
641 * existing drm_plane_index for planes which is well less than 31
642 * planes and bit 31 for crtc. This should be fine to cover all
643 * our platforms.
644 *
645 * intel_atomic_setup_scalers will setup available scalers to users
646 * requesting scalers. It will gracefully fail if request exceeds
647 * avilability.
648 */
649 #define SKL_CRTC_INDEX 31
650 unsigned scaler_users;
651
652 /* scaler used by crtc for panel fitting purpose */
653 int scaler_id;
654 };
655
656 /* drm_mode->private_flags */
657 #define I915_MODE_FLAG_INHERITED (1<<0)
658 /* Flag to get scanline using frame time stamps */
659 #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
660 /* Flag to use the scanline counter instead of the pixel counter */
661 #define I915_MODE_FLAG_USE_SCANLINE_COUNTER (1<<2)
662
663 struct intel_pipe_wm {
664 struct intel_wm_level wm[5];
665 u32 linetime;
666 bool fbc_wm_enabled;
667 bool pipe_enabled;
668 bool sprites_enabled;
669 bool sprites_scaled;
670 };
671
672 struct skl_plane_wm {
673 struct skl_wm_level wm[8];
674 struct skl_wm_level uv_wm[8];
675 struct skl_wm_level trans_wm;
676 bool is_planar;
677 };
678
679 struct skl_pipe_wm {
680 struct skl_plane_wm planes[I915_MAX_PLANES];
681 u32 linetime;
682 };
683
684 enum vlv_wm_level {
685 VLV_WM_LEVEL_PM2,
686 VLV_WM_LEVEL_PM5,
687 VLV_WM_LEVEL_DDR_DVFS,
688 NUM_VLV_WM_LEVELS,
689 };
690
691 struct vlv_wm_state {
692 struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
693 struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
694 u8 num_levels;
695 bool cxsr;
696 };
697
698 struct vlv_fifo_state {
699 u16 plane[I915_MAX_PLANES];
700 };
701
702 enum g4x_wm_level {
703 G4X_WM_LEVEL_NORMAL,
704 G4X_WM_LEVEL_SR,
705 G4X_WM_LEVEL_HPLL,
706 NUM_G4X_WM_LEVELS,
707 };
708
709 struct g4x_wm_state {
710 struct g4x_pipe_wm wm;
711 struct g4x_sr_wm sr;
712 struct g4x_sr_wm hpll;
713 bool cxsr;
714 bool hpll_en;
715 bool fbc_en;
716 };
717
718 struct intel_crtc_wm_state {
719 union {
720 struct {
721 /*
722 * Intermediate watermarks; these can be
723 * programmed immediately since they satisfy
724 * both the current configuration we're
725 * switching away from and the new
726 * configuration we're switching to.
727 */
728 struct intel_pipe_wm intermediate;
729
730 /*
731 * Optimal watermarks, programmed post-vblank
732 * when this state is committed.
733 */
734 struct intel_pipe_wm optimal;
735 } ilk;
736
737 struct {
738 /* gen9+ only needs 1-step wm programming */
739 struct skl_pipe_wm optimal;
740 struct skl_ddb_entry ddb;
741 struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES];
742 struct skl_ddb_entry plane_ddb_uv[I915_MAX_PLANES];
743 } skl;
744
745 struct {
746 /* "raw" watermarks (not inverted) */
747 struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS];
748 /* intermediate watermarks (inverted) */
749 struct vlv_wm_state intermediate;
750 /* optimal watermarks (inverted) */
751 struct vlv_wm_state optimal;
752 /* display FIFO split */
753 struct vlv_fifo_state fifo_state;
754 } vlv;
755
756 struct {
757 /* "raw" watermarks */
758 struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
759 /* intermediate watermarks */
760 struct g4x_wm_state intermediate;
761 /* optimal watermarks */
762 struct g4x_wm_state optimal;
763 } g4x;
764 };
765
766 /*
767 * Platforms with two-step watermark programming will need to
768 * update watermark programming post-vblank to switch from the
769 * safe intermediate watermarks to the optimal final
770 * watermarks.
771 */
772 bool need_postvbl_update;
773 };
774
775 enum intel_output_format {
776 INTEL_OUTPUT_FORMAT_INVALID,
777 INTEL_OUTPUT_FORMAT_RGB,
778 INTEL_OUTPUT_FORMAT_YCBCR420,
779 INTEL_OUTPUT_FORMAT_YCBCR444,
780 };
781
782 struct intel_crtc_state {
783 /*
784 * uapi (drm) state. This is the software state shown to userspace.
785 * In particular, the following members are used for bookkeeping:
786 * - crtc
787 * - state
788 * - *_changed
789 * - event
790 * - commit
791 * - mode_blob
792 */
793 struct drm_crtc_state uapi;
794
795 /*
796 * actual hardware state, the state we program to the hardware.
797 * The following members are used to verify the hardware state:
798 * - enable
799 * - active
800 * - mode / adjusted_mode
801 * - color property blobs.
802 *
803 * During initial hw readout, they need to be copied to uapi.
804 */
805 struct {
806 bool active, enable;
807 struct drm_property_blob *degamma_lut, *gamma_lut, *ctm;
808 struct drm_display_mode mode, adjusted_mode;
809 } hw;
810
811 /**
812 * quirks - bitfield with hw state readout quirks
813 *
814 * For various reasons the hw state readout code might not be able to
815 * completely faithfully read out the current state. These cases are
816 * tracked with quirk flags so that fastboot and state checker can act
817 * accordingly.
818 */
819 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
820 unsigned long quirks;
821
822 unsigned fb_bits; /* framebuffers to flip */
823 bool update_pipe; /* can a fast modeset be performed? */
824 bool disable_cxsr;
825 bool update_wm_pre, update_wm_post; /* watermarks are updated */
826 bool fifo_changed; /* FIFO split is changed */
827 bool preload_luts;
828
829 /* Pipe source size (ie. panel fitter input size)
830 * All planes will be positioned inside this space,
831 * and get clipped at the edges. */
832 int pipe_src_w, pipe_src_h;
833
834 /*
835 * Pipe pixel rate, adjusted for
836 * panel fitter/pipe scaler downscaling.
837 */
838 unsigned int pixel_rate;
839
840 /* Whether to set up the PCH/FDI. Note that we never allow sharing
841 * between pch encoders and cpu encoders. */
842 bool has_pch_encoder;
843
844 /* Are we sending infoframes on the attached port */
845 bool has_infoframe;
846
847 /* CPU Transcoder for the pipe. Currently this can only differ from the
848 * pipe on Haswell and later (where we have a special eDP transcoder)
849 * and Broxton (where we have special DSI transcoders). */
850 enum transcoder cpu_transcoder;
851
852 /*
853 * Use reduced/limited/broadcast rbg range, compressing from the full
854 * range fed into the crtcs.
855 */
856 bool limited_color_range;
857
858 /* Bitmask of encoder types (enum intel_output_type)
859 * driven by the pipe.
860 */
861 unsigned int output_types;
862
863 /* Whether we should send NULL infoframes. Required for audio. */
864 bool has_hdmi_sink;
865
866 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
867 * has_dp_encoder is set. */
868 bool has_audio;
869
870 /*
871 * Enable dithering, used when the selected pipe bpp doesn't match the
872 * plane bpp.
873 */
874 bool dither;
875
876 /*
877 * Dither gets enabled for 18bpp which causes CRC mismatch errors for
878 * compliance video pattern tests.
879 * Disable dither only if it is a compliance test request for
880 * 18bpp.
881 */
882 bool dither_force_disable;
883
884 /* Controls for the clock computation, to override various stages. */
885 bool clock_set;
886
887 /* SDVO TV has a bunch of special case. To make multifunction encoders
888 * work correctly, we need to track this at runtime.*/
889 bool sdvo_tv_clock;
890
891 /*
892 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
893 * required. This is set in the 2nd loop of calling encoder's
894 * ->compute_config if the first pick doesn't work out.
895 */
896 bool bw_constrained;
897
898 /* Settings for the intel dpll used on pretty much everything but
899 * haswell. */
900 struct dpll dpll;
901
902 /* Selected dpll when shared or NULL. */
903 struct intel_shared_dpll *shared_dpll;
904
905 /* Actual register state of the dpll, for shared dpll cross-checking. */
906 struct intel_dpll_hw_state dpll_hw_state;
907
908 /*
909 * ICL reserved DPLLs for the CRTC/port. The active PLL is selected by
910 * setting shared_dpll and dpll_hw_state to one of these reserved ones.
911 */
912 struct icl_port_dpll {
913 struct intel_shared_dpll *pll;
914 struct intel_dpll_hw_state hw_state;
915 } icl_port_dplls[ICL_PORT_DPLL_COUNT];
916
917 /* DSI PLL registers */
918 struct {
919 u32 ctrl, div;
920 } dsi_pll;
921
922 int pipe_bpp;
923 struct intel_link_m_n dp_m_n;
924
925 /* m2_n2 for eDP downclock */
926 struct intel_link_m_n dp_m2_n2;
927 bool has_drrs;
928
929 bool has_psr;
930 bool has_psr2;
931 u32 dc3co_exitline;
932
933 /*
934 * Frequence the dpll for the port should run at. Differs from the
935 * adjusted dotclock e.g. for DP or 10/12bpc hdmi mode. This is also
936 * already multiplied by pixel_multiplier.
937 */
938 int port_clock;
939
940 /* Used by SDVO (and if we ever fix it, HDMI). */
941 unsigned pixel_multiplier;
942
943 u8 lane_count;
944
945 /*
946 * Used by platforms having DP/HDMI PHY with programmable lane
947 * latency optimization.
948 */
949 u8 lane_lat_optim_mask;
950
951 /* minimum acceptable voltage level */
952 u8 min_voltage_level;
953
954 /* Panel fitter controls for gen2-gen4 + VLV */
955 struct {
956 u32 control;
957 u32 pgm_ratios;
958 u32 lvds_border_bits;
959 } gmch_pfit;
960
961 /* Panel fitter placement and size for Ironlake+ */
962 struct {
963 u32 pos;
964 u32 size;
965 bool enabled;
966 bool force_thru;
967 } pch_pfit;
968
969 /* FDI configuration, only valid if has_pch_encoder is set. */
970 int fdi_lanes;
971 struct intel_link_m_n fdi_m_n;
972
973 bool ips_enabled;
974
975 bool crc_enabled;
976
977 bool enable_fbc;
978
979 bool double_wide;
980
981 int pbn;
982
983 struct intel_crtc_scaler_state scaler_state;
984
985 /* w/a for waiting 2 vblanks during crtc enable */
986 enum pipe hsw_workaround_pipe;
987
988 /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
989 bool disable_lp_wm;
990
991 struct intel_crtc_wm_state wm;
992
993 int min_cdclk[I915_MAX_PLANES];
994
995 u32 data_rate[I915_MAX_PLANES];
996
997 /* Gamma mode programmed on the pipe */
998 u32 gamma_mode;
999
1000 union {
1001 /* CSC mode programmed on the pipe */
1002 u32 csc_mode;
1003
1004 /* CHV CGM mode */
1005 u32 cgm_mode;
1006 };
1007
1008 /* bitmask of visible planes (enum plane_id) */
1009 u8 active_planes;
1010 u8 nv12_planes;
1011 u8 c8_planes;
1012
1013 /* bitmask of planes that will be updated during the commit */
1014 u8 update_planes;
1015
1016 struct {
1017 u32 enable;
1018 u32 gcp;
1019 union hdmi_infoframe avi;
1020 union hdmi_infoframe spd;
1021 union hdmi_infoframe hdmi;
1022 union hdmi_infoframe drm;
1023 } infoframes;
1024
1025 /* HDMI scrambling status */
1026 bool hdmi_scrambling;
1027
1028 /* HDMI High TMDS char rate ratio */
1029 bool hdmi_high_tmds_clock_ratio;
1030
1031 /* Output format RGB/YCBCR etc */
1032 enum intel_output_format output_format;
1033
1034 /* Output down scaling is done in LSPCON device */
1035 bool lspcon_downsampling;
1036
1037 /* enable pipe gamma? */
1038 bool gamma_enable;
1039
1040 /* enable pipe csc? */
1041 bool csc_enable;
1042
1043 /* Display Stream compression state */
1044 struct {
1045 bool compression_enable;
1046 bool dsc_split;
1047 u16 compressed_bpp;
1048 u8 slice_count;
1049 struct drm_dsc_config config;
1050 } dsc;
1051
1052 /* Forward Error correction State */
1053 bool fec_enable;
1054
1055 /* Pointer to master transcoder in case of tiled displays */
1056 enum transcoder master_transcoder;
1057
1058 /* Bitmask to indicate slaves attached */
1059 u8 sync_mode_slaves_mask;
1060
1061 /* Only valid on TGL+ */
1062 enum transcoder mst_master_transcoder;
1063 };
1064
1065 struct intel_crtc {
1066 struct drm_crtc base;
1067 enum pipe pipe;
1068 /*
1069 * Whether the crtc and the connected output pipeline is active. Implies
1070 * that crtc->enabled is set, i.e. the current mode configuration has
1071 * some outputs connected to this crtc.
1072 */
1073 bool active;
1074 u8 plane_ids_mask;
1075 unsigned long long enabled_power_domains;
1076 struct intel_overlay *overlay;
1077
1078 struct intel_crtc_state *config;
1079
1080 /* Access to these should be protected by dev_priv->irq_lock. */
1081 bool cpu_fifo_underrun_disabled;
1082 bool pch_fifo_underrun_disabled;
1083
1084 /* per-pipe watermark state */
1085 struct {
1086 /* watermarks currently being used */
1087 union {
1088 struct intel_pipe_wm ilk;
1089 struct vlv_wm_state vlv;
1090 struct g4x_wm_state g4x;
1091 } active;
1092 } wm;
1093
1094 int scanline_offset;
1095
1096 struct {
1097 unsigned start_vbl_count;
1098 ktime_t start_vbl_time;
1099 int min_vbl, max_vbl;
1100 int scanline_start;
1101 } debug;
1102
1103 /* scalers available on this crtc */
1104 int num_scalers;
1105
1106 /* per pipe DSB related info */
1107 struct intel_dsb dsb;
1108 };
1109
1110 struct intel_plane {
1111 struct drm_plane base;
1112 enum i9xx_plane_id i9xx_plane;
1113 enum plane_id id;
1114 enum pipe pipe;
1115 bool has_fbc;
1116 bool has_ccs;
1117 u32 frontbuffer_bit;
1118
1119 struct {
1120 u32 base, cntl, size;
1121 } cursor;
1122
1123 /*
1124 * NOTE: Do not place new plane state fields here (e.g., when adding
1125 * new plane properties). New runtime state should now be placed in
1126 * the intel_plane_state structure and accessed via plane_state.
1127 */
1128
1129 unsigned int (*max_stride)(struct intel_plane *plane,
1130 u32 pixel_format, u64 modifier,
1131 unsigned int rotation);
1132 void (*update_plane)(struct intel_plane *plane,
1133 const struct intel_crtc_state *crtc_state,
1134 const struct intel_plane_state *plane_state);
1135 void (*disable_plane)(struct intel_plane *plane,
1136 const struct intel_crtc_state *crtc_state);
1137 bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe);
1138 int (*check_plane)(struct intel_crtc_state *crtc_state,
1139 struct intel_plane_state *plane_state);
1140 int (*min_cdclk)(const struct intel_crtc_state *crtc_state,
1141 const struct intel_plane_state *plane_state);
1142 };
1143
1144 struct intel_watermark_params {
1145 u16 fifo_size;
1146 u16 max_wm;
1147 u8 default_wm;
1148 u8 guard_size;
1149 u8 cacheline_size;
1150 };
1151
1152 struct cxsr_latency {
1153 bool is_desktop : 1;
1154 bool is_ddr3 : 1;
1155 u16 fsb_freq;
1156 u16 mem_freq;
1157 u16 display_sr;
1158 u16 display_hpll_disable;
1159 u16 cursor_sr;
1160 u16 cursor_hpll_disable;
1161 };
1162
1163 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
1164 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
1165 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, uapi)
1166 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
1167 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
1168 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
1169 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
1170 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, uapi)
1171 #define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL)
1172
1173 struct intel_hdmi {
1174 i915_reg_t hdmi_reg;
1175 int ddc_bus;
1176 struct {
1177 enum drm_dp_dual_mode_type type;
1178 int max_tmds_clock;
1179 } dp_dual_mode;
1180 bool has_hdmi_sink;
1181 bool has_audio;
1182 struct intel_connector *attached_connector;
1183 struct cec_notifier *cec_notifier;
1184 };
1185
1186 struct intel_dp_mst_encoder;
1187 #define DP_MAX_DOWNSTREAM_PORTS 0x10
1188
1189 /*
1190 * enum link_m_n_set:
1191 * When platform provides two set of M_N registers for dp, we can
1192 * program them and switch between them incase of DRRS.
1193 * But When only one such register is provided, we have to program the
1194 * required divider value on that registers itself based on the DRRS state.
1195 *
1196 * M1_N1 : Program dp_m_n on M1_N1 registers
1197 * dp_m2_n2 on M2_N2 registers (If supported)
1198 *
1199 * M2_N2 : Program dp_m2_n2 on M1_N1 registers
1200 * M2_N2 registers are not supported
1201 */
1202
1203 enum link_m_n_set {
1204 /* Sets the m1_n1 and m2_n2 */
1205 M1_N1 = 0,
1206 M2_N2
1207 };
1208
1209 struct intel_dp_compliance_data {
1210 unsigned long edid;
1211 u8 video_pattern;
1212 u16 hdisplay, vdisplay;
1213 u8 bpc;
1214 };
1215
1216 struct intel_dp_compliance {
1217 unsigned long test_type;
1218 struct intel_dp_compliance_data test_data;
1219 bool test_active;
1220 int test_link_rate;
1221 u8 test_lane_count;
1222 };
1223
1224 struct intel_dp {
1225 i915_reg_t output_reg;
1226 u32 DP;
1227 int link_rate;
1228 u8 lane_count;
1229 u8 sink_count;
1230 bool link_mst;
1231 bool link_trained;
1232 bool has_audio;
1233 bool reset_link_params;
1234 u8 dpcd[DP_RECEIVER_CAP_SIZE];
1235 u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
1236 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
1237 u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
1238 u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
1239 u8 fec_capable;
1240 /* source rates */
1241 int num_source_rates;
1242 const int *source_rates;
1243 /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
1244 int num_sink_rates;
1245 int sink_rates[DP_MAX_SUPPORTED_RATES];
1246 bool use_rate_select;
1247 /* intersection of source and sink rates */
1248 int num_common_rates;
1249 int common_rates[DP_MAX_SUPPORTED_RATES];
1250 /* Max lane count for the current link */
1251 int max_link_lane_count;
1252 /* Max rate for the current link */
1253 int max_link_rate;
1254 /* sink or branch descriptor */
1255 struct drm_dp_desc desc;
1256 struct drm_dp_aux aux;
1257 u32 aux_busy_last_status;
1258 u8 train_set[4];
1259 int panel_power_up_delay;
1260 int panel_power_down_delay;
1261 int panel_power_cycle_delay;
1262 int backlight_on_delay;
1263 int backlight_off_delay;
1264 struct delayed_work panel_vdd_work;
1265 bool want_panel_vdd;
1266 unsigned long last_power_on;
1267 unsigned long last_backlight_off;
1268 ktime_t panel_power_off_time;
1269
1270 struct notifier_block edp_notifier;
1271
1272 /*
1273 * Pipe whose power sequencer is currently locked into
1274 * this port. Only relevant on VLV/CHV.
1275 */
1276 enum pipe pps_pipe;
1277 /*
1278 * Pipe currently driving the port. Used for preventing
1279 * the use of the PPS for any pipe currentrly driving
1280 * external DP as that will mess things up on VLV.
1281 */
1282 enum pipe active_pipe;
1283 /*
1284 * Set if the sequencer may be reset due to a power transition,
1285 * requiring a reinitialization. Only relevant on BXT.
1286 */
1287 bool pps_reset;
1288 struct edp_power_seq pps_delays;
1289
1290 bool can_mst; /* this port supports mst */
1291 bool is_mst;
1292 int active_mst_links;
1293
1294 /*
1295 * DP_TP_* registers may be either on port or transcoder register space.
1296 */
1297 struct {
1298 i915_reg_t dp_tp_ctl;
1299 i915_reg_t dp_tp_status;
1300 } regs;
1301
1302 /* connector directly attached - won't be use for modeset in mst world */
1303 struct intel_connector *attached_connector;
1304
1305 /* mst connector list */
1306 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
1307 struct drm_dp_mst_topology_mgr mst_mgr;
1308
1309 u32 (*get_aux_clock_divider)(struct intel_dp *dp, int index);
1310 /*
1311 * This function returns the value we have to program the AUX_CTL
1312 * register with to kick off an AUX transaction.
1313 */
1314 u32 (*get_aux_send_ctl)(struct intel_dp *dp, int send_bytes,
1315 u32 aux_clock_divider);
1316
1317 i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp);
1318 i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);
1319
1320 /* This is called before a link training is starterd */
1321 void (*prepare_link_retrain)(struct intel_dp *intel_dp);
1322
1323 /* Displayport compliance testing */
1324 struct intel_dp_compliance compliance;
1325
1326 /* Display stream compression testing */
1327 bool force_dsc_en;
1328 };
1329
1330 enum lspcon_vendor {
1331 LSPCON_VENDOR_MCA,
1332 LSPCON_VENDOR_PARADE
1333 };
1334
1335 struct intel_lspcon {
1336 bool active;
1337 enum drm_lspcon_mode mode;
1338 enum lspcon_vendor vendor;
1339 };
1340
1341 struct intel_digital_port {
1342 struct intel_encoder base;
1343 u32 saved_port_bits;
1344 struct intel_dp dp;
1345 struct intel_hdmi hdmi;
1346 struct intel_lspcon lspcon;
1347 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1348 bool release_cl2_override;
1349 u8 max_lanes;
1350 /* Used for DP and ICL+ TypeC/DP and TypeC/HDMI ports. */
1351 enum aux_ch aux_ch;
1352 enum intel_display_power_domain ddi_io_power_domain;
1353 struct mutex tc_lock; /* protects the TypeC port mode */
1354 intel_wakeref_t tc_lock_wakeref;
1355 int tc_link_refcount;
1356 bool tc_legacy_port:1;
1357 char tc_port_name[8];
1358 enum tc_port_mode tc_mode;
1359 enum phy_fia tc_phy_fia;
1360 u8 tc_phy_fia_idx;
1361
1362 void (*write_infoframe)(struct intel_encoder *encoder,
1363 const struct intel_crtc_state *crtc_state,
1364 unsigned int type,
1365 const void *frame, ssize_t len);
1366 void (*read_infoframe)(struct intel_encoder *encoder,
1367 const struct intel_crtc_state *crtc_state,
1368 unsigned int type,
1369 void *frame, ssize_t len);
1370 void (*set_infoframes)(struct intel_encoder *encoder,
1371 bool enable,
1372 const struct intel_crtc_state *crtc_state,
1373 const struct drm_connector_state *conn_state);
1374 u32 (*infoframes_enabled)(struct intel_encoder *encoder,
1375 const struct intel_crtc_state *pipe_config);
1376 };
1377
1378 struct intel_dp_mst_encoder {
1379 struct intel_encoder base;
1380 enum pipe pipe;
1381 struct intel_digital_port *primary;
1382 struct intel_connector *connector;
1383 };
1384
1385 static inline enum dpio_channel
vlv_dport_to_channel(struct intel_digital_port * dport)1386 vlv_dport_to_channel(struct intel_digital_port *dport)
1387 {
1388 switch (dport->base.port) {
1389 case PORT_B:
1390 case PORT_D:
1391 return DPIO_CH0;
1392 case PORT_C:
1393 return DPIO_CH1;
1394 default:
1395 BUG();
1396 }
1397 }
1398
1399 static inline enum dpio_phy
vlv_dport_to_phy(struct intel_digital_port * dport)1400 vlv_dport_to_phy(struct intel_digital_port *dport)
1401 {
1402 switch (dport->base.port) {
1403 case PORT_B:
1404 case PORT_C:
1405 return DPIO_PHY0;
1406 case PORT_D:
1407 return DPIO_PHY1;
1408 default:
1409 BUG();
1410 }
1411 }
1412
1413 static inline enum dpio_channel
vlv_pipe_to_channel(enum pipe pipe)1414 vlv_pipe_to_channel(enum pipe pipe)
1415 {
1416 switch (pipe) {
1417 case PIPE_A:
1418 case PIPE_C:
1419 return DPIO_CH0;
1420 case PIPE_B:
1421 return DPIO_CH1;
1422 default:
1423 BUG();
1424 }
1425 }
1426
1427 static inline struct intel_crtc *
intel_get_crtc_for_pipe(struct drm_i915_private * dev_priv,enum pipe pipe)1428 intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1429 {
1430 return dev_priv->pipe_to_crtc_mapping[pipe];
1431 }
1432
1433 static inline struct intel_crtc *
intel_get_crtc_for_plane(struct drm_i915_private * dev_priv,enum i9xx_plane_id plane)1434 intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum i9xx_plane_id plane)
1435 {
1436 return dev_priv->plane_to_crtc_mapping[plane];
1437 }
1438
1439 struct intel_load_detect_pipe {
1440 struct drm_atomic_state *restore_state;
1441 };
1442
1443 static inline struct intel_encoder *
intel_attached_encoder(struct intel_connector * connector)1444 intel_attached_encoder(struct intel_connector *connector)
1445 {
1446 return connector->encoder;
1447 }
1448
intel_encoder_is_dig_port(struct intel_encoder * encoder)1449 static inline bool intel_encoder_is_dig_port(struct intel_encoder *encoder)
1450 {
1451 switch (encoder->type) {
1452 case INTEL_OUTPUT_DDI:
1453 case INTEL_OUTPUT_DP:
1454 case INTEL_OUTPUT_EDP:
1455 case INTEL_OUTPUT_HDMI:
1456 return true;
1457 default:
1458 return false;
1459 }
1460 }
1461
1462 static inline struct intel_digital_port *
enc_to_dig_port(struct intel_encoder * encoder)1463 enc_to_dig_port(struct intel_encoder *encoder)
1464 {
1465 struct intel_encoder *intel_encoder = encoder;
1466
1467 if (intel_encoder_is_dig_port(intel_encoder))
1468 return container_of(&encoder->base, struct intel_digital_port,
1469 base.base);
1470 else
1471 return NULL;
1472 }
1473
1474 static inline struct intel_digital_port *
conn_to_dig_port(struct intel_connector * connector)1475 conn_to_dig_port(struct intel_connector *connector)
1476 {
1477 return enc_to_dig_port(intel_attached_encoder(connector));
1478 }
1479
1480 static inline struct intel_dp_mst_encoder *
enc_to_mst(struct intel_encoder * encoder)1481 enc_to_mst(struct intel_encoder *encoder)
1482 {
1483 return container_of(&encoder->base, struct intel_dp_mst_encoder,
1484 base.base);
1485 }
1486
enc_to_intel_dp(struct intel_encoder * encoder)1487 static inline struct intel_dp *enc_to_intel_dp(struct intel_encoder *encoder)
1488 {
1489 return &enc_to_dig_port(encoder)->dp;
1490 }
1491
intel_encoder_is_dp(struct intel_encoder * encoder)1492 static inline bool intel_encoder_is_dp(struct intel_encoder *encoder)
1493 {
1494 switch (encoder->type) {
1495 case INTEL_OUTPUT_DP:
1496 case INTEL_OUTPUT_EDP:
1497 return true;
1498 case INTEL_OUTPUT_DDI:
1499 /* Skip pure HDMI/DVI DDI encoders */
1500 return i915_mmio_reg_valid(enc_to_intel_dp(encoder)->output_reg);
1501 default:
1502 return false;
1503 }
1504 }
1505
1506 static inline struct intel_lspcon *
enc_to_intel_lspcon(struct intel_encoder * encoder)1507 enc_to_intel_lspcon(struct intel_encoder *encoder)
1508 {
1509 return &enc_to_dig_port(encoder)->lspcon;
1510 }
1511
1512 static inline struct intel_digital_port *
dp_to_dig_port(struct intel_dp * intel_dp)1513 dp_to_dig_port(struct intel_dp *intel_dp)
1514 {
1515 return container_of(intel_dp, struct intel_digital_port, dp);
1516 }
1517
1518 static inline struct intel_lspcon *
dp_to_lspcon(struct intel_dp * intel_dp)1519 dp_to_lspcon(struct intel_dp *intel_dp)
1520 {
1521 return &dp_to_dig_port(intel_dp)->lspcon;
1522 }
1523
1524 static inline struct drm_i915_private *
dp_to_i915(struct intel_dp * intel_dp)1525 dp_to_i915(struct intel_dp *intel_dp)
1526 {
1527 return to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
1528 }
1529
1530 static inline struct intel_digital_port *
hdmi_to_dig_port(struct intel_hdmi * intel_hdmi)1531 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1532 {
1533 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1534 }
1535
1536 static inline struct intel_plane_state *
intel_atomic_get_plane_state(struct intel_atomic_state * state,struct intel_plane * plane)1537 intel_atomic_get_plane_state(struct intel_atomic_state *state,
1538 struct intel_plane *plane)
1539 {
1540 struct drm_plane_state *ret =
1541 drm_atomic_get_plane_state(&state->base, &plane->base);
1542
1543 if (IS_ERR(ret))
1544 return ERR_CAST(ret);
1545
1546 return to_intel_plane_state(ret);
1547 }
1548
1549 static inline struct intel_plane_state *
intel_atomic_get_old_plane_state(struct intel_atomic_state * state,struct intel_plane * plane)1550 intel_atomic_get_old_plane_state(struct intel_atomic_state *state,
1551 struct intel_plane *plane)
1552 {
1553 return to_intel_plane_state(drm_atomic_get_old_plane_state(&state->base,
1554 &plane->base));
1555 }
1556
1557 static inline struct intel_plane_state *
intel_atomic_get_new_plane_state(struct intel_atomic_state * state,struct intel_plane * plane)1558 intel_atomic_get_new_plane_state(struct intel_atomic_state *state,
1559 struct intel_plane *plane)
1560 {
1561 return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base,
1562 &plane->base));
1563 }
1564
1565 static inline struct intel_crtc_state *
intel_atomic_get_old_crtc_state(struct intel_atomic_state * state,struct intel_crtc * crtc)1566 intel_atomic_get_old_crtc_state(struct intel_atomic_state *state,
1567 struct intel_crtc *crtc)
1568 {
1569 return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base,
1570 &crtc->base));
1571 }
1572
1573 static inline struct intel_crtc_state *
intel_atomic_get_new_crtc_state(struct intel_atomic_state * state,struct intel_crtc * crtc)1574 intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
1575 struct intel_crtc *crtc)
1576 {
1577 return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base,
1578 &crtc->base));
1579 }
1580
1581 static inline struct intel_digital_connector_state *
intel_atomic_get_new_connector_state(struct intel_atomic_state * state,struct intel_connector * connector)1582 intel_atomic_get_new_connector_state(struct intel_atomic_state *state,
1583 struct intel_connector *connector)
1584 {
1585 return to_intel_digital_connector_state(
1586 drm_atomic_get_new_connector_state(&state->base,
1587 &connector->base));
1588 }
1589
1590 static inline struct intel_digital_connector_state *
intel_atomic_get_old_connector_state(struct intel_atomic_state * state,struct intel_connector * connector)1591 intel_atomic_get_old_connector_state(struct intel_atomic_state *state,
1592 struct intel_connector *connector)
1593 {
1594 return to_intel_digital_connector_state(
1595 drm_atomic_get_old_connector_state(&state->base,
1596 &connector->base));
1597 }
1598
1599 /* intel_display.c */
1600 static inline bool
intel_crtc_has_type(const struct intel_crtc_state * crtc_state,enum intel_output_type type)1601 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1602 enum intel_output_type type)
1603 {
1604 return crtc_state->output_types & (1 << type);
1605 }
1606 static inline bool
intel_crtc_has_dp_encoder(const struct intel_crtc_state * crtc_state)1607 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1608 {
1609 return crtc_state->output_types &
1610 ((1 << INTEL_OUTPUT_DP) |
1611 (1 << INTEL_OUTPUT_DP_MST) |
1612 (1 << INTEL_OUTPUT_EDP));
1613 }
1614 static inline void
intel_wait_for_vblank(struct drm_i915_private * dev_priv,enum pipe pipe)1615 intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
1616 {
1617 drm_wait_one_vblank(&dev_priv->drm, pipe);
1618 }
1619 static inline void
intel_wait_for_vblank_if_active(struct drm_i915_private * dev_priv,enum pipe pipe)1620 intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, enum pipe pipe)
1621 {
1622 const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1623
1624 if (crtc->active)
1625 intel_wait_for_vblank(dev_priv, pipe);
1626 }
1627
intel_plane_ggtt_offset(const struct intel_plane_state * state)1628 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
1629 {
1630 return i915_ggtt_offset(state->vma);
1631 }
1632
1633 #endif /* __INTEL_DISPLAY_TYPES_H__ */
1634