1 /* $NetBSD: interrupt.c,v 1.2 2021/12/18 23:45:31 riastradh Exp $ */
2
3 /*
4 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Kevin Tian <kevin.tian@intel.com>
27 * Zhi Wang <zhi.a.wang@intel.com>
28 *
29 * Contributors:
30 * Min he <min.he@intel.com>
31 *
32 */
33
34 #include <sys/cdefs.h>
35 __KERNEL_RCSID(0, "$NetBSD: interrupt.c,v 1.2 2021/12/18 23:45:31 riastradh Exp $");
36
37 #include "i915_drv.h"
38 #include "gvt.h"
39 #include "trace.h"
40
41 /* common offset among interrupt control registers */
42 #define regbase_to_isr(base) (base)
43 #define regbase_to_imr(base) (base + 0x4)
44 #define regbase_to_iir(base) (base + 0x8)
45 #define regbase_to_ier(base) (base + 0xC)
46
47 #define iir_to_regbase(iir) (iir - 0x8)
48 #define ier_to_regbase(ier) (ier - 0xC)
49
50 #define get_event_virt_handler(irq, e) (irq->events[e].v_handler)
51 #define get_irq_info(irq, e) (irq->events[e].info)
52
53 #define irq_to_gvt(irq) \
54 container_of(irq, struct intel_gvt, irq)
55
56 static void update_upstream_irq(struct intel_vgpu *vgpu,
57 struct intel_gvt_irq_info *info);
58
59 static const char * const irq_name[INTEL_GVT_EVENT_MAX] = {
60 [RCS_MI_USER_INTERRUPT] = "Render CS MI USER INTERRUPT",
61 [RCS_DEBUG] = "Render EU debug from SVG",
62 [RCS_MMIO_SYNC_FLUSH] = "Render MMIO sync flush status",
63 [RCS_CMD_STREAMER_ERR] = "Render CS error interrupt",
64 [RCS_PIPE_CONTROL] = "Render PIPE CONTROL notify",
65 [RCS_WATCHDOG_EXCEEDED] = "Render CS Watchdog counter exceeded",
66 [RCS_PAGE_DIRECTORY_FAULT] = "Render page directory faults",
67 [RCS_AS_CONTEXT_SWITCH] = "Render AS Context Switch Interrupt",
68
69 [VCS_MI_USER_INTERRUPT] = "Video CS MI USER INTERRUPT",
70 [VCS_MMIO_SYNC_FLUSH] = "Video MMIO sync flush status",
71 [VCS_CMD_STREAMER_ERR] = "Video CS error interrupt",
72 [VCS_MI_FLUSH_DW] = "Video MI FLUSH DW notify",
73 [VCS_WATCHDOG_EXCEEDED] = "Video CS Watchdog counter exceeded",
74 [VCS_PAGE_DIRECTORY_FAULT] = "Video page directory faults",
75 [VCS_AS_CONTEXT_SWITCH] = "Video AS Context Switch Interrupt",
76 [VCS2_MI_USER_INTERRUPT] = "VCS2 Video CS MI USER INTERRUPT",
77 [VCS2_MI_FLUSH_DW] = "VCS2 Video MI FLUSH DW notify",
78 [VCS2_AS_CONTEXT_SWITCH] = "VCS2 Context Switch Interrupt",
79
80 [BCS_MI_USER_INTERRUPT] = "Blitter CS MI USER INTERRUPT",
81 [BCS_MMIO_SYNC_FLUSH] = "Billter MMIO sync flush status",
82 [BCS_CMD_STREAMER_ERR] = "Blitter CS error interrupt",
83 [BCS_MI_FLUSH_DW] = "Blitter MI FLUSH DW notify",
84 [BCS_PAGE_DIRECTORY_FAULT] = "Blitter page directory faults",
85 [BCS_AS_CONTEXT_SWITCH] = "Blitter AS Context Switch Interrupt",
86
87 [VECS_MI_FLUSH_DW] = "Video Enhanced Streamer MI FLUSH DW notify",
88 [VECS_AS_CONTEXT_SWITCH] = "VECS Context Switch Interrupt",
89
90 [PIPE_A_FIFO_UNDERRUN] = "Pipe A FIFO underrun",
91 [PIPE_A_CRC_ERR] = "Pipe A CRC error",
92 [PIPE_A_CRC_DONE] = "Pipe A CRC done",
93 [PIPE_A_VSYNC] = "Pipe A vsync",
94 [PIPE_A_LINE_COMPARE] = "Pipe A line compare",
95 [PIPE_A_ODD_FIELD] = "Pipe A odd field",
96 [PIPE_A_EVEN_FIELD] = "Pipe A even field",
97 [PIPE_A_VBLANK] = "Pipe A vblank",
98 [PIPE_B_FIFO_UNDERRUN] = "Pipe B FIFO underrun",
99 [PIPE_B_CRC_ERR] = "Pipe B CRC error",
100 [PIPE_B_CRC_DONE] = "Pipe B CRC done",
101 [PIPE_B_VSYNC] = "Pipe B vsync",
102 [PIPE_B_LINE_COMPARE] = "Pipe B line compare",
103 [PIPE_B_ODD_FIELD] = "Pipe B odd field",
104 [PIPE_B_EVEN_FIELD] = "Pipe B even field",
105 [PIPE_B_VBLANK] = "Pipe B vblank",
106 [PIPE_C_VBLANK] = "Pipe C vblank",
107 [DPST_PHASE_IN] = "DPST phase in event",
108 [DPST_HISTOGRAM] = "DPST histogram event",
109 [GSE] = "GSE",
110 [DP_A_HOTPLUG] = "DP A Hotplug",
111 [AUX_CHANNEL_A] = "AUX Channel A",
112 [PERF_COUNTER] = "Performance counter",
113 [POISON] = "Poison",
114 [GTT_FAULT] = "GTT fault",
115 [PRIMARY_A_FLIP_DONE] = "Primary Plane A flip done",
116 [PRIMARY_B_FLIP_DONE] = "Primary Plane B flip done",
117 [PRIMARY_C_FLIP_DONE] = "Primary Plane C flip done",
118 [SPRITE_A_FLIP_DONE] = "Sprite Plane A flip done",
119 [SPRITE_B_FLIP_DONE] = "Sprite Plane B flip done",
120 [SPRITE_C_FLIP_DONE] = "Sprite Plane C flip done",
121
122 [PCU_THERMAL] = "PCU Thermal Event",
123 [PCU_PCODE2DRIVER_MAILBOX] = "PCU pcode2driver mailbox event",
124
125 [FDI_RX_INTERRUPTS_TRANSCODER_A] = "FDI RX Interrupts Combined A",
126 [AUDIO_CP_CHANGE_TRANSCODER_A] = "Audio CP Change Transcoder A",
127 [AUDIO_CP_REQUEST_TRANSCODER_A] = "Audio CP Request Transcoder A",
128 [FDI_RX_INTERRUPTS_TRANSCODER_B] = "FDI RX Interrupts Combined B",
129 [AUDIO_CP_CHANGE_TRANSCODER_B] = "Audio CP Change Transcoder B",
130 [AUDIO_CP_REQUEST_TRANSCODER_B] = "Audio CP Request Transcoder B",
131 [FDI_RX_INTERRUPTS_TRANSCODER_C] = "FDI RX Interrupts Combined C",
132 [AUDIO_CP_CHANGE_TRANSCODER_C] = "Audio CP Change Transcoder C",
133 [AUDIO_CP_REQUEST_TRANSCODER_C] = "Audio CP Request Transcoder C",
134 [ERR_AND_DBG] = "South Error and Debug Interrupts Combined",
135 [GMBUS] = "Gmbus",
136 [SDVO_B_HOTPLUG] = "SDVO B hotplug",
137 [CRT_HOTPLUG] = "CRT Hotplug",
138 [DP_B_HOTPLUG] = "DisplayPort/HDMI/DVI B Hotplug",
139 [DP_C_HOTPLUG] = "DisplayPort/HDMI/DVI C Hotplug",
140 [DP_D_HOTPLUG] = "DisplayPort/HDMI/DVI D Hotplug",
141 [AUX_CHANNEL_B] = "AUX Channel B",
142 [AUX_CHANNEL_C] = "AUX Channel C",
143 [AUX_CHANNEL_D] = "AUX Channel D",
144 [AUDIO_POWER_STATE_CHANGE_B] = "Audio Power State change Port B",
145 [AUDIO_POWER_STATE_CHANGE_C] = "Audio Power State change Port C",
146 [AUDIO_POWER_STATE_CHANGE_D] = "Audio Power State change Port D",
147
148 [INTEL_GVT_EVENT_RESERVED] = "RESERVED EVENTS!!!",
149 };
150
regbase_to_irq_info(struct intel_gvt * gvt,unsigned int reg)151 static inline struct intel_gvt_irq_info *regbase_to_irq_info(
152 struct intel_gvt *gvt,
153 unsigned int reg)
154 {
155 struct intel_gvt_irq *irq = &gvt->irq;
156 int i;
157
158 for_each_set_bit(i, irq->irq_info_bitmap, INTEL_GVT_IRQ_INFO_MAX) {
159 if (i915_mmio_reg_offset(irq->info[i]->reg_base) == reg)
160 return irq->info[i];
161 }
162
163 return NULL;
164 }
165
166 /**
167 * intel_vgpu_reg_imr_handler - Generic IMR register emulation write handler
168 * @vgpu: a vGPU
169 * @reg: register offset written by guest
170 * @p_data: register data written by guest
171 * @bytes: register data length
172 *
173 * This function is used to emulate the generic IMR register bit change
174 * behavior.
175 *
176 * Returns:
177 * Zero on success, negative error code if failed.
178 *
179 */
intel_vgpu_reg_imr_handler(struct intel_vgpu * vgpu,unsigned int reg,void * p_data,unsigned int bytes)180 int intel_vgpu_reg_imr_handler(struct intel_vgpu *vgpu,
181 unsigned int reg, void *p_data, unsigned int bytes)
182 {
183 struct intel_gvt *gvt = vgpu->gvt;
184 struct intel_gvt_irq_ops *ops = gvt->irq.ops;
185 u32 imr = *(u32 *)p_data;
186
187 trace_write_ir(vgpu->id, "IMR", reg, imr, vgpu_vreg(vgpu, reg),
188 (vgpu_vreg(vgpu, reg) ^ imr));
189
190 vgpu_vreg(vgpu, reg) = imr;
191
192 ops->check_pending_irq(vgpu);
193
194 return 0;
195 }
196
197 /**
198 * intel_vgpu_reg_master_irq_handler - master IRQ write emulation handler
199 * @vgpu: a vGPU
200 * @reg: register offset written by guest
201 * @p_data: register data written by guest
202 * @bytes: register data length
203 *
204 * This function is used to emulate the master IRQ register on gen8+.
205 *
206 * Returns:
207 * Zero on success, negative error code if failed.
208 *
209 */
intel_vgpu_reg_master_irq_handler(struct intel_vgpu * vgpu,unsigned int reg,void * p_data,unsigned int bytes)210 int intel_vgpu_reg_master_irq_handler(struct intel_vgpu *vgpu,
211 unsigned int reg, void *p_data, unsigned int bytes)
212 {
213 struct intel_gvt *gvt = vgpu->gvt;
214 struct intel_gvt_irq_ops *ops = gvt->irq.ops;
215 u32 ier = *(u32 *)p_data;
216 u32 virtual_ier = vgpu_vreg(vgpu, reg);
217
218 trace_write_ir(vgpu->id, "MASTER_IRQ", reg, ier, virtual_ier,
219 (virtual_ier ^ ier));
220
221 /*
222 * GEN8_MASTER_IRQ is a special irq register,
223 * only bit 31 is allowed to be modified
224 * and treated as an IER bit.
225 */
226 ier &= GEN8_MASTER_IRQ_CONTROL;
227 virtual_ier &= GEN8_MASTER_IRQ_CONTROL;
228 vgpu_vreg(vgpu, reg) &= ~GEN8_MASTER_IRQ_CONTROL;
229 vgpu_vreg(vgpu, reg) |= ier;
230
231 ops->check_pending_irq(vgpu);
232
233 return 0;
234 }
235
236 /**
237 * intel_vgpu_reg_ier_handler - Generic IER write emulation handler
238 * @vgpu: a vGPU
239 * @reg: register offset written by guest
240 * @p_data: register data written by guest
241 * @bytes: register data length
242 *
243 * This function is used to emulate the generic IER register behavior.
244 *
245 * Returns:
246 * Zero on success, negative error code if failed.
247 *
248 */
intel_vgpu_reg_ier_handler(struct intel_vgpu * vgpu,unsigned int reg,void * p_data,unsigned int bytes)249 int intel_vgpu_reg_ier_handler(struct intel_vgpu *vgpu,
250 unsigned int reg, void *p_data, unsigned int bytes)
251 {
252 struct intel_gvt *gvt = vgpu->gvt;
253 struct intel_gvt_irq_ops *ops = gvt->irq.ops;
254 struct intel_gvt_irq_info *info;
255 u32 ier = *(u32 *)p_data;
256
257 trace_write_ir(vgpu->id, "IER", reg, ier, vgpu_vreg(vgpu, reg),
258 (vgpu_vreg(vgpu, reg) ^ ier));
259
260 vgpu_vreg(vgpu, reg) = ier;
261
262 info = regbase_to_irq_info(gvt, ier_to_regbase(reg));
263 if (WARN_ON(!info))
264 return -EINVAL;
265
266 if (info->has_upstream_irq)
267 update_upstream_irq(vgpu, info);
268
269 ops->check_pending_irq(vgpu);
270
271 return 0;
272 }
273
274 /**
275 * intel_vgpu_reg_iir_handler - Generic IIR write emulation handler
276 * @vgpu: a vGPU
277 * @reg: register offset written by guest
278 * @p_data: register data written by guest
279 * @bytes: register data length
280 *
281 * This function is used to emulate the generic IIR register behavior.
282 *
283 * Returns:
284 * Zero on success, negative error code if failed.
285 *
286 */
intel_vgpu_reg_iir_handler(struct intel_vgpu * vgpu,unsigned int reg,void * p_data,unsigned int bytes)287 int intel_vgpu_reg_iir_handler(struct intel_vgpu *vgpu, unsigned int reg,
288 void *p_data, unsigned int bytes)
289 {
290 struct intel_gvt_irq_info *info = regbase_to_irq_info(vgpu->gvt,
291 iir_to_regbase(reg));
292 u32 iir = *(u32 *)p_data;
293
294 trace_write_ir(vgpu->id, "IIR", reg, iir, vgpu_vreg(vgpu, reg),
295 (vgpu_vreg(vgpu, reg) ^ iir));
296
297 if (WARN_ON(!info))
298 return -EINVAL;
299
300 vgpu_vreg(vgpu, reg) &= ~iir;
301
302 if (info->has_upstream_irq)
303 update_upstream_irq(vgpu, info);
304 return 0;
305 }
306
307 static struct intel_gvt_irq_map gen8_irq_map[] = {
308 { INTEL_GVT_IRQ_INFO_MASTER, 0, INTEL_GVT_IRQ_INFO_GT0, 0xffff },
309 { INTEL_GVT_IRQ_INFO_MASTER, 1, INTEL_GVT_IRQ_INFO_GT0, 0xffff0000 },
310 { INTEL_GVT_IRQ_INFO_MASTER, 2, INTEL_GVT_IRQ_INFO_GT1, 0xffff },
311 { INTEL_GVT_IRQ_INFO_MASTER, 3, INTEL_GVT_IRQ_INFO_GT1, 0xffff0000 },
312 { INTEL_GVT_IRQ_INFO_MASTER, 4, INTEL_GVT_IRQ_INFO_GT2, 0xffff },
313 { INTEL_GVT_IRQ_INFO_MASTER, 6, INTEL_GVT_IRQ_INFO_GT3, 0xffff },
314 { INTEL_GVT_IRQ_INFO_MASTER, 16, INTEL_GVT_IRQ_INFO_DE_PIPE_A, ~0 },
315 { INTEL_GVT_IRQ_INFO_MASTER, 17, INTEL_GVT_IRQ_INFO_DE_PIPE_B, ~0 },
316 { INTEL_GVT_IRQ_INFO_MASTER, 18, INTEL_GVT_IRQ_INFO_DE_PIPE_C, ~0 },
317 { INTEL_GVT_IRQ_INFO_MASTER, 20, INTEL_GVT_IRQ_INFO_DE_PORT, ~0 },
318 { INTEL_GVT_IRQ_INFO_MASTER, 22, INTEL_GVT_IRQ_INFO_DE_MISC, ~0 },
319 { INTEL_GVT_IRQ_INFO_MASTER, 23, INTEL_GVT_IRQ_INFO_PCH, ~0 },
320 { INTEL_GVT_IRQ_INFO_MASTER, 30, INTEL_GVT_IRQ_INFO_PCU, ~0 },
321 { -1, -1, ~0 },
322 };
323
update_upstream_irq(struct intel_vgpu * vgpu,struct intel_gvt_irq_info * info)324 static void update_upstream_irq(struct intel_vgpu *vgpu,
325 struct intel_gvt_irq_info *info)
326 {
327 struct intel_gvt_irq *irq = &vgpu->gvt->irq;
328 struct intel_gvt_irq_map *map = irq->irq_map;
329 struct intel_gvt_irq_info *up_irq_info = NULL;
330 u32 set_bits = 0;
331 u32 clear_bits = 0;
332 int bit;
333 u32 val = vgpu_vreg(vgpu,
334 regbase_to_iir(i915_mmio_reg_offset(info->reg_base)))
335 & vgpu_vreg(vgpu,
336 regbase_to_ier(i915_mmio_reg_offset(info->reg_base)));
337
338 if (!info->has_upstream_irq)
339 return;
340
341 for (map = irq->irq_map; map->up_irq_bit != -1; map++) {
342 if (info->group != map->down_irq_group)
343 continue;
344
345 if (!up_irq_info)
346 up_irq_info = irq->info[map->up_irq_group];
347 else
348 WARN_ON(up_irq_info != irq->info[map->up_irq_group]);
349
350 bit = map->up_irq_bit;
351
352 if (val & map->down_irq_bitmask)
353 set_bits |= (1 << bit);
354 else
355 clear_bits |= (1 << bit);
356 }
357
358 if (WARN_ON(!up_irq_info))
359 return;
360
361 if (up_irq_info->group == INTEL_GVT_IRQ_INFO_MASTER) {
362 u32 isr = i915_mmio_reg_offset(up_irq_info->reg_base);
363
364 vgpu_vreg(vgpu, isr) &= ~clear_bits;
365 vgpu_vreg(vgpu, isr) |= set_bits;
366 } else {
367 u32 iir = regbase_to_iir(
368 i915_mmio_reg_offset(up_irq_info->reg_base));
369 u32 imr = regbase_to_imr(
370 i915_mmio_reg_offset(up_irq_info->reg_base));
371
372 vgpu_vreg(vgpu, iir) |= (set_bits & ~vgpu_vreg(vgpu, imr));
373 }
374
375 if (up_irq_info->has_upstream_irq)
376 update_upstream_irq(vgpu, up_irq_info);
377 }
378
init_irq_map(struct intel_gvt_irq * irq)379 static void init_irq_map(struct intel_gvt_irq *irq)
380 {
381 struct intel_gvt_irq_map *map;
382 struct intel_gvt_irq_info *up_info, *down_info;
383 int up_bit;
384
385 for (map = irq->irq_map; map->up_irq_bit != -1; map++) {
386 up_info = irq->info[map->up_irq_group];
387 up_bit = map->up_irq_bit;
388 down_info = irq->info[map->down_irq_group];
389
390 set_bit(up_bit, up_info->downstream_irq_bitmap);
391 down_info->has_upstream_irq = true;
392
393 gvt_dbg_irq("[up] grp %d bit %d -> [down] grp %d bitmask %x\n",
394 up_info->group, up_bit,
395 down_info->group, map->down_irq_bitmask);
396 }
397 }
398
399 /* =======================vEvent injection===================== */
inject_virtual_interrupt(struct intel_vgpu * vgpu)400 static int inject_virtual_interrupt(struct intel_vgpu *vgpu)
401 {
402 return intel_gvt_hypervisor_inject_msi(vgpu);
403 }
404
propagate_event(struct intel_gvt_irq * irq,enum intel_gvt_event_type event,struct intel_vgpu * vgpu)405 static void propagate_event(struct intel_gvt_irq *irq,
406 enum intel_gvt_event_type event, struct intel_vgpu *vgpu)
407 {
408 struct intel_gvt_irq_info *info;
409 unsigned int reg_base;
410 int bit;
411
412 info = get_irq_info(irq, event);
413 if (WARN_ON(!info))
414 return;
415
416 reg_base = i915_mmio_reg_offset(info->reg_base);
417 bit = irq->events[event].bit;
418
419 if (!test_bit(bit, (void *)&vgpu_vreg(vgpu,
420 regbase_to_imr(reg_base)))) {
421 trace_propagate_event(vgpu->id, irq_name[event], bit);
422 set_bit(bit, (void *)&vgpu_vreg(vgpu,
423 regbase_to_iir(reg_base)));
424 }
425 }
426
427 /* =======================vEvent Handlers===================== */
handle_default_event_virt(struct intel_gvt_irq * irq,enum intel_gvt_event_type event,struct intel_vgpu * vgpu)428 static void handle_default_event_virt(struct intel_gvt_irq *irq,
429 enum intel_gvt_event_type event, struct intel_vgpu *vgpu)
430 {
431 if (!vgpu->irq.irq_warn_once[event]) {
432 gvt_dbg_core("vgpu%d: IRQ receive event %d (%s)\n",
433 vgpu->id, event, irq_name[event]);
434 vgpu->irq.irq_warn_once[event] = true;
435 }
436 propagate_event(irq, event, vgpu);
437 }
438
439 /* =====================GEN specific logic======================= */
440 /* GEN8 interrupt routines. */
441
442 #define DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(regname, regbase) \
443 static struct intel_gvt_irq_info gen8_##regname##_info = { \
444 .name = #regname"-IRQ", \
445 .reg_base = (regbase), \
446 .bit_to_event = {[0 ... INTEL_GVT_IRQ_BITWIDTH-1] = \
447 INTEL_GVT_EVENT_RESERVED}, \
448 }
449
450 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(gt0, GEN8_GT_ISR(0));
451 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(gt1, GEN8_GT_ISR(1));
452 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(gt2, GEN8_GT_ISR(2));
453 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(gt3, GEN8_GT_ISR(3));
454 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_pipe_a, GEN8_DE_PIPE_ISR(PIPE_A));
455 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_pipe_b, GEN8_DE_PIPE_ISR(PIPE_B));
456 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_pipe_c, GEN8_DE_PIPE_ISR(PIPE_C));
457 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_port, GEN8_DE_PORT_ISR);
458 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_misc, GEN8_DE_MISC_ISR);
459 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(pcu, GEN8_PCU_ISR);
460 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(master, GEN8_MASTER_IRQ);
461
462 static struct intel_gvt_irq_info gvt_base_pch_info = {
463 .name = "PCH-IRQ",
464 .reg_base = SDEISR,
465 .bit_to_event = {[0 ... INTEL_GVT_IRQ_BITWIDTH-1] =
466 INTEL_GVT_EVENT_RESERVED},
467 };
468
gen8_check_pending_irq(struct intel_vgpu * vgpu)469 static void gen8_check_pending_irq(struct intel_vgpu *vgpu)
470 {
471 struct intel_gvt_irq *irq = &vgpu->gvt->irq;
472 int i;
473
474 if (!(vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ)) &
475 GEN8_MASTER_IRQ_CONTROL))
476 return;
477
478 for_each_set_bit(i, irq->irq_info_bitmap, INTEL_GVT_IRQ_INFO_MAX) {
479 struct intel_gvt_irq_info *info = irq->info[i];
480 u32 reg_base;
481
482 if (!info->has_upstream_irq)
483 continue;
484
485 reg_base = i915_mmio_reg_offset(info->reg_base);
486 if ((vgpu_vreg(vgpu, regbase_to_iir(reg_base))
487 & vgpu_vreg(vgpu, regbase_to_ier(reg_base))))
488 update_upstream_irq(vgpu, info);
489 }
490
491 if (vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ))
492 & ~GEN8_MASTER_IRQ_CONTROL)
493 inject_virtual_interrupt(vgpu);
494 }
495
gen8_init_irq(struct intel_gvt_irq * irq)496 static void gen8_init_irq(
497 struct intel_gvt_irq *irq)
498 {
499 struct intel_gvt *gvt = irq_to_gvt(irq);
500
501 #define SET_BIT_INFO(s, b, e, i) \
502 do { \
503 s->events[e].bit = b; \
504 s->events[e].info = s->info[i]; \
505 s->info[i]->bit_to_event[b] = e;\
506 } while (0)
507
508 #define SET_IRQ_GROUP(s, g, i) \
509 do { \
510 s->info[g] = i; \
511 (i)->group = g; \
512 set_bit(g, s->irq_info_bitmap); \
513 } while (0)
514
515 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_MASTER, &gen8_master_info);
516 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_GT0, &gen8_gt0_info);
517 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_GT1, &gen8_gt1_info);
518 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_GT2, &gen8_gt2_info);
519 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_GT3, &gen8_gt3_info);
520 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_PIPE_A, &gen8_de_pipe_a_info);
521 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_PIPE_B, &gen8_de_pipe_b_info);
522 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_PIPE_C, &gen8_de_pipe_c_info);
523 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_PORT, &gen8_de_port_info);
524 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_MISC, &gen8_de_misc_info);
525 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_PCU, &gen8_pcu_info);
526 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_PCH, &gvt_base_pch_info);
527
528 /* GEN8 level 2 interrupts. */
529
530 /* GEN8 interrupt GT0 events */
531 SET_BIT_INFO(irq, 0, RCS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT0);
532 SET_BIT_INFO(irq, 4, RCS_PIPE_CONTROL, INTEL_GVT_IRQ_INFO_GT0);
533 SET_BIT_INFO(irq, 8, RCS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT0);
534
535 SET_BIT_INFO(irq, 16, BCS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT0);
536 SET_BIT_INFO(irq, 20, BCS_MI_FLUSH_DW, INTEL_GVT_IRQ_INFO_GT0);
537 SET_BIT_INFO(irq, 24, BCS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT0);
538
539 /* GEN8 interrupt GT1 events */
540 SET_BIT_INFO(irq, 0, VCS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT1);
541 SET_BIT_INFO(irq, 4, VCS_MI_FLUSH_DW, INTEL_GVT_IRQ_INFO_GT1);
542 SET_BIT_INFO(irq, 8, VCS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT1);
543
544 if (HAS_ENGINE(gvt->dev_priv, VCS1)) {
545 SET_BIT_INFO(irq, 16, VCS2_MI_USER_INTERRUPT,
546 INTEL_GVT_IRQ_INFO_GT1);
547 SET_BIT_INFO(irq, 20, VCS2_MI_FLUSH_DW,
548 INTEL_GVT_IRQ_INFO_GT1);
549 SET_BIT_INFO(irq, 24, VCS2_AS_CONTEXT_SWITCH,
550 INTEL_GVT_IRQ_INFO_GT1);
551 }
552
553 /* GEN8 interrupt GT3 events */
554 SET_BIT_INFO(irq, 0, VECS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT3);
555 SET_BIT_INFO(irq, 4, VECS_MI_FLUSH_DW, INTEL_GVT_IRQ_INFO_GT3);
556 SET_BIT_INFO(irq, 8, VECS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT3);
557
558 SET_BIT_INFO(irq, 0, PIPE_A_VBLANK, INTEL_GVT_IRQ_INFO_DE_PIPE_A);
559 SET_BIT_INFO(irq, 0, PIPE_B_VBLANK, INTEL_GVT_IRQ_INFO_DE_PIPE_B);
560 SET_BIT_INFO(irq, 0, PIPE_C_VBLANK, INTEL_GVT_IRQ_INFO_DE_PIPE_C);
561
562 /* GEN8 interrupt DE PORT events */
563 SET_BIT_INFO(irq, 0, AUX_CHANNEL_A, INTEL_GVT_IRQ_INFO_DE_PORT);
564 SET_BIT_INFO(irq, 3, DP_A_HOTPLUG, INTEL_GVT_IRQ_INFO_DE_PORT);
565
566 /* GEN8 interrupt DE MISC events */
567 SET_BIT_INFO(irq, 0, GSE, INTEL_GVT_IRQ_INFO_DE_MISC);
568
569 /* PCH events */
570 SET_BIT_INFO(irq, 17, GMBUS, INTEL_GVT_IRQ_INFO_PCH);
571 SET_BIT_INFO(irq, 19, CRT_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH);
572 SET_BIT_INFO(irq, 21, DP_B_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH);
573 SET_BIT_INFO(irq, 22, DP_C_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH);
574 SET_BIT_INFO(irq, 23, DP_D_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH);
575
576 if (IS_BROADWELL(gvt->dev_priv)) {
577 SET_BIT_INFO(irq, 25, AUX_CHANNEL_B, INTEL_GVT_IRQ_INFO_PCH);
578 SET_BIT_INFO(irq, 26, AUX_CHANNEL_C, INTEL_GVT_IRQ_INFO_PCH);
579 SET_BIT_INFO(irq, 27, AUX_CHANNEL_D, INTEL_GVT_IRQ_INFO_PCH);
580
581 SET_BIT_INFO(irq, 4, PRIMARY_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A);
582 SET_BIT_INFO(irq, 5, SPRITE_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A);
583
584 SET_BIT_INFO(irq, 4, PRIMARY_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B);
585 SET_BIT_INFO(irq, 5, SPRITE_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B);
586
587 SET_BIT_INFO(irq, 4, PRIMARY_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C);
588 SET_BIT_INFO(irq, 5, SPRITE_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C);
589 } else if (INTEL_GEN(gvt->dev_priv) >= 9) {
590 SET_BIT_INFO(irq, 25, AUX_CHANNEL_B, INTEL_GVT_IRQ_INFO_DE_PORT);
591 SET_BIT_INFO(irq, 26, AUX_CHANNEL_C, INTEL_GVT_IRQ_INFO_DE_PORT);
592 SET_BIT_INFO(irq, 27, AUX_CHANNEL_D, INTEL_GVT_IRQ_INFO_DE_PORT);
593
594 SET_BIT_INFO(irq, 3, PRIMARY_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A);
595 SET_BIT_INFO(irq, 3, PRIMARY_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B);
596 SET_BIT_INFO(irq, 3, PRIMARY_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C);
597
598 SET_BIT_INFO(irq, 4, SPRITE_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A);
599 SET_BIT_INFO(irq, 4, SPRITE_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B);
600 SET_BIT_INFO(irq, 4, SPRITE_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C);
601 }
602
603 /* GEN8 interrupt PCU events */
604 SET_BIT_INFO(irq, 24, PCU_THERMAL, INTEL_GVT_IRQ_INFO_PCU);
605 SET_BIT_INFO(irq, 25, PCU_PCODE2DRIVER_MAILBOX, INTEL_GVT_IRQ_INFO_PCU);
606 }
607
608 static struct intel_gvt_irq_ops gen8_irq_ops = {
609 .init_irq = gen8_init_irq,
610 .check_pending_irq = gen8_check_pending_irq,
611 };
612
613 /**
614 * intel_vgpu_trigger_virtual_event - Trigger a virtual event for a vGPU
615 * @vgpu: a vGPU
616 * @event: interrupt event
617 *
618 * This function is used to trigger a virtual interrupt event for vGPU.
619 * The caller provides the event to be triggered, the framework itself
620 * will emulate the IRQ register bit change.
621 *
622 */
intel_vgpu_trigger_virtual_event(struct intel_vgpu * vgpu,enum intel_gvt_event_type event)623 void intel_vgpu_trigger_virtual_event(struct intel_vgpu *vgpu,
624 enum intel_gvt_event_type event)
625 {
626 struct intel_gvt *gvt = vgpu->gvt;
627 struct intel_gvt_irq *irq = &gvt->irq;
628 gvt_event_virt_handler_t handler;
629 struct intel_gvt_irq_ops *ops = gvt->irq.ops;
630
631 handler = get_event_virt_handler(irq, event);
632 WARN_ON(!handler);
633
634 handler(irq, event, vgpu);
635
636 ops->check_pending_irq(vgpu);
637 }
638
init_events(struct intel_gvt_irq * irq)639 static void init_events(
640 struct intel_gvt_irq *irq)
641 {
642 int i;
643
644 for (i = 0; i < INTEL_GVT_EVENT_MAX; i++) {
645 irq->events[i].info = NULL;
646 irq->events[i].v_handler = handle_default_event_virt;
647 }
648 }
649
vblank_timer_fn(struct hrtimer * data)650 static enum hrtimer_restart vblank_timer_fn(struct hrtimer *data)
651 {
652 struct intel_gvt_vblank_timer *vblank_timer;
653 struct intel_gvt_irq *irq;
654 struct intel_gvt *gvt;
655
656 vblank_timer = container_of(data, struct intel_gvt_vblank_timer, timer);
657 irq = container_of(vblank_timer, struct intel_gvt_irq, vblank_timer);
658 gvt = container_of(irq, struct intel_gvt, irq);
659
660 intel_gvt_request_service(gvt, INTEL_GVT_REQUEST_EMULATE_VBLANK);
661 hrtimer_add_expires_ns(&vblank_timer->timer, vblank_timer->period);
662 return HRTIMER_RESTART;
663 }
664
665 /**
666 * intel_gvt_clean_irq - clean up GVT-g IRQ emulation subsystem
667 * @gvt: a GVT device
668 *
669 * This function is called at driver unloading stage, to clean up GVT-g IRQ
670 * emulation subsystem.
671 *
672 */
intel_gvt_clean_irq(struct intel_gvt * gvt)673 void intel_gvt_clean_irq(struct intel_gvt *gvt)
674 {
675 struct intel_gvt_irq *irq = &gvt->irq;
676
677 hrtimer_cancel(&irq->vblank_timer.timer);
678 }
679
680 #define VBLANK_TIMER_PERIOD 16000000
681
682 /**
683 * intel_gvt_init_irq - initialize GVT-g IRQ emulation subsystem
684 * @gvt: a GVT device
685 *
686 * This function is called at driver loading stage, to initialize the GVT-g IRQ
687 * emulation subsystem.
688 *
689 * Returns:
690 * Zero on success, negative error code if failed.
691 */
intel_gvt_init_irq(struct intel_gvt * gvt)692 int intel_gvt_init_irq(struct intel_gvt *gvt)
693 {
694 struct intel_gvt_irq *irq = &gvt->irq;
695 struct intel_gvt_vblank_timer *vblank_timer = &irq->vblank_timer;
696
697 gvt_dbg_core("init irq framework\n");
698
699 irq->ops = &gen8_irq_ops;
700 irq->irq_map = gen8_irq_map;
701
702 /* common event initialization */
703 init_events(irq);
704
705 /* gen specific initialization */
706 irq->ops->init_irq(irq);
707
708 init_irq_map(irq);
709
710 hrtimer_init(&vblank_timer->timer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
711 vblank_timer->timer.function = vblank_timer_fn;
712 vblank_timer->period = VBLANK_TIMER_PERIOD;
713
714 return 0;
715 }
716