1 /*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
27 */
28
29 #include <linux/i2c.h>
30 #include <linux/slab.h>
31 #include <linux/delay.h>
32 #include <linux/hdmi.h>
33 #include <asm/io.h>
34 #include <drm/drmP.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_edid.h>
37 #include "intel_drv.h"
38 #include <drm/i915_drm.h>
39 #include "i915_drv.h"
40
intel_hdmi_to_dev(struct intel_hdmi * intel_hdmi)41 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
42 {
43 return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
44 }
45
46 static void
assert_hdmi_port_disabled(struct intel_hdmi * intel_hdmi)47 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
48 {
49 struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
50 struct drm_i915_private *dev_priv = dev->dev_private;
51 uint32_t enabled_bits;
52
53 enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
54
55 WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
56 "HDMI port enabled, expecting disabled\n");
57 }
58
enc_to_intel_hdmi(struct drm_encoder * encoder)59 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
60 {
61 struct intel_digital_port *intel_dig_port =
62 container_of(encoder, struct intel_digital_port, base.base);
63 return &intel_dig_port->hdmi;
64 }
65
intel_attached_hdmi(struct drm_connector * connector)66 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
67 {
68 return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
69 }
70
g4x_infoframe_index(enum hdmi_infoframe_type type)71 static u32 g4x_infoframe_index(enum hdmi_infoframe_type type)
72 {
73 switch (type) {
74 case HDMI_INFOFRAME_TYPE_AVI:
75 return VIDEO_DIP_SELECT_AVI;
76 case HDMI_INFOFRAME_TYPE_SPD:
77 return VIDEO_DIP_SELECT_SPD;
78 case HDMI_INFOFRAME_TYPE_VENDOR:
79 return VIDEO_DIP_SELECT_VENDOR;
80 default:
81 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
82 return 0;
83 }
84 }
85
g4x_infoframe_enable(enum hdmi_infoframe_type type)86 static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type)
87 {
88 switch (type) {
89 case HDMI_INFOFRAME_TYPE_AVI:
90 return VIDEO_DIP_ENABLE_AVI;
91 case HDMI_INFOFRAME_TYPE_SPD:
92 return VIDEO_DIP_ENABLE_SPD;
93 case HDMI_INFOFRAME_TYPE_VENDOR:
94 return VIDEO_DIP_ENABLE_VENDOR;
95 default:
96 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
97 return 0;
98 }
99 }
100
hsw_infoframe_enable(enum hdmi_infoframe_type type)101 static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)
102 {
103 switch (type) {
104 case HDMI_INFOFRAME_TYPE_AVI:
105 return VIDEO_DIP_ENABLE_AVI_HSW;
106 case HDMI_INFOFRAME_TYPE_SPD:
107 return VIDEO_DIP_ENABLE_SPD_HSW;
108 case HDMI_INFOFRAME_TYPE_VENDOR:
109 return VIDEO_DIP_ENABLE_VS_HSW;
110 default:
111 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
112 return 0;
113 }
114 }
115
hsw_infoframe_data_reg(enum hdmi_infoframe_type type,enum transcoder cpu_transcoder,struct drm_i915_private * dev_priv)116 static u32 hsw_infoframe_data_reg(enum hdmi_infoframe_type type,
117 enum transcoder cpu_transcoder,
118 struct drm_i915_private *dev_priv)
119 {
120 switch (type) {
121 case HDMI_INFOFRAME_TYPE_AVI:
122 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder);
123 case HDMI_INFOFRAME_TYPE_SPD:
124 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder);
125 case HDMI_INFOFRAME_TYPE_VENDOR:
126 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder);
127 default:
128 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
129 return 0;
130 }
131 }
132
g4x_write_infoframe(struct drm_encoder * encoder,enum hdmi_infoframe_type type,const void * frame,ssize_t len)133 static void g4x_write_infoframe(struct drm_encoder *encoder,
134 enum hdmi_infoframe_type type,
135 const void *frame, ssize_t len)
136 {
137 const uint32_t *data = frame;
138 struct drm_device *dev = encoder->dev;
139 struct drm_i915_private *dev_priv = dev->dev_private;
140 u32 val = I915_READ(VIDEO_DIP_CTL);
141 int i;
142
143 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
144
145 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
146 val |= g4x_infoframe_index(type);
147
148 val &= ~g4x_infoframe_enable(type);
149
150 I915_WRITE(VIDEO_DIP_CTL, val);
151
152 mmiowb();
153 for (i = 0; i < len; i += 4) {
154 I915_WRITE(VIDEO_DIP_DATA, *data);
155 data++;
156 }
157 /* Write every possible data byte to force correct ECC calculation. */
158 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
159 I915_WRITE(VIDEO_DIP_DATA, 0);
160 mmiowb();
161
162 val |= g4x_infoframe_enable(type);
163 val &= ~VIDEO_DIP_FREQ_MASK;
164 val |= VIDEO_DIP_FREQ_VSYNC;
165
166 I915_WRITE(VIDEO_DIP_CTL, val);
167 POSTING_READ(VIDEO_DIP_CTL);
168 }
169
ibx_write_infoframe(struct drm_encoder * encoder,enum hdmi_infoframe_type type,const void * frame,ssize_t len)170 static void ibx_write_infoframe(struct drm_encoder *encoder,
171 enum hdmi_infoframe_type type,
172 const void *frame, ssize_t len)
173 {
174 const uint32_t *data = frame;
175 struct drm_device *dev = encoder->dev;
176 struct drm_i915_private *dev_priv = dev->dev_private;
177 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
178 int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
179 u32 val = I915_READ(reg);
180
181 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
182
183 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
184 val |= g4x_infoframe_index(type);
185
186 val &= ~g4x_infoframe_enable(type);
187
188 I915_WRITE(reg, val);
189
190 mmiowb();
191 for (i = 0; i < len; i += 4) {
192 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
193 data++;
194 }
195 /* Write every possible data byte to force correct ECC calculation. */
196 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
197 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
198 mmiowb();
199
200 val |= g4x_infoframe_enable(type);
201 val &= ~VIDEO_DIP_FREQ_MASK;
202 val |= VIDEO_DIP_FREQ_VSYNC;
203
204 I915_WRITE(reg, val);
205 POSTING_READ(reg);
206 }
207
cpt_write_infoframe(struct drm_encoder * encoder,enum hdmi_infoframe_type type,const void * frame,ssize_t len)208 static void cpt_write_infoframe(struct drm_encoder *encoder,
209 enum hdmi_infoframe_type type,
210 const void *frame, ssize_t len)
211 {
212 const uint32_t *data = frame;
213 struct drm_device *dev = encoder->dev;
214 struct drm_i915_private *dev_priv = dev->dev_private;
215 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
216 int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
217 u32 val = I915_READ(reg);
218
219 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
220
221 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
222 val |= g4x_infoframe_index(type);
223
224 /* The DIP control register spec says that we need to update the AVI
225 * infoframe without clearing its enable bit */
226 if (type != HDMI_INFOFRAME_TYPE_AVI)
227 val &= ~g4x_infoframe_enable(type);
228
229 I915_WRITE(reg, val);
230
231 mmiowb();
232 for (i = 0; i < len; i += 4) {
233 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
234 data++;
235 }
236 /* Write every possible data byte to force correct ECC calculation. */
237 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
238 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
239 mmiowb();
240
241 val |= g4x_infoframe_enable(type);
242 val &= ~VIDEO_DIP_FREQ_MASK;
243 val |= VIDEO_DIP_FREQ_VSYNC;
244
245 I915_WRITE(reg, val);
246 POSTING_READ(reg);
247 }
248
vlv_write_infoframe(struct drm_encoder * encoder,enum hdmi_infoframe_type type,const void * frame,ssize_t len)249 static void vlv_write_infoframe(struct drm_encoder *encoder,
250 enum hdmi_infoframe_type type,
251 const void *frame, ssize_t len)
252 {
253 const uint32_t *data = frame;
254 struct drm_device *dev = encoder->dev;
255 struct drm_i915_private *dev_priv = dev->dev_private;
256 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
257 int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
258 u32 val = I915_READ(reg);
259
260 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
261
262 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
263 val |= g4x_infoframe_index(type);
264
265 val &= ~g4x_infoframe_enable(type);
266
267 I915_WRITE(reg, val);
268
269 mmiowb();
270 for (i = 0; i < len; i += 4) {
271 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
272 data++;
273 }
274 /* Write every possible data byte to force correct ECC calculation. */
275 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
276 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
277 mmiowb();
278
279 val |= g4x_infoframe_enable(type);
280 val &= ~VIDEO_DIP_FREQ_MASK;
281 val |= VIDEO_DIP_FREQ_VSYNC;
282
283 I915_WRITE(reg, val);
284 POSTING_READ(reg);
285 }
286
hsw_write_infoframe(struct drm_encoder * encoder,enum hdmi_infoframe_type type,const void * frame,ssize_t len)287 static void hsw_write_infoframe(struct drm_encoder *encoder,
288 enum hdmi_infoframe_type type,
289 const void *frame, ssize_t len)
290 {
291 const uint32_t *data = frame;
292 struct drm_device *dev = encoder->dev;
293 struct drm_i915_private *dev_priv = dev->dev_private;
294 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
295 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder);
296 u32 data_reg;
297 int i;
298 u32 val = I915_READ(ctl_reg);
299
300 data_reg = hsw_infoframe_data_reg(type,
301 intel_crtc->config.cpu_transcoder,
302 dev_priv);
303 if (data_reg == 0)
304 return;
305
306 val &= ~hsw_infoframe_enable(type);
307 I915_WRITE(ctl_reg, val);
308
309 mmiowb();
310 for (i = 0; i < len; i += 4) {
311 I915_WRITE(data_reg + i, *data);
312 data++;
313 }
314 /* Write every possible data byte to force correct ECC calculation. */
315 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
316 I915_WRITE(data_reg + i, 0);
317 mmiowb();
318
319 val |= hsw_infoframe_enable(type);
320 I915_WRITE(ctl_reg, val);
321 POSTING_READ(ctl_reg);
322 }
323
324 /*
325 * The data we write to the DIP data buffer registers is 1 byte bigger than the
326 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
327 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
328 * used for both technologies.
329 *
330 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
331 * DW1: DB3 | DB2 | DB1 | DB0
332 * DW2: DB7 | DB6 | DB5 | DB4
333 * DW3: ...
334 *
335 * (HB is Header Byte, DB is Data Byte)
336 *
337 * The hdmi pack() functions don't know about that hardware specific hole so we
338 * trick them by giving an offset into the buffer and moving back the header
339 * bytes by one.
340 */
intel_write_infoframe(struct drm_encoder * encoder,union hdmi_infoframe * frame)341 static void intel_write_infoframe(struct drm_encoder *encoder,
342 union hdmi_infoframe *frame)
343 {
344 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
345 uint8_t buffer[VIDEO_DIP_DATA_SIZE];
346 ssize_t len;
347
348 /* see comment above for the reason for this offset */
349 len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
350 if (len < 0)
351 return;
352
353 /* Insert the 'hole' (see big comment above) at position 3 */
354 buffer[0] = buffer[1];
355 buffer[1] = buffer[2];
356 buffer[2] = buffer[3];
357 buffer[3] = 0;
358 len++;
359
360 intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len);
361 }
362
intel_hdmi_set_avi_infoframe(struct drm_encoder * encoder,struct drm_display_mode * adjusted_mode)363 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
364 struct drm_display_mode *adjusted_mode)
365 {
366 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
367 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
368 union hdmi_infoframe frame;
369 int ret;
370
371 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
372 adjusted_mode);
373 if (ret < 0) {
374 DRM_ERROR("couldn't fill AVI infoframe\n");
375 return;
376 }
377
378 if (intel_hdmi->rgb_quant_range_selectable) {
379 if (intel_crtc->config.limited_color_range)
380 frame.avi.quantization_range =
381 HDMI_QUANTIZATION_RANGE_LIMITED;
382 else
383 frame.avi.quantization_range =
384 HDMI_QUANTIZATION_RANGE_FULL;
385 }
386
387 intel_write_infoframe(encoder, &frame);
388 }
389
intel_hdmi_set_spd_infoframe(struct drm_encoder * encoder)390 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
391 {
392 union hdmi_infoframe frame;
393 int ret;
394
395 ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
396 if (ret < 0) {
397 DRM_ERROR("couldn't fill SPD infoframe\n");
398 return;
399 }
400
401 frame.spd.sdi = HDMI_SPD_SDI_PC;
402
403 intel_write_infoframe(encoder, &frame);
404 }
405
406 static void
intel_hdmi_set_hdmi_infoframe(struct drm_encoder * encoder,struct drm_display_mode * adjusted_mode)407 intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder,
408 struct drm_display_mode *adjusted_mode)
409 {
410 union hdmi_infoframe frame;
411 int ret;
412
413 ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
414 adjusted_mode);
415 if (ret < 0)
416 return;
417
418 intel_write_infoframe(encoder, &frame);
419 }
420
g4x_set_infoframes(struct drm_encoder * encoder,struct drm_display_mode * adjusted_mode)421 static void g4x_set_infoframes(struct drm_encoder *encoder,
422 struct drm_display_mode *adjusted_mode)
423 {
424 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
425 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
426 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
427 u32 reg = VIDEO_DIP_CTL;
428 u32 val = I915_READ(reg);
429 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
430
431 assert_hdmi_port_disabled(intel_hdmi);
432
433 /* If the registers were not initialized yet, they might be zeroes,
434 * which means we're selecting the AVI DIP and we're setting its
435 * frequency to once. This seems to really confuse the HW and make
436 * things stop working (the register spec says the AVI always needs to
437 * be sent every VSync). So here we avoid writing to the register more
438 * than we need and also explicitly select the AVI DIP and explicitly
439 * set its frequency to every VSync. Avoiding to write it twice seems to
440 * be enough to solve the problem, but being defensive shouldn't hurt us
441 * either. */
442 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
443
444 if (!intel_hdmi->has_hdmi_sink) {
445 if (!(val & VIDEO_DIP_ENABLE))
446 return;
447 val &= ~VIDEO_DIP_ENABLE;
448 I915_WRITE(reg, val);
449 POSTING_READ(reg);
450 return;
451 }
452
453 if (port != (val & VIDEO_DIP_PORT_MASK)) {
454 if (val & VIDEO_DIP_ENABLE) {
455 val &= ~VIDEO_DIP_ENABLE;
456 I915_WRITE(reg, val);
457 POSTING_READ(reg);
458 }
459 val &= ~VIDEO_DIP_PORT_MASK;
460 val |= port;
461 }
462
463 val |= VIDEO_DIP_ENABLE;
464 val &= ~VIDEO_DIP_ENABLE_VENDOR;
465
466 I915_WRITE(reg, val);
467 POSTING_READ(reg);
468
469 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
470 intel_hdmi_set_spd_infoframe(encoder);
471 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
472 }
473
ibx_set_infoframes(struct drm_encoder * encoder,struct drm_display_mode * adjusted_mode)474 static void ibx_set_infoframes(struct drm_encoder *encoder,
475 struct drm_display_mode *adjusted_mode)
476 {
477 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
478 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
479 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
480 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
481 u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
482 u32 val = I915_READ(reg);
483 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
484
485 assert_hdmi_port_disabled(intel_hdmi);
486
487 /* See the big comment in g4x_set_infoframes() */
488 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
489
490 if (!intel_hdmi->has_hdmi_sink) {
491 if (!(val & VIDEO_DIP_ENABLE))
492 return;
493 val &= ~VIDEO_DIP_ENABLE;
494 I915_WRITE(reg, val);
495 POSTING_READ(reg);
496 return;
497 }
498
499 if (port != (val & VIDEO_DIP_PORT_MASK)) {
500 if (val & VIDEO_DIP_ENABLE) {
501 val &= ~VIDEO_DIP_ENABLE;
502 I915_WRITE(reg, val);
503 POSTING_READ(reg);
504 }
505 val &= ~VIDEO_DIP_PORT_MASK;
506 val |= port;
507 }
508
509 val |= VIDEO_DIP_ENABLE;
510 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
511 VIDEO_DIP_ENABLE_GCP);
512
513 I915_WRITE(reg, val);
514 POSTING_READ(reg);
515
516 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
517 intel_hdmi_set_spd_infoframe(encoder);
518 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
519 }
520
cpt_set_infoframes(struct drm_encoder * encoder,struct drm_display_mode * adjusted_mode)521 static void cpt_set_infoframes(struct drm_encoder *encoder,
522 struct drm_display_mode *adjusted_mode)
523 {
524 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
525 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
526 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
527 u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
528 u32 val = I915_READ(reg);
529
530 assert_hdmi_port_disabled(intel_hdmi);
531
532 /* See the big comment in g4x_set_infoframes() */
533 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
534
535 if (!intel_hdmi->has_hdmi_sink) {
536 if (!(val & VIDEO_DIP_ENABLE))
537 return;
538 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI);
539 I915_WRITE(reg, val);
540 POSTING_READ(reg);
541 return;
542 }
543
544 /* Set both together, unset both together: see the spec. */
545 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
546 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
547 VIDEO_DIP_ENABLE_GCP);
548
549 I915_WRITE(reg, val);
550 POSTING_READ(reg);
551
552 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
553 intel_hdmi_set_spd_infoframe(encoder);
554 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
555 }
556
vlv_set_infoframes(struct drm_encoder * encoder,struct drm_display_mode * adjusted_mode)557 static void vlv_set_infoframes(struct drm_encoder *encoder,
558 struct drm_display_mode *adjusted_mode)
559 {
560 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
561 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
562 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
563 u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
564 u32 val = I915_READ(reg);
565
566 assert_hdmi_port_disabled(intel_hdmi);
567
568 /* See the big comment in g4x_set_infoframes() */
569 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
570
571 if (!intel_hdmi->has_hdmi_sink) {
572 if (!(val & VIDEO_DIP_ENABLE))
573 return;
574 val &= ~VIDEO_DIP_ENABLE;
575 I915_WRITE(reg, val);
576 POSTING_READ(reg);
577 return;
578 }
579
580 val |= VIDEO_DIP_ENABLE;
581 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
582 VIDEO_DIP_ENABLE_GCP);
583
584 I915_WRITE(reg, val);
585 POSTING_READ(reg);
586
587 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
588 intel_hdmi_set_spd_infoframe(encoder);
589 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
590 }
591
hsw_set_infoframes(struct drm_encoder * encoder,struct drm_display_mode * adjusted_mode)592 static void hsw_set_infoframes(struct drm_encoder *encoder,
593 struct drm_display_mode *adjusted_mode)
594 {
595 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
596 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
597 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
598 u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder);
599 u32 val = I915_READ(reg);
600
601 assert_hdmi_port_disabled(intel_hdmi);
602
603 if (!intel_hdmi->has_hdmi_sink) {
604 I915_WRITE(reg, 0);
605 POSTING_READ(reg);
606 return;
607 }
608
609 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
610 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW);
611
612 I915_WRITE(reg, val);
613 POSTING_READ(reg);
614
615 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
616 intel_hdmi_set_spd_infoframe(encoder);
617 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
618 }
619
intel_hdmi_mode_set(struct intel_encoder * encoder)620 static void intel_hdmi_mode_set(struct intel_encoder *encoder)
621 {
622 struct drm_device *dev = encoder->base.dev;
623 struct drm_i915_private *dev_priv = dev->dev_private;
624 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
625 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
626 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
627 u32 hdmi_val;
628
629 hdmi_val = SDVO_ENCODING_HDMI;
630 if (!HAS_PCH_SPLIT(dev))
631 hdmi_val |= intel_hdmi->color_range;
632 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
633 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
634 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
635 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
636
637 if (crtc->config.pipe_bpp > 24)
638 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
639 else
640 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
641
642 /* Required on CPT */
643 if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev))
644 hdmi_val |= HDMI_MODE_SELECT_HDMI;
645
646 if (intel_hdmi->has_audio) {
647 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
648 pipe_name(crtc->pipe));
649 hdmi_val |= SDVO_AUDIO_ENABLE;
650 hdmi_val |= HDMI_MODE_SELECT_HDMI;
651 intel_write_eld(&encoder->base, adjusted_mode);
652 }
653
654 if (HAS_PCH_CPT(dev))
655 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
656 else
657 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
658
659 I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
660 POSTING_READ(intel_hdmi->hdmi_reg);
661
662 intel_hdmi->set_infoframes(&encoder->base, adjusted_mode);
663 }
664
intel_hdmi_get_hw_state(struct intel_encoder * encoder,enum i915_pipe * pipe)665 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
666 enum i915_pipe *pipe)
667 {
668 struct drm_device *dev = encoder->base.dev;
669 struct drm_i915_private *dev_priv = dev->dev_private;
670 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
671 enum intel_display_power_domain power_domain;
672 u32 tmp;
673
674 power_domain = intel_display_port_power_domain(encoder);
675 if (!intel_display_power_enabled(dev_priv, power_domain))
676 return false;
677
678 tmp = I915_READ(intel_hdmi->hdmi_reg);
679
680 if (!(tmp & SDVO_ENABLE))
681 return false;
682
683 if (HAS_PCH_CPT(dev))
684 *pipe = PORT_TO_PIPE_CPT(tmp);
685 else
686 *pipe = PORT_TO_PIPE(tmp);
687
688 return true;
689 }
690
intel_hdmi_get_config(struct intel_encoder * encoder,struct intel_crtc_config * pipe_config)691 static void intel_hdmi_get_config(struct intel_encoder *encoder,
692 struct intel_crtc_config *pipe_config)
693 {
694 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
695 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
696 u32 tmp, flags = 0;
697 int dotclock;
698
699 tmp = I915_READ(intel_hdmi->hdmi_reg);
700
701 if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
702 flags |= DRM_MODE_FLAG_PHSYNC;
703 else
704 flags |= DRM_MODE_FLAG_NHSYNC;
705
706 if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
707 flags |= DRM_MODE_FLAG_PVSYNC;
708 else
709 flags |= DRM_MODE_FLAG_NVSYNC;
710
711 pipe_config->adjusted_mode.flags |= flags;
712
713 if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
714 dotclock = pipe_config->port_clock * 2 / 3;
715 else
716 dotclock = pipe_config->port_clock;
717
718 if (HAS_PCH_SPLIT(dev_priv->dev))
719 ironlake_check_encoder_dotclock(pipe_config, dotclock);
720
721 pipe_config->adjusted_mode.crtc_clock = dotclock;
722 }
723
intel_enable_hdmi(struct intel_encoder * encoder)724 static void intel_enable_hdmi(struct intel_encoder *encoder)
725 {
726 struct drm_device *dev = encoder->base.dev;
727 struct drm_i915_private *dev_priv = dev->dev_private;
728 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
729 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
730 u32 temp;
731 u32 enable_bits = SDVO_ENABLE;
732
733 if (intel_hdmi->has_audio)
734 enable_bits |= SDVO_AUDIO_ENABLE;
735
736 temp = I915_READ(intel_hdmi->hdmi_reg);
737
738 /* HW workaround for IBX, we need to move the port to transcoder A
739 * before disabling it, so restore the transcoder select bit here. */
740 if (HAS_PCH_IBX(dev))
741 enable_bits |= SDVO_PIPE_SEL(intel_crtc->pipe);
742
743 /* HW workaround, need to toggle enable bit off and on for 12bpc, but
744 * we do this anyway which shows more stable in testing.
745 */
746 if (HAS_PCH_SPLIT(dev)) {
747 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
748 POSTING_READ(intel_hdmi->hdmi_reg);
749 }
750
751 temp |= enable_bits;
752
753 I915_WRITE(intel_hdmi->hdmi_reg, temp);
754 POSTING_READ(intel_hdmi->hdmi_reg);
755
756 /* HW workaround, need to write this twice for issue that may result
757 * in first write getting masked.
758 */
759 if (HAS_PCH_SPLIT(dev)) {
760 I915_WRITE(intel_hdmi->hdmi_reg, temp);
761 POSTING_READ(intel_hdmi->hdmi_reg);
762 }
763 }
764
vlv_enable_hdmi(struct intel_encoder * encoder)765 static void vlv_enable_hdmi(struct intel_encoder *encoder)
766 {
767 }
768
intel_disable_hdmi(struct intel_encoder * encoder)769 static void intel_disable_hdmi(struct intel_encoder *encoder)
770 {
771 struct drm_device *dev = encoder->base.dev;
772 struct drm_i915_private *dev_priv = dev->dev_private;
773 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
774 u32 temp;
775 u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE;
776
777 temp = I915_READ(intel_hdmi->hdmi_reg);
778
779 /* HW workaround for IBX, we need to move the port to transcoder A
780 * before disabling it. */
781 if (HAS_PCH_IBX(dev)) {
782 struct drm_crtc *crtc = encoder->base.crtc;
783 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
784
785 if (temp & SDVO_PIPE_B_SELECT) {
786 temp &= ~SDVO_PIPE_B_SELECT;
787 I915_WRITE(intel_hdmi->hdmi_reg, temp);
788 POSTING_READ(intel_hdmi->hdmi_reg);
789
790 /* Again we need to write this twice. */
791 I915_WRITE(intel_hdmi->hdmi_reg, temp);
792 POSTING_READ(intel_hdmi->hdmi_reg);
793
794 /* Transcoder selection bits only update
795 * effectively on vblank. */
796 if (crtc)
797 intel_wait_for_vblank(dev, pipe);
798 else
799 msleep(50);
800 }
801 }
802
803 /* HW workaround, need to toggle enable bit off and on for 12bpc, but
804 * we do this anyway which shows more stable in testing.
805 */
806 if (HAS_PCH_SPLIT(dev)) {
807 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
808 POSTING_READ(intel_hdmi->hdmi_reg);
809 }
810
811 temp &= ~enable_bits;
812
813 I915_WRITE(intel_hdmi->hdmi_reg, temp);
814 POSTING_READ(intel_hdmi->hdmi_reg);
815
816 /* HW workaround, need to write this twice for issue that may result
817 * in first write getting masked.
818 */
819 if (HAS_PCH_SPLIT(dev)) {
820 I915_WRITE(intel_hdmi->hdmi_reg, temp);
821 POSTING_READ(intel_hdmi->hdmi_reg);
822 }
823 }
824
hdmi_portclock_limit(struct intel_hdmi * hdmi,bool respect_dvi_limit)825 static int hdmi_portclock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit)
826 {
827 struct drm_device *dev = intel_hdmi_to_dev(hdmi);
828
829 if ((respect_dvi_limit && !hdmi->has_hdmi_sink) || IS_G4X(dev))
830 return 165000;
831 else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8)
832 return 300000;
833 else
834 return 225000;
835 }
836
837 static enum drm_mode_status
intel_hdmi_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)838 intel_hdmi_mode_valid(struct drm_connector *connector,
839 struct drm_display_mode *mode)
840 {
841 if (mode->clock > hdmi_portclock_limit(intel_attached_hdmi(connector),
842 true))
843 return MODE_CLOCK_HIGH;
844 if (mode->clock < 20000)
845 return MODE_CLOCK_LOW;
846
847 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
848 return MODE_NO_DBLESCAN;
849
850 return MODE_OK;
851 }
852
hdmi_12bpc_possible(struct intel_crtc * crtc)853 static bool hdmi_12bpc_possible(struct intel_crtc *crtc)
854 {
855 struct drm_device *dev = crtc->base.dev;
856 struct intel_encoder *encoder;
857 int count = 0, count_hdmi = 0;
858
859 if (!HAS_PCH_SPLIT(dev))
860 return false;
861
862 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
863 if (encoder->new_crtc != crtc)
864 continue;
865
866 count_hdmi += encoder->type == INTEL_OUTPUT_HDMI;
867 count++;
868 }
869
870 /*
871 * HDMI 12bpc affects the clocks, so it's only possible
872 * when not cloning with other encoder types.
873 */
874 return count_hdmi > 0 && count_hdmi == count;
875 }
876
intel_hdmi_compute_config(struct intel_encoder * encoder,struct intel_crtc_config * pipe_config)877 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
878 struct intel_crtc_config *pipe_config)
879 {
880 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
881 struct drm_device *dev = encoder->base.dev;
882 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
883 int clock_12bpc = pipe_config->adjusted_mode.crtc_clock * 3 / 2;
884 int portclock_limit = hdmi_portclock_limit(intel_hdmi, false);
885 int desired_bpp;
886
887 if (intel_hdmi->color_range_auto) {
888 /* See CEA-861-E - 5.1 Default Encoding Parameters */
889 if (intel_hdmi->has_hdmi_sink &&
890 drm_match_cea_mode(adjusted_mode) > 1)
891 intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
892 else
893 intel_hdmi->color_range = 0;
894 }
895
896 if (intel_hdmi->color_range)
897 pipe_config->limited_color_range = true;
898
899 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev))
900 pipe_config->has_pch_encoder = true;
901
902 /*
903 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
904 * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
905 * outputs. We also need to check that the higher clock still fits
906 * within limits.
907 */
908 if (pipe_config->pipe_bpp > 8*3 && intel_hdmi->has_hdmi_sink &&
909 clock_12bpc <= portclock_limit &&
910 hdmi_12bpc_possible(encoder->new_crtc)) {
911 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
912 desired_bpp = 12*3;
913
914 /* Need to adjust the port link by 1.5x for 12bpc. */
915 pipe_config->port_clock = clock_12bpc;
916 } else {
917 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
918 desired_bpp = 8*3;
919 }
920
921 if (!pipe_config->bw_constrained) {
922 DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp);
923 pipe_config->pipe_bpp = desired_bpp;
924 }
925
926 if (adjusted_mode->crtc_clock > portclock_limit) {
927 DRM_DEBUG_KMS("too high HDMI clock, rejecting mode\n");
928 return false;
929 }
930
931 return true;
932 }
933
934 static enum drm_connector_status
intel_hdmi_detect(struct drm_connector * connector,bool force)935 intel_hdmi_detect(struct drm_connector *connector, bool force)
936 {
937 struct drm_device *dev = connector->dev;
938 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
939 struct intel_digital_port *intel_dig_port =
940 hdmi_to_dig_port(intel_hdmi);
941 struct intel_encoder *intel_encoder = &intel_dig_port->base;
942 struct drm_i915_private *dev_priv = dev->dev_private;
943 struct edid *edid;
944 enum intel_display_power_domain power_domain;
945 enum drm_connector_status status = connector_status_disconnected;
946
947 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
948 connector->base.id, drm_get_connector_name(connector));
949
950 power_domain = intel_display_port_power_domain(intel_encoder);
951 intel_display_power_get(dev_priv, power_domain);
952
953 intel_hdmi->has_hdmi_sink = false;
954 intel_hdmi->has_audio = false;
955 intel_hdmi->rgb_quant_range_selectable = false;
956 edid = drm_get_edid(connector,
957 intel_gmbus_get_adapter(dev_priv,
958 intel_hdmi->ddc_bus));
959
960 if (edid) {
961 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
962 status = connector_status_connected;
963 if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
964 intel_hdmi->has_hdmi_sink =
965 drm_detect_hdmi_monitor(edid);
966 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
967 intel_hdmi->rgb_quant_range_selectable =
968 drm_rgb_quant_range_selectable(edid);
969 }
970 kfree(edid);
971 }
972
973 if (status == connector_status_connected) {
974 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
975 intel_hdmi->has_audio =
976 (intel_hdmi->force_audio == HDMI_AUDIO_ON);
977 intel_encoder->type = INTEL_OUTPUT_HDMI;
978 }
979
980 intel_display_power_put(dev_priv, power_domain);
981
982 return status;
983 }
984
intel_hdmi_get_modes(struct drm_connector * connector)985 static int intel_hdmi_get_modes(struct drm_connector *connector)
986 {
987 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
988 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
989 struct drm_i915_private *dev_priv = connector->dev->dev_private;
990 enum intel_display_power_domain power_domain;
991 int ret;
992
993 /* We should parse the EDID data and find out if it's an HDMI sink so
994 * we can send audio to it.
995 */
996
997 power_domain = intel_display_port_power_domain(intel_encoder);
998 intel_display_power_get(dev_priv, power_domain);
999
1000 ret = intel_ddc_get_modes(connector,
1001 intel_gmbus_get_adapter(dev_priv,
1002 intel_hdmi->ddc_bus));
1003
1004 intel_display_power_put(dev_priv, power_domain);
1005
1006 return ret;
1007 }
1008
1009 static bool
intel_hdmi_detect_audio(struct drm_connector * connector)1010 intel_hdmi_detect_audio(struct drm_connector *connector)
1011 {
1012 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
1013 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
1014 struct drm_i915_private *dev_priv = connector->dev->dev_private;
1015 enum intel_display_power_domain power_domain;
1016 struct edid *edid;
1017 bool has_audio = false;
1018
1019 power_domain = intel_display_port_power_domain(intel_encoder);
1020 intel_display_power_get(dev_priv, power_domain);
1021
1022 edid = drm_get_edid(connector,
1023 intel_gmbus_get_adapter(dev_priv,
1024 intel_hdmi->ddc_bus));
1025 if (edid) {
1026 if (edid->input & DRM_EDID_INPUT_DIGITAL)
1027 has_audio = drm_detect_monitor_audio(edid);
1028 kfree(edid);
1029 }
1030
1031 intel_display_power_put(dev_priv, power_domain);
1032
1033 return has_audio;
1034 }
1035
1036 static int
intel_hdmi_set_property(struct drm_connector * connector,struct drm_property * property,uint64_t val)1037 intel_hdmi_set_property(struct drm_connector *connector,
1038 struct drm_property *property,
1039 uint64_t val)
1040 {
1041 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1042 struct intel_digital_port *intel_dig_port =
1043 hdmi_to_dig_port(intel_hdmi);
1044 struct drm_i915_private *dev_priv = connector->dev->dev_private;
1045 int ret;
1046
1047 ret = drm_object_property_set_value(&connector->base, property, val);
1048 if (ret)
1049 return ret;
1050
1051 if (property == dev_priv->force_audio_property) {
1052 enum hdmi_force_audio i = val;
1053 bool has_audio;
1054
1055 if (i == intel_hdmi->force_audio)
1056 return 0;
1057
1058 intel_hdmi->force_audio = i;
1059
1060 if (i == HDMI_AUDIO_AUTO)
1061 has_audio = intel_hdmi_detect_audio(connector);
1062 else
1063 has_audio = (i == HDMI_AUDIO_ON);
1064
1065 if (i == HDMI_AUDIO_OFF_DVI)
1066 intel_hdmi->has_hdmi_sink = 0;
1067
1068 intel_hdmi->has_audio = has_audio;
1069 goto done;
1070 }
1071
1072 if (property == dev_priv->broadcast_rgb_property) {
1073 bool old_auto = intel_hdmi->color_range_auto;
1074 uint32_t old_range = intel_hdmi->color_range;
1075
1076 switch (val) {
1077 case INTEL_BROADCAST_RGB_AUTO:
1078 intel_hdmi->color_range_auto = true;
1079 break;
1080 case INTEL_BROADCAST_RGB_FULL:
1081 intel_hdmi->color_range_auto = false;
1082 intel_hdmi->color_range = 0;
1083 break;
1084 case INTEL_BROADCAST_RGB_LIMITED:
1085 intel_hdmi->color_range_auto = false;
1086 intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
1087 break;
1088 default:
1089 return -EINVAL;
1090 }
1091
1092 if (old_auto == intel_hdmi->color_range_auto &&
1093 old_range == intel_hdmi->color_range)
1094 return 0;
1095
1096 goto done;
1097 }
1098
1099 return -EINVAL;
1100
1101 done:
1102 if (intel_dig_port->base.base.crtc)
1103 intel_crtc_restore_mode(intel_dig_port->base.base.crtc);
1104
1105 return 0;
1106 }
1107
vlv_hdmi_pre_enable(struct intel_encoder * encoder)1108 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
1109 {
1110 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1111 struct drm_device *dev = encoder->base.dev;
1112 struct drm_i915_private *dev_priv = dev->dev_private;
1113 struct intel_crtc *intel_crtc =
1114 to_intel_crtc(encoder->base.crtc);
1115 enum dpio_channel port = vlv_dport_to_channel(dport);
1116 int pipe = intel_crtc->pipe;
1117 u32 val;
1118
1119 if (!IS_VALLEYVIEW(dev))
1120 return;
1121
1122 /* Enable clock channels for this port */
1123 mutex_lock(&dev_priv->dpio_lock);
1124 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
1125 val = 0;
1126 if (pipe)
1127 val |= (1<<21);
1128 else
1129 val &= ~(1<<21);
1130 val |= 0x001000c4;
1131 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1132
1133 /* HDMI 1.0V-2dB */
1134 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0);
1135 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f);
1136 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a);
1137 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040);
1138 vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878);
1139 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
1140 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1141 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1142
1143 /* Program lane clock */
1144 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1145 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
1146 mutex_unlock(&dev_priv->dpio_lock);
1147
1148 intel_enable_hdmi(encoder);
1149
1150 vlv_wait_port_ready(dev_priv, dport);
1151 }
1152
vlv_hdmi_pre_pll_enable(struct intel_encoder * encoder)1153 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
1154 {
1155 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1156 struct drm_device *dev = encoder->base.dev;
1157 struct drm_i915_private *dev_priv = dev->dev_private;
1158 struct intel_crtc *intel_crtc =
1159 to_intel_crtc(encoder->base.crtc);
1160 enum dpio_channel port = vlv_dport_to_channel(dport);
1161 int pipe = intel_crtc->pipe;
1162
1163 if (!IS_VALLEYVIEW(dev))
1164 return;
1165
1166 /* Program Tx lane resets to default */
1167 mutex_lock(&dev_priv->dpio_lock);
1168 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
1169 DPIO_PCS_TX_LANE2_RESET |
1170 DPIO_PCS_TX_LANE1_RESET);
1171 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
1172 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1173 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1174 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1175 DPIO_PCS_CLK_SOFT_RESET);
1176
1177 /* Fix up inter-pair skew failure */
1178 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1179 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1180 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
1181
1182 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1183 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1184 mutex_unlock(&dev_priv->dpio_lock);
1185 }
1186
vlv_hdmi_post_disable(struct intel_encoder * encoder)1187 static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
1188 {
1189 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1190 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1191 struct intel_crtc *intel_crtc =
1192 to_intel_crtc(encoder->base.crtc);
1193 enum dpio_channel port = vlv_dport_to_channel(dport);
1194 int pipe = intel_crtc->pipe;
1195
1196 /* Reset lanes to avoid HDMI flicker (VLV w/a) */
1197 mutex_lock(&dev_priv->dpio_lock);
1198 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);
1199 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);
1200 mutex_unlock(&dev_priv->dpio_lock);
1201 }
1202
intel_hdmi_destroy(struct drm_connector * connector)1203 static void intel_hdmi_destroy(struct drm_connector *connector)
1204 {
1205 drm_connector_cleanup(connector);
1206 kfree(connector);
1207 }
1208
1209 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
1210 .dpms = intel_connector_dpms,
1211 .detect = intel_hdmi_detect,
1212 .fill_modes = drm_helper_probe_single_connector_modes,
1213 .set_property = intel_hdmi_set_property,
1214 .destroy = intel_hdmi_destroy,
1215 };
1216
1217 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
1218 .get_modes = intel_hdmi_get_modes,
1219 .mode_valid = intel_hdmi_mode_valid,
1220 .best_encoder = intel_best_encoder,
1221 };
1222
1223 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
1224 .destroy = intel_encoder_destroy,
1225 };
1226
1227 static void
intel_hdmi_add_properties(struct intel_hdmi * intel_hdmi,struct drm_connector * connector)1228 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
1229 {
1230 intel_attach_force_audio_property(connector);
1231 intel_attach_broadcast_rgb_property(connector);
1232 intel_hdmi->color_range_auto = true;
1233 }
1234
intel_hdmi_init_connector(struct intel_digital_port * intel_dig_port,struct intel_connector * intel_connector)1235 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1236 struct intel_connector *intel_connector)
1237 {
1238 struct drm_connector *connector = &intel_connector->base;
1239 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
1240 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1241 struct drm_device *dev = intel_encoder->base.dev;
1242 struct drm_i915_private *dev_priv = dev->dev_private;
1243 enum port port = intel_dig_port->port;
1244
1245 drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
1246 DRM_MODE_CONNECTOR_HDMIA);
1247 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
1248
1249 connector->interlace_allowed = 1;
1250 connector->doublescan_allowed = 0;
1251 connector->stereo_allowed = 1;
1252
1253 switch (port) {
1254 case PORT_B:
1255 intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
1256 intel_encoder->hpd_pin = HPD_PORT_B;
1257 break;
1258 case PORT_C:
1259 intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
1260 intel_encoder->hpd_pin = HPD_PORT_C;
1261 break;
1262 case PORT_D:
1263 intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
1264 intel_encoder->hpd_pin = HPD_PORT_D;
1265 break;
1266 case PORT_A:
1267 intel_encoder->hpd_pin = HPD_PORT_A;
1268 /* Internal port only for eDP. */
1269 default:
1270 BUG();
1271 }
1272
1273 if (IS_VALLEYVIEW(dev)) {
1274 intel_hdmi->write_infoframe = vlv_write_infoframe;
1275 intel_hdmi->set_infoframes = vlv_set_infoframes;
1276 } else if (!HAS_PCH_SPLIT(dev)) {
1277 intel_hdmi->write_infoframe = g4x_write_infoframe;
1278 intel_hdmi->set_infoframes = g4x_set_infoframes;
1279 } else if (HAS_DDI(dev)) {
1280 intel_hdmi->write_infoframe = hsw_write_infoframe;
1281 intel_hdmi->set_infoframes = hsw_set_infoframes;
1282 } else if (HAS_PCH_IBX(dev)) {
1283 intel_hdmi->write_infoframe = ibx_write_infoframe;
1284 intel_hdmi->set_infoframes = ibx_set_infoframes;
1285 } else {
1286 intel_hdmi->write_infoframe = cpt_write_infoframe;
1287 intel_hdmi->set_infoframes = cpt_set_infoframes;
1288 }
1289
1290 if (HAS_DDI(dev))
1291 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
1292 else
1293 intel_connector->get_hw_state = intel_connector_get_hw_state;
1294 intel_connector->unregister = intel_connector_unregister;
1295
1296 intel_hdmi_add_properties(intel_hdmi, connector);
1297
1298 intel_connector_attach_encoder(intel_connector, intel_encoder);
1299 drm_sysfs_connector_add(connector);
1300
1301 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1302 * 0xd. Failure to do so will result in spurious interrupts being
1303 * generated on the port when a cable is not attached.
1304 */
1305 if (IS_G4X(dev) && !IS_GM45(dev)) {
1306 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1307 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1308 }
1309 }
1310
intel_hdmi_init(struct drm_device * dev,int hdmi_reg,enum port port)1311 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port)
1312 {
1313 struct intel_digital_port *intel_dig_port;
1314 struct intel_encoder *intel_encoder;
1315 struct intel_connector *intel_connector;
1316
1317 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
1318 if (!intel_dig_port)
1319 return;
1320
1321 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
1322 if (!intel_connector) {
1323 kfree(intel_dig_port);
1324 return;
1325 }
1326
1327 intel_encoder = &intel_dig_port->base;
1328
1329 drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
1330 DRM_MODE_ENCODER_TMDS);
1331
1332 intel_encoder->compute_config = intel_hdmi_compute_config;
1333 intel_encoder->mode_set = intel_hdmi_mode_set;
1334 intel_encoder->disable = intel_disable_hdmi;
1335 intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
1336 intel_encoder->get_config = intel_hdmi_get_config;
1337 if (IS_VALLEYVIEW(dev)) {
1338 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
1339 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
1340 intel_encoder->enable = vlv_enable_hdmi;
1341 intel_encoder->post_disable = vlv_hdmi_post_disable;
1342 } else {
1343 intel_encoder->enable = intel_enable_hdmi;
1344 }
1345
1346 intel_encoder->type = INTEL_OUTPUT_HDMI;
1347 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
1348 intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
1349 /*
1350 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
1351 * to work on real hardware. And since g4x can send infoframes to
1352 * only one port anyway, nothing is lost by allowing it.
1353 */
1354 if (IS_G4X(dev))
1355 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
1356
1357 intel_dig_port->port = port;
1358 intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
1359 intel_dig_port->dp.output_reg = 0;
1360
1361 intel_hdmi_init_connector(intel_dig_port, intel_connector);
1362 }
1363