1 /* $NetBSD: intel_tc.c,v 1.3 2021/12/19 11:49:11 riastradh Exp $ */
2
3 // SPDX-License-Identifier: MIT
4 /*
5 * Copyright © 2019 Intel Corporation
6 */
7
8 #include <sys/cdefs.h>
9 __KERNEL_RCSID(0, "$NetBSD: intel_tc.c,v 1.3 2021/12/19 11:49:11 riastradh Exp $");
10
11 #include "i915_drv.h"
12 #include "intel_display.h"
13 #include "intel_display_types.h"
14 #include "intel_dp_mst.h"
15 #include "intel_tc.h"
16
17 #include <linux/nbsd-namespace.h>
18
tc_port_mode_name(enum tc_port_mode mode)19 static const char *tc_port_mode_name(enum tc_port_mode mode)
20 {
21 static const char * const names[] = {
22 [TC_PORT_TBT_ALT] = "tbt-alt",
23 [TC_PORT_DP_ALT] = "dp-alt",
24 [TC_PORT_LEGACY] = "legacy",
25 };
26
27 if (WARN_ON(mode >= ARRAY_SIZE(names)))
28 mode = TC_PORT_TBT_ALT;
29
30 return names[mode];
31 }
32
33 static void
tc_port_load_fia_params(struct drm_i915_private * i915,struct intel_digital_port * dig_port)34 tc_port_load_fia_params(struct drm_i915_private *i915,
35 struct intel_digital_port *dig_port)
36 {
37 enum port port = dig_port->base.port;
38 enum tc_port tc_port = intel_port_to_tc(i915, port);
39 u32 modular_fia;
40
41 if (INTEL_INFO(i915)->display.has_modular_fia) {
42 modular_fia = intel_uncore_read(&i915->uncore,
43 PORT_TX_DFLEXDPSP(FIA1));
44 modular_fia &= MODULAR_FIA_MASK;
45 } else {
46 modular_fia = 0;
47 }
48
49 /*
50 * Each Modular FIA instance houses 2 TC ports. In SOC that has more
51 * than two TC ports, there are multiple instances of Modular FIA.
52 */
53 if (modular_fia) {
54 dig_port->tc_phy_fia = tc_port / 2;
55 dig_port->tc_phy_fia_idx = tc_port % 2;
56 } else {
57 dig_port->tc_phy_fia = FIA1;
58 dig_port->tc_phy_fia_idx = tc_port;
59 }
60 }
61
intel_tc_port_get_lane_mask(struct intel_digital_port * dig_port)62 u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port)
63 {
64 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
65 struct intel_uncore *uncore = &i915->uncore;
66 u32 lane_mask;
67
68 lane_mask = intel_uncore_read(uncore,
69 PORT_TX_DFLEXDPSP(dig_port->tc_phy_fia));
70
71 WARN_ON(lane_mask == 0xffffffff);
72
73 lane_mask &= DP_LANE_ASSIGNMENT_MASK(dig_port->tc_phy_fia_idx);
74 return lane_mask >> DP_LANE_ASSIGNMENT_SHIFT(dig_port->tc_phy_fia_idx);
75 }
76
intel_tc_port_get_pin_assignment_mask(struct intel_digital_port * dig_port)77 u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port)
78 {
79 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
80 struct intel_uncore *uncore = &i915->uncore;
81 u32 pin_mask;
82
83 pin_mask = intel_uncore_read(uncore,
84 PORT_TX_DFLEXPA1(dig_port->tc_phy_fia));
85
86 WARN_ON(pin_mask == 0xffffffff);
87
88 return (pin_mask & DP_PIN_ASSIGNMENT_MASK(dig_port->tc_phy_fia_idx)) >>
89 DP_PIN_ASSIGNMENT_SHIFT(dig_port->tc_phy_fia_idx);
90 }
91
intel_tc_port_fia_max_lane_count(struct intel_digital_port * dig_port)92 int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port)
93 {
94 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
95 intel_wakeref_t wakeref;
96 u32 lane_mask;
97
98 if (dig_port->tc_mode != TC_PORT_DP_ALT)
99 return 4;
100
101 lane_mask = 0;
102 with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref)
103 lane_mask = intel_tc_port_get_lane_mask(dig_port);
104
105 switch (lane_mask) {
106 default:
107 MISSING_CASE(lane_mask);
108 /* fall-through */
109 case 0x1:
110 case 0x2:
111 case 0x4:
112 case 0x8:
113 return 1;
114 case 0x3:
115 case 0xc:
116 return 2;
117 case 0xf:
118 return 4;
119 }
120 }
121
intel_tc_port_set_fia_lane_count(struct intel_digital_port * dig_port,int required_lanes)122 void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
123 int required_lanes)
124 {
125 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
126 bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
127 struct intel_uncore *uncore = &i915->uncore;
128 u32 val;
129
130 WARN_ON(lane_reversal && dig_port->tc_mode != TC_PORT_LEGACY);
131
132 val = intel_uncore_read(uncore,
133 PORT_TX_DFLEXDPMLE1(dig_port->tc_phy_fia));
134 val &= ~DFLEXDPMLE1_DPMLETC_MASK(dig_port->tc_phy_fia_idx);
135
136 switch (required_lanes) {
137 case 1:
138 val |= lane_reversal ?
139 DFLEXDPMLE1_DPMLETC_ML3(dig_port->tc_phy_fia_idx) :
140 DFLEXDPMLE1_DPMLETC_ML0(dig_port->tc_phy_fia_idx);
141 break;
142 case 2:
143 val |= lane_reversal ?
144 DFLEXDPMLE1_DPMLETC_ML3_2(dig_port->tc_phy_fia_idx) :
145 DFLEXDPMLE1_DPMLETC_ML1_0(dig_port->tc_phy_fia_idx);
146 break;
147 case 4:
148 val |= DFLEXDPMLE1_DPMLETC_ML3_0(dig_port->tc_phy_fia_idx);
149 break;
150 default:
151 MISSING_CASE(required_lanes);
152 }
153
154 intel_uncore_write(uncore,
155 PORT_TX_DFLEXDPMLE1(dig_port->tc_phy_fia), val);
156 }
157
tc_port_fixup_legacy_flag(struct intel_digital_port * dig_port,u32 live_status_mask)158 static void tc_port_fixup_legacy_flag(struct intel_digital_port *dig_port,
159 u32 live_status_mask)
160 {
161 u32 valid_hpd_mask;
162
163 if (dig_port->tc_legacy_port)
164 valid_hpd_mask = BIT(TC_PORT_LEGACY);
165 else
166 valid_hpd_mask = BIT(TC_PORT_DP_ALT) |
167 BIT(TC_PORT_TBT_ALT);
168
169 if (!(live_status_mask & ~valid_hpd_mask))
170 return;
171
172 /* If live status mismatches the VBT flag, trust the live status. */
173 DRM_ERROR("Port %s: live status %08x mismatches the legacy port flag, fix flag\n",
174 dig_port->tc_port_name, live_status_mask);
175
176 dig_port->tc_legacy_port = !dig_port->tc_legacy_port;
177 }
178
tc_port_live_status_mask(struct intel_digital_port * dig_port)179 static u32 tc_port_live_status_mask(struct intel_digital_port *dig_port)
180 {
181 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
182 enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
183 struct intel_uncore *uncore = &i915->uncore;
184 u32 mask = 0;
185 u32 val;
186
187 val = intel_uncore_read(uncore,
188 PORT_TX_DFLEXDPSP(dig_port->tc_phy_fia));
189
190 if (val == 0xffffffff) {
191 DRM_DEBUG_KMS("Port %s: PHY in TCCOLD, nothing connected\n",
192 dig_port->tc_port_name);
193 return mask;
194 }
195
196 if (val & TC_LIVE_STATE_TBT(dig_port->tc_phy_fia_idx))
197 mask |= BIT(TC_PORT_TBT_ALT);
198 if (val & TC_LIVE_STATE_TC(dig_port->tc_phy_fia_idx))
199 mask |= BIT(TC_PORT_DP_ALT);
200
201 if (intel_uncore_read(uncore, SDEISR) & SDE_TC_HOTPLUG_ICP(tc_port))
202 mask |= BIT(TC_PORT_LEGACY);
203
204 /* The sink can be connected only in a single mode. */
205 if (!WARN_ON(hweight32(mask) > 1))
206 tc_port_fixup_legacy_flag(dig_port, mask);
207
208 return mask;
209 }
210
icl_tc_phy_status_complete(struct intel_digital_port * dig_port)211 static bool icl_tc_phy_status_complete(struct intel_digital_port *dig_port)
212 {
213 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
214 struct intel_uncore *uncore = &i915->uncore;
215 u32 val;
216
217 val = intel_uncore_read(uncore,
218 PORT_TX_DFLEXDPPMS(dig_port->tc_phy_fia));
219 if (val == 0xffffffff) {
220 DRM_DEBUG_KMS("Port %s: PHY in TCCOLD, assuming not complete\n",
221 dig_port->tc_port_name);
222 return false;
223 }
224
225 return val & DP_PHY_MODE_STATUS_COMPLETED(dig_port->tc_phy_fia_idx);
226 }
227
icl_tc_phy_set_safe_mode(struct intel_digital_port * dig_port,bool enable)228 static bool icl_tc_phy_set_safe_mode(struct intel_digital_port *dig_port,
229 bool enable)
230 {
231 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
232 struct intel_uncore *uncore = &i915->uncore;
233 u32 val;
234
235 val = intel_uncore_read(uncore,
236 PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia));
237 if (val == 0xffffffff) {
238 DRM_DEBUG_KMS("Port %s: PHY in TCCOLD, can't set safe-mode to %s\n",
239 dig_port->tc_port_name,
240 enableddisabled(enable));
241
242 return false;
243 }
244
245 val &= ~DP_PHY_MODE_STATUS_NOT_SAFE(dig_port->tc_phy_fia_idx);
246 if (!enable)
247 val |= DP_PHY_MODE_STATUS_NOT_SAFE(dig_port->tc_phy_fia_idx);
248
249 intel_uncore_write(uncore,
250 PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia), val);
251
252 if (enable && wait_for(!icl_tc_phy_status_complete(dig_port), 10))
253 DRM_DEBUG_KMS("Port %s: PHY complete clear timed out\n",
254 dig_port->tc_port_name);
255
256 return true;
257 }
258
icl_tc_phy_is_in_safe_mode(struct intel_digital_port * dig_port)259 static bool icl_tc_phy_is_in_safe_mode(struct intel_digital_port *dig_port)
260 {
261 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
262 struct intel_uncore *uncore = &i915->uncore;
263 u32 val;
264
265 val = intel_uncore_read(uncore,
266 PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia));
267 if (val == 0xffffffff) {
268 DRM_DEBUG_KMS("Port %s: PHY in TCCOLD, assume safe mode\n",
269 dig_port->tc_port_name);
270 return true;
271 }
272
273 return !(val & DP_PHY_MODE_STATUS_NOT_SAFE(dig_port->tc_phy_fia_idx));
274 }
275
276 /*
277 * This function implements the first part of the Connect Flow described by our
278 * specification, Gen11 TypeC Programming chapter. The rest of the flow (reading
279 * lanes, EDID, etc) is done as needed in the typical places.
280 *
281 * Unlike the other ports, type-C ports are not available to use as soon as we
282 * get a hotplug. The type-C PHYs can be shared between multiple controllers:
283 * display, USB, etc. As a result, handshaking through FIA is required around
284 * connect and disconnect to cleanly transfer ownership with the controller and
285 * set the type-C power state.
286 */
icl_tc_phy_connect(struct intel_digital_port * dig_port,int required_lanes)287 static void icl_tc_phy_connect(struct intel_digital_port *dig_port,
288 int required_lanes)
289 {
290 int max_lanes;
291
292 if (!icl_tc_phy_status_complete(dig_port)) {
293 DRM_DEBUG_KMS("Port %s: PHY not ready\n",
294 dig_port->tc_port_name);
295 goto out_set_tbt_alt_mode;
296 }
297
298 if (!icl_tc_phy_set_safe_mode(dig_port, false) &&
299 !WARN_ON(dig_port->tc_legacy_port))
300 goto out_set_tbt_alt_mode;
301
302 max_lanes = intel_tc_port_fia_max_lane_count(dig_port);
303 if (dig_port->tc_legacy_port) {
304 WARN_ON(max_lanes != 4);
305 dig_port->tc_mode = TC_PORT_LEGACY;
306
307 return;
308 }
309
310 /*
311 * Now we have to re-check the live state, in case the port recently
312 * became disconnected. Not necessary for legacy mode.
313 */
314 if (!(tc_port_live_status_mask(dig_port) & BIT(TC_PORT_DP_ALT))) {
315 DRM_DEBUG_KMS("Port %s: PHY sudden disconnect\n",
316 dig_port->tc_port_name);
317 goto out_set_safe_mode;
318 }
319
320 if (max_lanes < required_lanes) {
321 DRM_DEBUG_KMS("Port %s: PHY max lanes %d < required lanes %d\n",
322 dig_port->tc_port_name,
323 max_lanes, required_lanes);
324 goto out_set_safe_mode;
325 }
326
327 dig_port->tc_mode = TC_PORT_DP_ALT;
328
329 return;
330
331 out_set_safe_mode:
332 icl_tc_phy_set_safe_mode(dig_port, true);
333 out_set_tbt_alt_mode:
334 dig_port->tc_mode = TC_PORT_TBT_ALT;
335 }
336
337 /*
338 * See the comment at the connect function. This implements the Disconnect
339 * Flow.
340 */
icl_tc_phy_disconnect(struct intel_digital_port * dig_port)341 static void icl_tc_phy_disconnect(struct intel_digital_port *dig_port)
342 {
343 switch (dig_port->tc_mode) {
344 case TC_PORT_LEGACY:
345 /* Nothing to do, we never disconnect from legacy mode */
346 break;
347 case TC_PORT_DP_ALT:
348 icl_tc_phy_set_safe_mode(dig_port, true);
349 dig_port->tc_mode = TC_PORT_TBT_ALT;
350 break;
351 case TC_PORT_TBT_ALT:
352 /* Nothing to do, we stay in TBT-alt mode */
353 break;
354 default:
355 MISSING_CASE(dig_port->tc_mode);
356 }
357 }
358
icl_tc_phy_is_connected(struct intel_digital_port * dig_port)359 static bool icl_tc_phy_is_connected(struct intel_digital_port *dig_port)
360 {
361 if (!icl_tc_phy_status_complete(dig_port)) {
362 DRM_DEBUG_KMS("Port %s: PHY status not complete\n",
363 dig_port->tc_port_name);
364 return dig_port->tc_mode == TC_PORT_TBT_ALT;
365 }
366
367 if (icl_tc_phy_is_in_safe_mode(dig_port)) {
368 DRM_DEBUG_KMS("Port %s: PHY still in safe mode\n",
369 dig_port->tc_port_name);
370
371 return false;
372 }
373
374 return dig_port->tc_mode == TC_PORT_DP_ALT ||
375 dig_port->tc_mode == TC_PORT_LEGACY;
376 }
377
378 static enum tc_port_mode
intel_tc_port_get_current_mode(struct intel_digital_port * dig_port)379 intel_tc_port_get_current_mode(struct intel_digital_port *dig_port)
380 {
381 u32 live_status_mask = tc_port_live_status_mask(dig_port);
382 bool in_safe_mode = icl_tc_phy_is_in_safe_mode(dig_port);
383 enum tc_port_mode mode;
384
385 if (in_safe_mode || WARN_ON(!icl_tc_phy_status_complete(dig_port)))
386 return TC_PORT_TBT_ALT;
387
388 mode = dig_port->tc_legacy_port ? TC_PORT_LEGACY : TC_PORT_DP_ALT;
389 if (live_status_mask) {
390 enum tc_port_mode live_mode = fls(live_status_mask) - 1;
391
392 if (!WARN_ON(live_mode == TC_PORT_TBT_ALT))
393 mode = live_mode;
394 }
395
396 return mode;
397 }
398
399 static enum tc_port_mode
intel_tc_port_get_target_mode(struct intel_digital_port * dig_port)400 intel_tc_port_get_target_mode(struct intel_digital_port *dig_port)
401 {
402 u32 live_status_mask = tc_port_live_status_mask(dig_port);
403
404 if (live_status_mask)
405 return fls(live_status_mask) - 1;
406
407 return icl_tc_phy_status_complete(dig_port) &&
408 dig_port->tc_legacy_port ? TC_PORT_LEGACY :
409 TC_PORT_TBT_ALT;
410 }
411
intel_tc_port_reset_mode(struct intel_digital_port * dig_port,int required_lanes)412 static void intel_tc_port_reset_mode(struct intel_digital_port *dig_port,
413 int required_lanes)
414 {
415 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
416 enum tc_port_mode old_tc_mode = dig_port->tc_mode;
417
418 intel_display_power_flush_work(i915);
419 WARN_ON(intel_display_power_is_enabled(i915,
420 intel_aux_power_domain(dig_port)));
421
422 icl_tc_phy_disconnect(dig_port);
423 icl_tc_phy_connect(dig_port, required_lanes);
424
425 DRM_DEBUG_KMS("Port %s: TC port mode reset (%s -> %s)\n",
426 dig_port->tc_port_name,
427 tc_port_mode_name(old_tc_mode),
428 tc_port_mode_name(dig_port->tc_mode));
429 }
430
431 static void
intel_tc_port_link_init_refcount(struct intel_digital_port * dig_port,int refcount)432 intel_tc_port_link_init_refcount(struct intel_digital_port *dig_port,
433 int refcount)
434 {
435 WARN_ON(dig_port->tc_link_refcount);
436 dig_port->tc_link_refcount = refcount;
437 }
438
intel_tc_port_sanitize(struct intel_digital_port * dig_port)439 void intel_tc_port_sanitize(struct intel_digital_port *dig_port)
440 {
441 struct intel_encoder *encoder = &dig_port->base;
442 int active_links = 0;
443
444 mutex_lock(&dig_port->tc_lock);
445
446 dig_port->tc_mode = intel_tc_port_get_current_mode(dig_port);
447 if (dig_port->dp.is_mst)
448 active_links = intel_dp_mst_encoder_active_links(dig_port);
449 else if (encoder->base.crtc)
450 active_links = to_intel_crtc(encoder->base.crtc)->active;
451
452 if (active_links) {
453 if (!icl_tc_phy_is_connected(dig_port))
454 DRM_DEBUG_KMS("Port %s: PHY disconnected with %d active link(s)\n",
455 dig_port->tc_port_name, active_links);
456 intel_tc_port_link_init_refcount(dig_port, active_links);
457
458 goto out;
459 }
460
461 if (dig_port->tc_legacy_port)
462 icl_tc_phy_connect(dig_port, 1);
463
464 out:
465 DRM_DEBUG_KMS("Port %s: sanitize mode (%s)\n",
466 dig_port->tc_port_name,
467 tc_port_mode_name(dig_port->tc_mode));
468
469 mutex_unlock(&dig_port->tc_lock);
470 }
471
intel_tc_port_needs_reset(struct intel_digital_port * dig_port)472 static bool intel_tc_port_needs_reset(struct intel_digital_port *dig_port)
473 {
474 return intel_tc_port_get_target_mode(dig_port) != dig_port->tc_mode;
475 }
476
477 /*
478 * The type-C ports are different because even when they are connected, they may
479 * not be available/usable by the graphics driver: see the comment on
480 * icl_tc_phy_connect(). So in our driver instead of adding the additional
481 * concept of "usable" and make everything check for "connected and usable" we
482 * define a port as "connected" when it is not only connected, but also when it
483 * is usable by the rest of the driver. That maintains the old assumption that
484 * connected ports are usable, and avoids exposing to the users objects they
485 * can't really use.
486 */
intel_tc_port_connected(struct intel_digital_port * dig_port)487 bool intel_tc_port_connected(struct intel_digital_port *dig_port)
488 {
489 bool is_connected;
490
491 intel_tc_port_lock(dig_port);
492 is_connected = tc_port_live_status_mask(dig_port) &
493 BIT(dig_port->tc_mode);
494 intel_tc_port_unlock(dig_port);
495
496 return is_connected;
497 }
498
__intel_tc_port_lock(struct intel_digital_port * dig_port,int required_lanes)499 static void __intel_tc_port_lock(struct intel_digital_port *dig_port,
500 int required_lanes)
501 {
502 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
503 intel_wakeref_t wakeref;
504
505 wakeref = intel_display_power_get(i915, POWER_DOMAIN_DISPLAY_CORE);
506
507 mutex_lock(&dig_port->tc_lock);
508
509 if (!dig_port->tc_link_refcount &&
510 intel_tc_port_needs_reset(dig_port))
511 intel_tc_port_reset_mode(dig_port, required_lanes);
512
513 WARN_ON(dig_port->tc_lock_wakeref);
514 dig_port->tc_lock_wakeref = wakeref;
515 }
516
intel_tc_port_lock(struct intel_digital_port * dig_port)517 void intel_tc_port_lock(struct intel_digital_port *dig_port)
518 {
519 __intel_tc_port_lock(dig_port, 1);
520 }
521
intel_tc_port_unlock(struct intel_digital_port * dig_port)522 void intel_tc_port_unlock(struct intel_digital_port *dig_port)
523 {
524 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
525 intel_wakeref_t wakeref = fetch_and_zero(&dig_port->tc_lock_wakeref);
526
527 mutex_unlock(&dig_port->tc_lock);
528
529 intel_display_power_put_async(i915, POWER_DOMAIN_DISPLAY_CORE,
530 wakeref);
531 }
532
intel_tc_port_ref_held(struct intel_digital_port * dig_port)533 bool intel_tc_port_ref_held(struct intel_digital_port *dig_port)
534 {
535 return mutex_is_locked(&dig_port->tc_lock) ||
536 dig_port->tc_link_refcount;
537 }
538
intel_tc_port_get_link(struct intel_digital_port * dig_port,int required_lanes)539 void intel_tc_port_get_link(struct intel_digital_port *dig_port,
540 int required_lanes)
541 {
542 __intel_tc_port_lock(dig_port, required_lanes);
543 dig_port->tc_link_refcount++;
544 intel_tc_port_unlock(dig_port);
545 }
546
intel_tc_port_put_link(struct intel_digital_port * dig_port)547 void intel_tc_port_put_link(struct intel_digital_port *dig_port)
548 {
549 mutex_lock(&dig_port->tc_lock);
550 dig_port->tc_link_refcount--;
551 mutex_unlock(&dig_port->tc_lock);
552 }
553
intel_tc_port_init(struct intel_digital_port * dig_port,bool is_legacy)554 void intel_tc_port_init(struct intel_digital_port *dig_port, bool is_legacy)
555 {
556 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
557 enum port port = dig_port->base.port;
558 enum tc_port tc_port = intel_port_to_tc(i915, port);
559
560 if (WARN_ON(tc_port == PORT_TC_NONE))
561 return;
562
563 snprintf(dig_port->tc_port_name, sizeof(dig_port->tc_port_name),
564 "%c/TC#%d", port_name(port), tc_port + 1);
565
566 mutex_init(&dig_port->tc_lock);
567 dig_port->tc_legacy_port = is_legacy;
568 dig_port->tc_link_refcount = 0;
569 tc_port_load_fia_params(i915, dig_port);
570 }
571