1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (C) 2012-2013 Intel Corporation
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 * Copyright 2019 Joyent, Inc.
29 */
30
31 /*
32 * illumos port notes:
33 *
34 * The upstream version of this file uses conditionals of the form
35 * #if _BYTE_ORDER != _LITTLE_ENDIAN
36 * Rather than keep this file in compat with only that little bit changed,
37 * this is locally patched below.
38 *
39 * There is also a static assertion which has been commented out due to a
40 * problem with smatch.
41 */
42
43 #ifndef __NVME_H__
44 #define __NVME_H__
45
46 #ifdef _KERNEL
47 #include <sys/types.h>
48 #endif
49
50 #include <sys/param.h>
51 #include <sys/endian.h>
52
53 #define NVME_PASSTHROUGH_CMD _IOWR('n', 0, struct nvme_pt_command)
54 #define NVME_RESET_CONTROLLER _IO('n', 1)
55 #define NVME_GET_NSID _IOR('n', 2, struct nvme_get_nsid)
56 #define NVME_GET_MAX_XFER_SIZE _IOR('n', 3, uint64_t)
57
58 #define NVME_IO_TEST _IOWR('n', 100, struct nvme_io_test)
59 #define NVME_BIO_TEST _IOWR('n', 101, struct nvme_io_test)
60
61 /*
62 * Macros to deal with NVME revisions, as defined VS register
63 */
64 #define NVME_REV(x, y) (((x) << 16) | ((y) << 8))
65 #define NVME_MAJOR(r) (((r) >> 16) & 0xffff)
66 #define NVME_MINOR(r) (((r) >> 8) & 0xff)
67
68 /*
69 * Use to mark a command to apply to all namespaces, or to retrieve global
70 * log pages.
71 */
72 #define NVME_GLOBAL_NAMESPACE_TAG ((uint32_t)0xFFFFFFFF)
73
74 /* Host memory buffer sizes are always in 4096 byte chunks */
75 #define NVME_HMB_UNITS 4096
76
77 /* Many items are expressed in terms of power of two times MPS */
78 #define NVME_MPS_SHIFT 12
79
80 /* Register field definitions */
81 #define NVME_CAP_LO_REG_MQES_SHIFT (0)
82 #define NVME_CAP_LO_REG_MQES_MASK (0xFFFF)
83 #define NVME_CAP_LO_REG_CQR_SHIFT (16)
84 #define NVME_CAP_LO_REG_CQR_MASK (0x1)
85 #define NVME_CAP_LO_REG_AMS_SHIFT (17)
86 #define NVME_CAP_LO_REG_AMS_MASK (0x3)
87 #define NVME_CAP_LO_REG_TO_SHIFT (24)
88 #define NVME_CAP_LO_REG_TO_MASK (0xFF)
89 #define NVME_CAP_LO_MQES(x) \
90 (((x) >> NVME_CAP_LO_REG_MQES_SHIFT) & NVME_CAP_LO_REG_MQES_MASK)
91 #define NVME_CAP_LO_CQR(x) \
92 (((x) >> NVME_CAP_LO_REG_CQR_SHIFT) & NVME_CAP_LO_REG_CQR_MASK)
93 #define NVME_CAP_LO_AMS(x) \
94 (((x) >> NVME_CAP_LO_REG_AMS_SHIFT) & NVME_CAP_LO_REG_AMS_MASK)
95 #define NVME_CAP_LO_TO(x) \
96 (((x) >> NVME_CAP_LO_REG_TO_SHIFT) & NVME_CAP_LO_REG_TO_MASK)
97
98 #define NVME_CAP_HI_REG_DSTRD_SHIFT (0)
99 #define NVME_CAP_HI_REG_DSTRD_MASK (0xF)
100 #define NVME_CAP_HI_REG_NSSRS_SHIFT (4)
101 #define NVME_CAP_HI_REG_NSSRS_MASK (0x1)
102 #define NVME_CAP_HI_REG_CSS_SHIFT (5)
103 #define NVME_CAP_HI_REG_CSS_MASK (0xff)
104 #define NVME_CAP_HI_REG_CSS_NVM_SHIFT (5)
105 #define NVME_CAP_HI_REG_CSS_NVM_MASK (0x1)
106 #define NVME_CAP_HI_REG_BPS_SHIFT (13)
107 #define NVME_CAP_HI_REG_BPS_MASK (0x1)
108 #define NVME_CAP_HI_REG_MPSMIN_SHIFT (16)
109 #define NVME_CAP_HI_REG_MPSMIN_MASK (0xF)
110 #define NVME_CAP_HI_REG_MPSMAX_SHIFT (20)
111 #define NVME_CAP_HI_REG_MPSMAX_MASK (0xF)
112 #define NVME_CAP_HI_REG_PMRS_SHIFT (24)
113 #define NVME_CAP_HI_REG_PMRS_MASK (0x1)
114 #define NVME_CAP_HI_REG_CMBS_SHIFT (25)
115 #define NVME_CAP_HI_REG_CMBS_MASK (0x1)
116 #define NVME_CAP_HI_DSTRD(x) \
117 (((x) >> NVME_CAP_HI_REG_DSTRD_SHIFT) & NVME_CAP_HI_REG_DSTRD_MASK)
118 #define NVME_CAP_HI_NSSRS(x) \
119 (((x) >> NVME_CAP_HI_REG_NSSRS_SHIFT) & NVME_CAP_HI_REG_NSSRS_MASK)
120 #define NVME_CAP_HI_CSS(x) \
121 (((x) >> NVME_CAP_HI_REG_CSS_SHIFT) & NVME_CAP_HI_REG_CSS_MASK)
122 #define NVME_CAP_HI_CSS_NVM(x) \
123 (((x) >> NVME_CAP_HI_REG_CSS_NVM_SHIFT) & NVME_CAP_HI_REG_CSS_NVM_MASK)
124 #define NVME_CAP_HI_BPS(x) \
125 (((x) >> NVME_CAP_HI_REG_BPS_SHIFT) & NVME_CAP_HI_REG_BPS_MASK)
126 #define NVME_CAP_HI_MPSMIN(x) \
127 (((x) >> NVME_CAP_HI_REG_MPSMIN_SHIFT) & NVME_CAP_HI_REG_MPSMIN_MASK)
128 #define NVME_CAP_HI_MPSMAX(x) \
129 (((x) >> NVME_CAP_HI_REG_MPSMAX_SHIFT) & NVME_CAP_HI_REG_MPSMAX_MASK)
130 #define NVME_CAP_HI_PMRS(x) \
131 (((x) >> NVME_CAP_HI_REG_PMRS_SHIFT) & NVME_CAP_HI_REG_PMRS_MASK)
132 #define NVME_CAP_HI_CMBS(x) \
133 (((x) >> NVME_CAP_HI_REG_CMBS_SHIFT) & NVME_CAP_HI_REG_CMBS_MASK)
134
135 #define NVME_CC_REG_EN_SHIFT (0)
136 #define NVME_CC_REG_EN_MASK (0x1)
137 #define NVME_CC_REG_CSS_SHIFT (4)
138 #define NVME_CC_REG_CSS_MASK (0x7)
139 #define NVME_CC_REG_MPS_SHIFT (7)
140 #define NVME_CC_REG_MPS_MASK (0xF)
141 #define NVME_CC_REG_AMS_SHIFT (11)
142 #define NVME_CC_REG_AMS_MASK (0x7)
143 #define NVME_CC_REG_SHN_SHIFT (14)
144 #define NVME_CC_REG_SHN_MASK (0x3)
145 #define NVME_CC_REG_IOSQES_SHIFT (16)
146 #define NVME_CC_REG_IOSQES_MASK (0xF)
147 #define NVME_CC_REG_IOCQES_SHIFT (20)
148 #define NVME_CC_REG_IOCQES_MASK (0xF)
149
150 #define NVME_CSTS_REG_RDY_SHIFT (0)
151 #define NVME_CSTS_REG_RDY_MASK (0x1)
152 #define NVME_CSTS_REG_CFS_SHIFT (1)
153 #define NVME_CSTS_REG_CFS_MASK (0x1)
154 #define NVME_CSTS_REG_SHST_SHIFT (2)
155 #define NVME_CSTS_REG_SHST_MASK (0x3)
156 #define NVME_CSTS_REG_NVSRO_SHIFT (4)
157 #define NVME_CSTS_REG_NVSRO_MASK (0x1)
158 #define NVME_CSTS_REG_PP_SHIFT (5)
159 #define NVME_CSTS_REG_PP_MASK (0x1)
160
161 #define NVME_CSTS_GET_SHST(csts) (((csts) >> NVME_CSTS_REG_SHST_SHIFT) & NVME_CSTS_REG_SHST_MASK)
162
163 #define NVME_AQA_REG_ASQS_SHIFT (0)
164 #define NVME_AQA_REG_ASQS_MASK (0xFFF)
165 #define NVME_AQA_REG_ACQS_SHIFT (16)
166 #define NVME_AQA_REG_ACQS_MASK (0xFFF)
167
168 #define NVME_PMRCAP_REG_RDS_SHIFT (3)
169 #define NVME_PMRCAP_REG_RDS_MASK (0x1)
170 #define NVME_PMRCAP_REG_WDS_SHIFT (4)
171 #define NVME_PMRCAP_REG_WDS_MASK (0x1)
172 #define NVME_PMRCAP_REG_BIR_SHIFT (5)
173 #define NVME_PMRCAP_REG_BIR_MASK (0x7)
174 #define NVME_PMRCAP_REG_PMRTU_SHIFT (8)
175 #define NVME_PMRCAP_REG_PMRTU_MASK (0x3)
176 #define NVME_PMRCAP_REG_PMRWBM_SHIFT (10)
177 #define NVME_PMRCAP_REG_PMRWBM_MASK (0xf)
178 #define NVME_PMRCAP_REG_PMRTO_SHIFT (16)
179 #define NVME_PMRCAP_REG_PMRTO_MASK (0xff)
180 #define NVME_PMRCAP_REG_CMSS_SHIFT (24)
181 #define NVME_PMRCAP_REG_CMSS_MASK (0x1)
182
183 #define NVME_PMRCAP_RDS(x) \
184 (((x) >> NVME_PMRCAP_REG_RDS_SHIFT) & NVME_PMRCAP_REG_RDS_MASK)
185 #define NVME_PMRCAP_WDS(x) \
186 (((x) >> NVME_PMRCAP_REG_WDS_SHIFT) & NVME_PMRCAP_REG_WDS_MASK)
187 #define NVME_PMRCAP_BIR(x) \
188 (((x) >> NVME_PMRCAP_REG_BIR_SHIFT) & NVME_PMRCAP_REG_BIR_MASK)
189 #define NVME_PMRCAP_PMRTU(x) \
190 (((x) >> NVME_PMRCAP_REG_PMRTU_SHIFT) & NVME_PMRCAP_REG_PMRTU_MASK)
191 #define NVME_PMRCAP_PMRWBM(x) \
192 (((x) >> NVME_PMRCAP_REG_PMRWBM_SHIFT) & NVME_PMRCAP_REG_PMRWBM_MASK)
193 #define NVME_PMRCAP_PMRTO(x) \
194 (((x) >> NVME_PMRCAP_REG_PMRTO_SHIFT) & NVME_PMRCAP_REG_PMRTO_MASK)
195 #define NVME_PMRCAP_CMSS(x) \
196 (((x) >> NVME_PMRCAP_REG_CMSS_SHIFT) & NVME_PMRCAP_REG_CMSS_MASK)
197
198 /* Command field definitions */
199
200 #define NVME_CMD_FUSE_SHIFT (8)
201 #define NVME_CMD_FUSE_MASK (0x3)
202
203 #define NVME_STATUS_P_SHIFT (0)
204 #define NVME_STATUS_P_MASK (0x1)
205 #define NVME_STATUS_SC_SHIFT (1)
206 #define NVME_STATUS_SC_MASK (0xFF)
207 #define NVME_STATUS_SCT_SHIFT (9)
208 #define NVME_STATUS_SCT_MASK (0x7)
209 #define NVME_STATUS_CRD_SHIFT (12)
210 #define NVME_STATUS_CRD_MASK (0x3)
211 #define NVME_STATUS_M_SHIFT (14)
212 #define NVME_STATUS_M_MASK (0x1)
213 #define NVME_STATUS_DNR_SHIFT (15)
214 #define NVME_STATUS_DNR_MASK (0x1)
215
216 #define NVME_STATUS_GET_P(st) (((st) >> NVME_STATUS_P_SHIFT) & NVME_STATUS_P_MASK)
217 #define NVME_STATUS_GET_SC(st) (((st) >> NVME_STATUS_SC_SHIFT) & NVME_STATUS_SC_MASK)
218 #define NVME_STATUS_GET_SCT(st) (((st) >> NVME_STATUS_SCT_SHIFT) & NVME_STATUS_SCT_MASK)
219 #define NVME_STATUS_GET_CRD(st) (((st) >> NVME_STATUS_CRD_SHIFT) & NVME_STATUS_CRD_MASK)
220 #define NVME_STATUS_GET_M(st) (((st) >> NVME_STATUS_M_SHIFT) & NVME_STATUS_M_MASK)
221 #define NVME_STATUS_GET_DNR(st) (((st) >> NVME_STATUS_DNR_SHIFT) & NVME_STATUS_DNR_MASK)
222
223 #define NVME_PWR_ST_MPS_SHIFT (0)
224 #define NVME_PWR_ST_MPS_MASK (0x1)
225 #define NVME_PWR_ST_NOPS_SHIFT (1)
226 #define NVME_PWR_ST_NOPS_MASK (0x1)
227 #define NVME_PWR_ST_RRT_SHIFT (0)
228 #define NVME_PWR_ST_RRT_MASK (0x1F)
229 #define NVME_PWR_ST_RRL_SHIFT (0)
230 #define NVME_PWR_ST_RRL_MASK (0x1F)
231 #define NVME_PWR_ST_RWT_SHIFT (0)
232 #define NVME_PWR_ST_RWT_MASK (0x1F)
233 #define NVME_PWR_ST_RWL_SHIFT (0)
234 #define NVME_PWR_ST_RWL_MASK (0x1F)
235 #define NVME_PWR_ST_IPS_SHIFT (6)
236 #define NVME_PWR_ST_IPS_MASK (0x3)
237 #define NVME_PWR_ST_APW_SHIFT (0)
238 #define NVME_PWR_ST_APW_MASK (0x7)
239 #define NVME_PWR_ST_APS_SHIFT (6)
240 #define NVME_PWR_ST_APS_MASK (0x3)
241
242 /** Controller Multi-path I/O and Namespace Sharing Capabilities */
243 /* More then one port */
244 #define NVME_CTRLR_DATA_MIC_MPORTS_SHIFT (0)
245 #define NVME_CTRLR_DATA_MIC_MPORTS_MASK (0x1)
246 /* More then one controller */
247 #define NVME_CTRLR_DATA_MIC_MCTRLRS_SHIFT (1)
248 #define NVME_CTRLR_DATA_MIC_MCTRLRS_MASK (0x1)
249 /* SR-IOV Virtual Function */
250 #define NVME_CTRLR_DATA_MIC_SRIOVVF_SHIFT (2)
251 #define NVME_CTRLR_DATA_MIC_SRIOVVF_MASK (0x1)
252 /* Asymmetric Namespace Access Reporting */
253 #define NVME_CTRLR_DATA_MIC_ANAR_SHIFT (3)
254 #define NVME_CTRLR_DATA_MIC_ANAR_MASK (0x1)
255
256 /** OAES - Optional Asynchronous Events Supported */
257 /* supports Namespace Attribute Notices event */
258 #define NVME_CTRLR_DATA_OAES_NS_ATTR_SHIFT (8)
259 #define NVME_CTRLR_DATA_OAES_NS_ATTR_MASK (0x1)
260 /* supports Firmware Activation Notices event */
261 #define NVME_CTRLR_DATA_OAES_FW_ACTIVATE_SHIFT (9)
262 #define NVME_CTRLR_DATA_OAES_FW_ACTIVATE_MASK (0x1)
263 /* supports Asymmetric Namespace Access Change Notices event */
264 #define NVME_CTRLR_DATA_OAES_ASYM_NS_CHANGE_SHIFT (11)
265 #define NVME_CTRLR_DATA_OAES_ASYM_NS_CHANGE_MASK (0x1)
266 /* supports Predictable Latency Event Aggregate Log Change Notices event */
267 #define NVME_CTRLR_DATA_OAES_PREDICT_LATENCY_SHIFT (12)
268 #define NVME_CTRLR_DATA_OAES_PREDICT_LATENCY_MASK (0x1)
269 /* supports LBA Status Information Notices event */
270 #define NVME_CTRLR_DATA_OAES_LBA_STATUS_SHIFT (13)
271 #define NVME_CTRLR_DATA_OAES_LBA_STATUS_MASK (0x1)
272 /* supports Endurance Group Event Aggregate Log Page Changes Notices event */
273 #define NVME_CTRLR_DATA_OAES_ENDURANCE_GROUP_SHIFT (14)
274 #define NVME_CTRLR_DATA_OAES_ENDURANCE_GROUP_MASK (0x1)
275 /* supports Normal NVM Subsystem Shutdown event */
276 #define NVME_CTRLR_DATA_OAES_NORMAL_SHUTDOWN_SHIFT (15)
277 #define NVME_CTRLR_DATA_OAES_NORMAL_SHUTDOWN_MASK (0x1)
278 /* supports Zone Descriptor Changed Notices event */
279 #define NVME_CTRLR_DATA_OAES_ZONE_DESC_CHANGE_SHIFT (27)
280 #define NVME_CTRLR_DATA_OAES_ZONE_DESC_CHANGE_MASK (0x1)
281 /* supports Discovery Log Page Change Notification event */
282 #define NVME_CTRLR_DATA_OAES_LOG_PAGE_CHANGE_SHIFT (31)
283 #define NVME_CTRLR_DATA_OAES_LOG_PAGE_CHANGE_MASK (0x1)
284
285 /** OACS - optional admin command support */
286 /* supports security send/receive commands */
287 #define NVME_CTRLR_DATA_OACS_SECURITY_SHIFT (0)
288 #define NVME_CTRLR_DATA_OACS_SECURITY_MASK (0x1)
289 /* supports format nvm command */
290 #define NVME_CTRLR_DATA_OACS_FORMAT_SHIFT (1)
291 #define NVME_CTRLR_DATA_OACS_FORMAT_MASK (0x1)
292 /* supports firmware activate/download commands */
293 #define NVME_CTRLR_DATA_OACS_FIRMWARE_SHIFT (2)
294 #define NVME_CTRLR_DATA_OACS_FIRMWARE_MASK (0x1)
295 /* supports namespace management commands */
296 #define NVME_CTRLR_DATA_OACS_NSMGMT_SHIFT (3)
297 #define NVME_CTRLR_DATA_OACS_NSMGMT_MASK (0x1)
298 /* supports Device Self-test command */
299 #define NVME_CTRLR_DATA_OACS_SELFTEST_SHIFT (4)
300 #define NVME_CTRLR_DATA_OACS_SELFTEST_MASK (0x1)
301 /* supports Directives */
302 #define NVME_CTRLR_DATA_OACS_DIRECTIVES_SHIFT (5)
303 #define NVME_CTRLR_DATA_OACS_DIRECTIVES_MASK (0x1)
304 /* supports NVMe-MI Send/Receive */
305 #define NVME_CTRLR_DATA_OACS_NVMEMI_SHIFT (6)
306 #define NVME_CTRLR_DATA_OACS_NVMEMI_MASK (0x1)
307 /* supports Virtualization Management */
308 #define NVME_CTRLR_DATA_OACS_VM_SHIFT (7)
309 #define NVME_CTRLR_DATA_OACS_VM_MASK (0x1)
310 /* supports Doorbell Buffer Config */
311 #define NVME_CTRLR_DATA_OACS_DBBUFFER_SHIFT (8)
312 #define NVME_CTRLR_DATA_OACS_DBBUFFER_MASK (0x1)
313 /* supports Get LBA Status */
314 #define NVME_CTRLR_DATA_OACS_GETLBA_SHIFT (9)
315 #define NVME_CTRLR_DATA_OACS_GETLBA_MASK (0x1)
316
317 /** firmware updates */
318 /* first slot is read-only */
319 #define NVME_CTRLR_DATA_FRMW_SLOT1_RO_SHIFT (0)
320 #define NVME_CTRLR_DATA_FRMW_SLOT1_RO_MASK (0x1)
321 /* number of firmware slots */
322 #define NVME_CTRLR_DATA_FRMW_NUM_SLOTS_SHIFT (1)
323 #define NVME_CTRLR_DATA_FRMW_NUM_SLOTS_MASK (0x7)
324 /* firmware activation without reset */
325 #define NVME_CTRLR_DATA_FRMW_ACT_WO_RESET_SHIFT (4)
326 #define NVME_CTRLR_DATA_FRMW_ACT_WO_RESET_MASK (0x1)
327
328 /** log page attributes */
329 /* per namespace smart/health log page */
330 #define NVME_CTRLR_DATA_LPA_NS_SMART_SHIFT (0)
331 #define NVME_CTRLR_DATA_LPA_NS_SMART_MASK (0x1)
332
333 /** AVSCC - admin vendor specific command configuration */
334 /* admin vendor specific commands use spec format */
335 #define NVME_CTRLR_DATA_AVSCC_SPEC_FORMAT_SHIFT (0)
336 #define NVME_CTRLR_DATA_AVSCC_SPEC_FORMAT_MASK (0x1)
337
338 /** Autonomous Power State Transition Attributes */
339 /* Autonomous Power State Transitions supported */
340 #define NVME_CTRLR_DATA_APSTA_APST_SUPP_SHIFT (0)
341 #define NVME_CTRLR_DATA_APSTA_APST_SUPP_MASK (0x1)
342
343 /** Sanitize Capabilities */
344 /* Crypto Erase Support */
345 #define NVME_CTRLR_DATA_SANICAP_CES_SHIFT (0)
346 #define NVME_CTRLR_DATA_SANICAP_CES_MASK (0x1)
347 /* Block Erase Support */
348 #define NVME_CTRLR_DATA_SANICAP_BES_SHIFT (1)
349 #define NVME_CTRLR_DATA_SANICAP_BES_MASK (0x1)
350 /* Overwrite Support */
351 #define NVME_CTRLR_DATA_SANICAP_OWS_SHIFT (2)
352 #define NVME_CTRLR_DATA_SANICAP_OWS_MASK (0x1)
353 /* No-Deallocate Inhibited */
354 #define NVME_CTRLR_DATA_SANICAP_NDI_SHIFT (29)
355 #define NVME_CTRLR_DATA_SANICAP_NDI_MASK (0x1)
356 /* No-Deallocate Modifies Media After Sanitize */
357 #define NVME_CTRLR_DATA_SANICAP_NODMMAS_SHIFT (30)
358 #define NVME_CTRLR_DATA_SANICAP_NODMMAS_MASK (0x3)
359 #define NVME_CTRLR_DATA_SANICAP_NODMMAS_UNDEF (0)
360 #define NVME_CTRLR_DATA_SANICAP_NODMMAS_NO (1)
361 #define NVME_CTRLR_DATA_SANICAP_NODMMAS_YES (2)
362
363 /** submission queue entry size */
364 #define NVME_CTRLR_DATA_SQES_MIN_SHIFT (0)
365 #define NVME_CTRLR_DATA_SQES_MIN_MASK (0xF)
366 #define NVME_CTRLR_DATA_SQES_MAX_SHIFT (4)
367 #define NVME_CTRLR_DATA_SQES_MAX_MASK (0xF)
368
369 /** completion queue entry size */
370 #define NVME_CTRLR_DATA_CQES_MIN_SHIFT (0)
371 #define NVME_CTRLR_DATA_CQES_MIN_MASK (0xF)
372 #define NVME_CTRLR_DATA_CQES_MAX_SHIFT (4)
373 #define NVME_CTRLR_DATA_CQES_MAX_MASK (0xF)
374
375 /** optional nvm command support */
376 #define NVME_CTRLR_DATA_ONCS_COMPARE_SHIFT (0)
377 #define NVME_CTRLR_DATA_ONCS_COMPARE_MASK (0x1)
378 #define NVME_CTRLR_DATA_ONCS_WRITE_UNC_SHIFT (1)
379 #define NVME_CTRLR_DATA_ONCS_WRITE_UNC_MASK (0x1)
380 #define NVME_CTRLR_DATA_ONCS_DSM_SHIFT (2)
381 #define NVME_CTRLR_DATA_ONCS_DSM_MASK (0x1)
382 #define NVME_CTRLR_DATA_ONCS_WRZERO_SHIFT (3)
383 #define NVME_CTRLR_DATA_ONCS_WRZERO_MASK (0x1)
384 #define NVME_CTRLR_DATA_ONCS_SAVEFEAT_SHIFT (4)
385 #define NVME_CTRLR_DATA_ONCS_SAVEFEAT_MASK (0x1)
386 #define NVME_CTRLR_DATA_ONCS_RESERV_SHIFT (5)
387 #define NVME_CTRLR_DATA_ONCS_RESERV_MASK (0x1)
388 #define NVME_CTRLR_DATA_ONCS_TIMESTAMP_SHIFT (6)
389 #define NVME_CTRLR_DATA_ONCS_TIMESTAMP_MASK (0x1)
390 #define NVME_CTRLR_DATA_ONCS_VERIFY_SHIFT (7)
391 #define NVME_CTRLR_DATA_ONCS_VERIFY_MASK (0x1)
392
393 /** Fused Operation Support */
394 #define NVME_CTRLR_DATA_FUSES_CNW_SHIFT (0)
395 #define NVME_CTRLR_DATA_FUSES_CNW_MASK (0x1)
396
397 /** Format NVM Attributes */
398 #define NVME_CTRLR_DATA_FNA_FORMAT_ALL_SHIFT (0)
399 #define NVME_CTRLR_DATA_FNA_FORMAT_ALL_MASK (0x1)
400 #define NVME_CTRLR_DATA_FNA_ERASE_ALL_SHIFT (1)
401 #define NVME_CTRLR_DATA_FNA_ERASE_ALL_MASK (0x1)
402 #define NVME_CTRLR_DATA_FNA_CRYPTO_ERASE_SHIFT (2)
403 #define NVME_CTRLR_DATA_FNA_CRYPTO_ERASE_MASK (0x1)
404
405 /** volatile write cache */
406 /* volatile write cache present */
407 #define NVME_CTRLR_DATA_VWC_PRESENT_SHIFT (0)
408 #define NVME_CTRLR_DATA_VWC_PRESENT_MASK (0x1)
409 /* flush all namespaces supported */
410 #define NVME_CTRLR_DATA_VWC_ALL_SHIFT (1)
411 #define NVME_CTRLR_DATA_VWC_ALL_MASK (0x3)
412 #define NVME_CTRLR_DATA_VWC_ALL_UNKNOWN (0)
413 #define NVME_CTRLR_DATA_VWC_ALL_NO (2)
414 #define NVME_CTRLR_DATA_VWC_ALL_YES (3)
415
416 /** namespace features */
417 /* thin provisioning */
418 #define NVME_NS_DATA_NSFEAT_THIN_PROV_SHIFT (0)
419 #define NVME_NS_DATA_NSFEAT_THIN_PROV_MASK (0x1)
420 /* NAWUN, NAWUPF, and NACWU fields are valid */
421 #define NVME_NS_DATA_NSFEAT_NA_FIELDS_SHIFT (1)
422 #define NVME_NS_DATA_NSFEAT_NA_FIELDS_MASK (0x1)
423 /* Deallocated or Unwritten Logical Block errors supported */
424 #define NVME_NS_DATA_NSFEAT_DEALLOC_SHIFT (2)
425 #define NVME_NS_DATA_NSFEAT_DEALLOC_MASK (0x1)
426 /* NGUID and EUI64 fields are not reusable */
427 #define NVME_NS_DATA_NSFEAT_NO_ID_REUSE_SHIFT (3)
428 #define NVME_NS_DATA_NSFEAT_NO_ID_REUSE_MASK (0x1)
429 /* NPWG, NPWA, NPDG, NPDA, and NOWS are valid */
430 #define NVME_NS_DATA_NSFEAT_NPVALID_SHIFT (4)
431 #define NVME_NS_DATA_NSFEAT_NPVALID_MASK (0x1)
432
433 /** formatted lba size */
434 #define NVME_NS_DATA_FLBAS_FORMAT_SHIFT (0)
435 #define NVME_NS_DATA_FLBAS_FORMAT_MASK (0xF)
436 #define NVME_NS_DATA_FLBAS_EXTENDED_SHIFT (4)
437 #define NVME_NS_DATA_FLBAS_EXTENDED_MASK (0x1)
438
439 /** metadata capabilities */
440 /* metadata can be transferred as part of data prp list */
441 #define NVME_NS_DATA_MC_EXTENDED_SHIFT (0)
442 #define NVME_NS_DATA_MC_EXTENDED_MASK (0x1)
443 /* metadata can be transferred with separate metadata pointer */
444 #define NVME_NS_DATA_MC_POINTER_SHIFT (1)
445 #define NVME_NS_DATA_MC_POINTER_MASK (0x1)
446
447 /** end-to-end data protection capabilities */
448 /* protection information type 1 */
449 #define NVME_NS_DATA_DPC_PIT1_SHIFT (0)
450 #define NVME_NS_DATA_DPC_PIT1_MASK (0x1)
451 /* protection information type 2 */
452 #define NVME_NS_DATA_DPC_PIT2_SHIFT (1)
453 #define NVME_NS_DATA_DPC_PIT2_MASK (0x1)
454 /* protection information type 3 */
455 #define NVME_NS_DATA_DPC_PIT3_SHIFT (2)
456 #define NVME_NS_DATA_DPC_PIT3_MASK (0x1)
457 /* first eight bytes of metadata */
458 #define NVME_NS_DATA_DPC_MD_START_SHIFT (3)
459 #define NVME_NS_DATA_DPC_MD_START_MASK (0x1)
460 /* last eight bytes of metadata */
461 #define NVME_NS_DATA_DPC_MD_END_SHIFT (4)
462 #define NVME_NS_DATA_DPC_MD_END_MASK (0x1)
463
464 /** end-to-end data protection type settings */
465 /* protection information type */
466 #define NVME_NS_DATA_DPS_PIT_SHIFT (0)
467 #define NVME_NS_DATA_DPS_PIT_MASK (0x7)
468 /* 1 == protection info transferred at start of metadata */
469 /* 0 == protection info transferred at end of metadata */
470 #define NVME_NS_DATA_DPS_MD_START_SHIFT (3)
471 #define NVME_NS_DATA_DPS_MD_START_MASK (0x1)
472
473 /** Namespace Multi-path I/O and Namespace Sharing Capabilities */
474 /* the namespace may be attached to two or more controllers */
475 #define NVME_NS_DATA_NMIC_MAY_BE_SHARED_SHIFT (0)
476 #define NVME_NS_DATA_NMIC_MAY_BE_SHARED_MASK (0x1)
477
478 /** Reservation Capabilities */
479 /* Persist Through Power Loss */
480 #define NVME_NS_DATA_RESCAP_PTPL_SHIFT (0)
481 #define NVME_NS_DATA_RESCAP_PTPL_MASK (0x1)
482 /* supports the Write Exclusive */
483 #define NVME_NS_DATA_RESCAP_WR_EX_SHIFT (1)
484 #define NVME_NS_DATA_RESCAP_WR_EX_MASK (0x1)
485 /* supports the Exclusive Access */
486 #define NVME_NS_DATA_RESCAP_EX_AC_SHIFT (2)
487 #define NVME_NS_DATA_RESCAP_EX_AC_MASK (0x1)
488 /* supports the Write Exclusive – Registrants Only */
489 #define NVME_NS_DATA_RESCAP_WR_EX_RO_SHIFT (3)
490 #define NVME_NS_DATA_RESCAP_WR_EX_RO_MASK (0x1)
491 /* supports the Exclusive Access - Registrants Only */
492 #define NVME_NS_DATA_RESCAP_EX_AC_RO_SHIFT (4)
493 #define NVME_NS_DATA_RESCAP_EX_AC_RO_MASK (0x1)
494 /* supports the Write Exclusive – All Registrants */
495 #define NVME_NS_DATA_RESCAP_WR_EX_AR_SHIFT (5)
496 #define NVME_NS_DATA_RESCAP_WR_EX_AR_MASK (0x1)
497 /* supports the Exclusive Access - All Registrants */
498 #define NVME_NS_DATA_RESCAP_EX_AC_AR_SHIFT (6)
499 #define NVME_NS_DATA_RESCAP_EX_AC_AR_MASK (0x1)
500 /* Ignore Existing Key is used as defined in revision 1.3 or later */
501 #define NVME_NS_DATA_RESCAP_IEKEY13_SHIFT (7)
502 #define NVME_NS_DATA_RESCAP_IEKEY13_MASK (0x1)
503
504 /** Format Progress Indicator */
505 /* percentage of the Format NVM command that remains to be completed */
506 #define NVME_NS_DATA_FPI_PERC_SHIFT (0)
507 #define NVME_NS_DATA_FPI_PERC_MASK (0x7f)
508 /* namespace supports the Format Progress Indicator */
509 #define NVME_NS_DATA_FPI_SUPP_SHIFT (7)
510 #define NVME_NS_DATA_FPI_SUPP_MASK (0x1)
511
512 /** Deallocate Logical Block Features */
513 /* deallocated logical block read behavior */
514 #define NVME_NS_DATA_DLFEAT_READ_SHIFT (0)
515 #define NVME_NS_DATA_DLFEAT_READ_MASK (0x07)
516 #define NVME_NS_DATA_DLFEAT_READ_NR (0x00)
517 #define NVME_NS_DATA_DLFEAT_READ_00 (0x01)
518 #define NVME_NS_DATA_DLFEAT_READ_FF (0x02)
519 /* supports the Deallocate bit in the Write Zeroes */
520 #define NVME_NS_DATA_DLFEAT_DWZ_SHIFT (3)
521 #define NVME_NS_DATA_DLFEAT_DWZ_MASK (0x01)
522 /* Guard field for deallocated logical blocks is set to the CRC */
523 #define NVME_NS_DATA_DLFEAT_GCRC_SHIFT (4)
524 #define NVME_NS_DATA_DLFEAT_GCRC_MASK (0x01)
525
526 /** lba format support */
527 /* metadata size */
528 #define NVME_NS_DATA_LBAF_MS_SHIFT (0)
529 #define NVME_NS_DATA_LBAF_MS_MASK (0xFFFF)
530 /* lba data size */
531 #define NVME_NS_DATA_LBAF_LBADS_SHIFT (16)
532 #define NVME_NS_DATA_LBAF_LBADS_MASK (0xFF)
533 /* relative performance */
534 #define NVME_NS_DATA_LBAF_RP_SHIFT (24)
535 #define NVME_NS_DATA_LBAF_RP_MASK (0x3)
536
537 enum nvme_critical_warning_state {
538 NVME_CRIT_WARN_ST_AVAILABLE_SPARE = 0x1,
539 NVME_CRIT_WARN_ST_TEMPERATURE = 0x2,
540 NVME_CRIT_WARN_ST_DEVICE_RELIABILITY = 0x4,
541 NVME_CRIT_WARN_ST_READ_ONLY = 0x8,
542 NVME_CRIT_WARN_ST_VOLATILE_MEMORY_BACKUP = 0x10,
543 };
544 #define NVME_CRIT_WARN_ST_RESERVED_MASK (0xE0)
545 #define NVME_ASYNC_EVENT_NS_ATTRIBUTE (0x100)
546 #define NVME_ASYNC_EVENT_FW_ACTIVATE (0x200)
547
548 /* slot for current FW */
549 #define NVME_FIRMWARE_PAGE_AFI_SLOT_SHIFT (0)
550 #define NVME_FIRMWARE_PAGE_AFI_SLOT_MASK (0x7)
551
552 /* Commands Supported and Effects */
553 #define NVME_CE_PAGE_CSUP_SHIFT (0)
554 #define NVME_CE_PAGE_CSUP_MASK (0x1)
555 #define NVME_CE_PAGE_LBCC_SHIFT (1)
556 #define NVME_CE_PAGE_LBCC_MASK (0x1)
557 #define NVME_CE_PAGE_NCC_SHIFT (2)
558 #define NVME_CE_PAGE_NCC_MASK (0x1)
559 #define NVME_CE_PAGE_NIC_SHIFT (3)
560 #define NVME_CE_PAGE_NIC_MASK (0x1)
561 #define NVME_CE_PAGE_CCC_SHIFT (4)
562 #define NVME_CE_PAGE_CCC_MASK (0x1)
563 #define NVME_CE_PAGE_CSE_SHIFT (16)
564 #define NVME_CE_PAGE_CSE_MASK (0x7)
565 #define NVME_CE_PAGE_UUID_SHIFT (19)
566 #define NVME_CE_PAGE_UUID_MASK (0x1)
567
568 /* Sanitize Status */
569 #define NVME_SS_PAGE_SSTAT_STATUS_SHIFT (0)
570 #define NVME_SS_PAGE_SSTAT_STATUS_MASK (0x7)
571 #define NVME_SS_PAGE_SSTAT_STATUS_NEVER (0)
572 #define NVME_SS_PAGE_SSTAT_STATUS_COMPLETED (1)
573 #define NVME_SS_PAGE_SSTAT_STATUS_INPROG (2)
574 #define NVME_SS_PAGE_SSTAT_STATUS_FAILED (3)
575 #define NVME_SS_PAGE_SSTAT_STATUS_COMPLETEDWD (4)
576 #define NVME_SS_PAGE_SSTAT_PASSES_SHIFT (3)
577 #define NVME_SS_PAGE_SSTAT_PASSES_MASK (0x1f)
578 #define NVME_SS_PAGE_SSTAT_GDE_SHIFT (8)
579 #define NVME_SS_PAGE_SSTAT_GDE_MASK (0x1)
580
581 /* Features */
582 /* Get Features */
583 #define NVME_FEAT_GET_SEL_SHIFT (8)
584 #define NVME_FEAT_GET_SEL_MASK (0x7)
585 #define NVME_FEAT_GET_FID_SHIFT (0)
586 #define NVME_FEAT_GET_FID_MASK (0xff)
587
588 /* Set Features */
589 #define NVME_FEAT_SET_SV_SHIFT (31)
590 #define NVME_FEAT_SET_SV_MASK (0x1)
591 #define NVME_FEAT_SET_FID_SHIFT (0)
592 #define NVME_FEAT_SET_FID_MASK (0xff)
593
594 /* Helper macro to combine *_MASK and *_SHIFT defines */
595 #define NVMEB(name) (name##_MASK << name##_SHIFT)
596
597 /* Helper macro to extract value from x */
598 #define NVMEV(name, x) (((x) >> name##_SHIFT) & name##_MASK)
599
600 /* CC register SHN field values */
601 enum shn_value {
602 NVME_SHN_NORMAL = 0x1,
603 NVME_SHN_ABRUPT = 0x2,
604 };
605
606 /* CSTS register SHST field values */
607 enum shst_value {
608 NVME_SHST_NORMAL = 0x0,
609 NVME_SHST_OCCURRING = 0x1,
610 NVME_SHST_COMPLETE = 0x2,
611 };
612
613 struct nvme_registers {
614 uint32_t cap_lo; /* controller capabilities */
615 uint32_t cap_hi;
616 uint32_t vs; /* version */
617 uint32_t intms; /* interrupt mask set */
618 uint32_t intmc; /* interrupt mask clear */
619 uint32_t cc; /* controller configuration */
620 uint32_t reserved1;
621 uint32_t csts; /* controller status */
622 uint32_t nssr; /* NVM Subsystem Reset */
623 uint32_t aqa; /* admin queue attributes */
624 uint64_t asq; /* admin submission queue base addr */
625 uint64_t acq; /* admin completion queue base addr */
626 uint32_t cmbloc; /* Controller Memory Buffer Location */
627 uint32_t cmbsz; /* Controller Memory Buffer Size */
628 uint32_t bpinfo; /* Boot Partition Information */
629 uint32_t bprsel; /* Boot Partition Read Select */
630 uint64_t bpmbl; /* Boot Partition Memory Buffer Location */
631 uint64_t cmbmsc; /* Controller Memory Buffer Memory Space Control */
632 uint32_t cmbsts; /* Controller Memory Buffer Status */
633 uint8_t reserved3[3492]; /* 5Ch - DFFh */
634 uint32_t pmrcap; /* Persistent Memory Capabilities */
635 uint32_t pmrctl; /* Persistent Memory Region Control */
636 uint32_t pmrsts; /* Persistent Memory Region Status */
637 uint32_t pmrebs; /* Persistent Memory Region Elasticity Buffer Size */
638 uint32_t pmrswtp; /* Persistent Memory Region Sustained Write Throughput */
639 uint32_t pmrmsc_lo; /* Persistent Memory Region Controller Memory Space Control */
640 uint32_t pmrmsc_hi;
641 uint8_t reserved4[484]; /* E1Ch - FFFh */
642 struct {
643 uint32_t sq_tdbl; /* submission queue tail doorbell */
644 uint32_t cq_hdbl; /* completion queue head doorbell */
645 } doorbell[1];
646 };
647
648 _Static_assert(sizeof(struct nvme_registers) == 0x1008, "bad size for nvme_registers");
649
650 struct nvme_command {
651 /* dword 0 */
652 uint8_t opc; /* opcode */
653 uint8_t fuse; /* fused operation */
654 uint16_t cid; /* command identifier */
655
656 /* dword 1 */
657 uint32_t nsid; /* namespace identifier */
658
659 /* dword 2-3 */
660 uint32_t rsvd2;
661 uint32_t rsvd3;
662
663 /* dword 4-5 */
664 uint64_t mptr; /* metadata pointer */
665
666 /* dword 6-7 */
667 uint64_t prp1; /* prp entry 1 */
668
669 /* dword 8-9 */
670 uint64_t prp2; /* prp entry 2 */
671
672 /* dword 10-15 */
673 uint32_t cdw10; /* command-specific */
674 uint32_t cdw11; /* command-specific */
675 uint32_t cdw12; /* command-specific */
676 uint32_t cdw13; /* command-specific */
677 uint32_t cdw14; /* command-specific */
678 uint32_t cdw15; /* command-specific */
679 };
680
681 _Static_assert(sizeof(struct nvme_command) == 16 * 4, "bad size for nvme_command");
682
683 struct nvme_completion {
684 /* dword 0 */
685 uint32_t cdw0; /* command-specific */
686
687 /* dword 1 */
688 uint32_t rsvd1;
689
690 /* dword 2 */
691 uint16_t sqhd; /* submission queue head pointer */
692 uint16_t sqid; /* submission queue identifier */
693
694 /* dword 3 */
695 uint16_t cid; /* command identifier */
696 uint16_t status;
697 } __aligned(8); /* riscv: nvme_qpair_process_completions has better code gen */
698
699 _Static_assert(sizeof(struct nvme_completion) == 4 * 4, "bad size for nvme_completion");
700
701 struct nvme_dsm_range {
702 uint32_t attributes;
703 uint32_t length;
704 uint64_t starting_lba;
705 };
706
707 /* Largest DSM Trim that can be done */
708 #define NVME_MAX_DSM_TRIM 4096
709
710 _Static_assert(sizeof(struct nvme_dsm_range) == 16, "bad size for nvme_dsm_ranage");
711
712 /* status code types */
713 enum nvme_status_code_type {
714 NVME_SCT_GENERIC = 0x0,
715 NVME_SCT_COMMAND_SPECIFIC = 0x1,
716 NVME_SCT_MEDIA_ERROR = 0x2,
717 NVME_SCT_PATH_RELATED = 0x3,
718 /* 0x3-0x6 - reserved */
719 NVME_SCT_VENDOR_SPECIFIC = 0x7,
720 };
721
722 /* generic command status codes */
723 enum nvme_generic_command_status_code {
724 NVME_SC_SUCCESS = 0x00,
725 NVME_SC_INVALID_OPCODE = 0x01,
726 NVME_SC_INVALID_FIELD = 0x02,
727 NVME_SC_COMMAND_ID_CONFLICT = 0x03,
728 NVME_SC_DATA_TRANSFER_ERROR = 0x04,
729 NVME_SC_ABORTED_POWER_LOSS = 0x05,
730 NVME_SC_INTERNAL_DEVICE_ERROR = 0x06,
731 NVME_SC_ABORTED_BY_REQUEST = 0x07,
732 NVME_SC_ABORTED_SQ_DELETION = 0x08,
733 NVME_SC_ABORTED_FAILED_FUSED = 0x09,
734 NVME_SC_ABORTED_MISSING_FUSED = 0x0a,
735 NVME_SC_INVALID_NAMESPACE_OR_FORMAT = 0x0b,
736 NVME_SC_COMMAND_SEQUENCE_ERROR = 0x0c,
737 NVME_SC_INVALID_SGL_SEGMENT_DESCR = 0x0d,
738 NVME_SC_INVALID_NUMBER_OF_SGL_DESCR = 0x0e,
739 NVME_SC_DATA_SGL_LENGTH_INVALID = 0x0f,
740 NVME_SC_METADATA_SGL_LENGTH_INVALID = 0x10,
741 NVME_SC_SGL_DESCRIPTOR_TYPE_INVALID = 0x11,
742 NVME_SC_INVALID_USE_OF_CMB = 0x12,
743 NVME_SC_PRP_OFFET_INVALID = 0x13,
744 NVME_SC_ATOMIC_WRITE_UNIT_EXCEEDED = 0x14,
745 NVME_SC_OPERATION_DENIED = 0x15,
746 NVME_SC_SGL_OFFSET_INVALID = 0x16,
747 /* 0x17 - reserved */
748 NVME_SC_HOST_ID_INCONSISTENT_FORMAT = 0x18,
749 NVME_SC_KEEP_ALIVE_TIMEOUT_EXPIRED = 0x19,
750 NVME_SC_KEEP_ALIVE_TIMEOUT_INVALID = 0x1a,
751 NVME_SC_ABORTED_DUE_TO_PREEMPT = 0x1b,
752 NVME_SC_SANITIZE_FAILED = 0x1c,
753 NVME_SC_SANITIZE_IN_PROGRESS = 0x1d,
754 NVME_SC_SGL_DATA_BLOCK_GRAN_INVALID = 0x1e,
755 NVME_SC_NOT_SUPPORTED_IN_CMB = 0x1f,
756 NVME_SC_NAMESPACE_IS_WRITE_PROTECTED = 0x20,
757 NVME_SC_COMMAND_INTERRUPTED = 0x21,
758 NVME_SC_TRANSIENT_TRANSPORT_ERROR = 0x22,
759
760 NVME_SC_LBA_OUT_OF_RANGE = 0x80,
761 NVME_SC_CAPACITY_EXCEEDED = 0x81,
762 NVME_SC_NAMESPACE_NOT_READY = 0x82,
763 NVME_SC_RESERVATION_CONFLICT = 0x83,
764 NVME_SC_FORMAT_IN_PROGRESS = 0x84,
765 };
766
767 /* command specific status codes */
768 enum nvme_command_specific_status_code {
769 NVME_SC_COMPLETION_QUEUE_INVALID = 0x00,
770 NVME_SC_INVALID_QUEUE_IDENTIFIER = 0x01,
771 NVME_SC_MAXIMUM_QUEUE_SIZE_EXCEEDED = 0x02,
772 NVME_SC_ABORT_COMMAND_LIMIT_EXCEEDED = 0x03,
773 /* 0x04 - reserved */
774 NVME_SC_ASYNC_EVENT_REQUEST_LIMIT_EXCEEDED = 0x05,
775 NVME_SC_INVALID_FIRMWARE_SLOT = 0x06,
776 NVME_SC_INVALID_FIRMWARE_IMAGE = 0x07,
777 NVME_SC_INVALID_INTERRUPT_VECTOR = 0x08,
778 NVME_SC_INVALID_LOG_PAGE = 0x09,
779 NVME_SC_INVALID_FORMAT = 0x0a,
780 NVME_SC_FIRMWARE_REQUIRES_RESET = 0x0b,
781 NVME_SC_INVALID_QUEUE_DELETION = 0x0c,
782 NVME_SC_FEATURE_NOT_SAVEABLE = 0x0d,
783 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x0e,
784 NVME_SC_FEATURE_NOT_NS_SPECIFIC = 0x0f,
785 NVME_SC_FW_ACT_REQUIRES_NVMS_RESET = 0x10,
786 NVME_SC_FW_ACT_REQUIRES_RESET = 0x11,
787 NVME_SC_FW_ACT_REQUIRES_TIME = 0x12,
788 NVME_SC_FW_ACT_PROHIBITED = 0x13,
789 NVME_SC_OVERLAPPING_RANGE = 0x14,
790 NVME_SC_NS_INSUFFICIENT_CAPACITY = 0x15,
791 NVME_SC_NS_ID_UNAVAILABLE = 0x16,
792 /* 0x17 - reserved */
793 NVME_SC_NS_ALREADY_ATTACHED = 0x18,
794 NVME_SC_NS_IS_PRIVATE = 0x19,
795 NVME_SC_NS_NOT_ATTACHED = 0x1a,
796 NVME_SC_THIN_PROV_NOT_SUPPORTED = 0x1b,
797 NVME_SC_CTRLR_LIST_INVALID = 0x1c,
798 NVME_SC_SELF_TEST_IN_PROGRESS = 0x1d,
799 NVME_SC_BOOT_PART_WRITE_PROHIB = 0x1e,
800 NVME_SC_INVALID_CTRLR_ID = 0x1f,
801 NVME_SC_INVALID_SEC_CTRLR_STATE = 0x20,
802 NVME_SC_INVALID_NUM_OF_CTRLR_RESRC = 0x21,
803 NVME_SC_INVALID_RESOURCE_ID = 0x22,
804 NVME_SC_SANITIZE_PROHIBITED_WPMRE = 0x23,
805 NVME_SC_ANA_GROUP_ID_INVALID = 0x24,
806 NVME_SC_ANA_ATTACH_FAILED = 0x25,
807
808 NVME_SC_CONFLICTING_ATTRIBUTES = 0x80,
809 NVME_SC_INVALID_PROTECTION_INFO = 0x81,
810 NVME_SC_ATTEMPTED_WRITE_TO_RO_PAGE = 0x82,
811 };
812
813 /* media error status codes */
814 enum nvme_media_error_status_code {
815 NVME_SC_WRITE_FAULTS = 0x80,
816 NVME_SC_UNRECOVERED_READ_ERROR = 0x81,
817 NVME_SC_GUARD_CHECK_ERROR = 0x82,
818 NVME_SC_APPLICATION_TAG_CHECK_ERROR = 0x83,
819 NVME_SC_REFERENCE_TAG_CHECK_ERROR = 0x84,
820 NVME_SC_COMPARE_FAILURE = 0x85,
821 NVME_SC_ACCESS_DENIED = 0x86,
822 NVME_SC_DEALLOCATED_OR_UNWRITTEN = 0x87,
823 };
824
825 /* path related status codes */
826 enum nvme_path_related_status_code {
827 NVME_SC_INTERNAL_PATH_ERROR = 0x00,
828 NVME_SC_ASYMMETRIC_ACCESS_PERSISTENT_LOSS = 0x01,
829 NVME_SC_ASYMMETRIC_ACCESS_INACCESSIBLE = 0x02,
830 NVME_SC_ASYMMETRIC_ACCESS_TRANSITION = 0x03,
831 NVME_SC_CONTROLLER_PATHING_ERROR = 0x60,
832 NVME_SC_HOST_PATHING_ERROR = 0x70,
833 NVME_SC_COMMAND_ABORTED_BY_HOST = 0x71,
834 };
835
836 /* admin opcodes */
837 enum nvme_admin_opcode {
838 NVME_OPC_DELETE_IO_SQ = 0x00,
839 NVME_OPC_CREATE_IO_SQ = 0x01,
840 NVME_OPC_GET_LOG_PAGE = 0x02,
841 /* 0x03 - reserved */
842 NVME_OPC_DELETE_IO_CQ = 0x04,
843 NVME_OPC_CREATE_IO_CQ = 0x05,
844 NVME_OPC_IDENTIFY = 0x06,
845 /* 0x07 - reserved */
846 NVME_OPC_ABORT = 0x08,
847 NVME_OPC_SET_FEATURES = 0x09,
848 NVME_OPC_GET_FEATURES = 0x0a,
849 /* 0x0b - reserved */
850 NVME_OPC_ASYNC_EVENT_REQUEST = 0x0c,
851 NVME_OPC_NAMESPACE_MANAGEMENT = 0x0d,
852 /* 0x0e-0x0f - reserved */
853 NVME_OPC_FIRMWARE_ACTIVATE = 0x10,
854 NVME_OPC_FIRMWARE_IMAGE_DOWNLOAD = 0x11,
855 /* 0x12-0x13 - reserved */
856 NVME_OPC_DEVICE_SELF_TEST = 0x14,
857 NVME_OPC_NAMESPACE_ATTACHMENT = 0x15,
858 /* 0x16-0x17 - reserved */
859 NVME_OPC_KEEP_ALIVE = 0x18,
860 NVME_OPC_DIRECTIVE_SEND = 0x19,
861 NVME_OPC_DIRECTIVE_RECEIVE = 0x1a,
862 /* 0x1b - reserved */
863 NVME_OPC_VIRTUALIZATION_MANAGEMENT = 0x1c,
864 NVME_OPC_NVME_MI_SEND = 0x1d,
865 NVME_OPC_NVME_MI_RECEIVE = 0x1e,
866 /* 0x1f - reserved */
867 NVME_OPC_CAPACITY_MANAGEMENT = 0x20,
868 /* 0x21-0x23 - reserved */
869 NVME_OPC_LOCKDOWN = 0x24,
870 /* 0x25-0x7b - reserved */
871 NVME_OPC_DOORBELL_BUFFER_CONFIG = 0x7c,
872 /* 0x7d-0x7e - reserved */
873 NVME_OPC_FABRICS_COMMANDS = 0x7f,
874
875 NVME_OPC_FORMAT_NVM = 0x80,
876 NVME_OPC_SECURITY_SEND = 0x81,
877 NVME_OPC_SECURITY_RECEIVE = 0x82,
878 /* 0x83 - reserved */
879 NVME_OPC_SANITIZE = 0x84,
880 /* 0x85 - reserved */
881 NVME_OPC_GET_LBA_STATUS = 0x86,
882 };
883
884 /* nvme nvm opcodes */
885 enum nvme_nvm_opcode {
886 NVME_OPC_FLUSH = 0x00,
887 NVME_OPC_WRITE = 0x01,
888 NVME_OPC_READ = 0x02,
889 /* 0x03 - reserved */
890 NVME_OPC_WRITE_UNCORRECTABLE = 0x04,
891 NVME_OPC_COMPARE = 0x05,
892 /* 0x06-0x07 - reserved */
893 NVME_OPC_WRITE_ZEROES = 0x08,
894 NVME_OPC_DATASET_MANAGEMENT = 0x09,
895 /* 0x0a-0x0b - reserved */
896 NVME_OPC_VERIFY = 0x0c,
897 NVME_OPC_RESERVATION_REGISTER = 0x0d,
898 NVME_OPC_RESERVATION_REPORT = 0x0e,
899 /* 0x0f-0x10 - reserved */
900 NVME_OPC_RESERVATION_ACQUIRE = 0x11,
901 /* 0x12-0x14 - reserved */
902 NVME_OPC_RESERVATION_RELEASE = 0x15,
903 /* 0x16-0x18 - reserved */
904 NVME_OPC_COPY = 0x19,
905 };
906
907 enum nvme_feature {
908 /* 0x00 - reserved */
909 NVME_FEAT_ARBITRATION = 0x01,
910 NVME_FEAT_POWER_MANAGEMENT = 0x02,
911 NVME_FEAT_LBA_RANGE_TYPE = 0x03,
912 NVME_FEAT_TEMPERATURE_THRESHOLD = 0x04,
913 NVME_FEAT_ERROR_RECOVERY = 0x05,
914 NVME_FEAT_VOLATILE_WRITE_CACHE = 0x06,
915 NVME_FEAT_NUMBER_OF_QUEUES = 0x07,
916 NVME_FEAT_INTERRUPT_COALESCING = 0x08,
917 NVME_FEAT_INTERRUPT_VECTOR_CONFIGURATION = 0x09,
918 NVME_FEAT_WRITE_ATOMICITY = 0x0A,
919 NVME_FEAT_ASYNC_EVENT_CONFIGURATION = 0x0B,
920 NVME_FEAT_AUTONOMOUS_POWER_STATE_TRANSITION = 0x0C,
921 NVME_FEAT_HOST_MEMORY_BUFFER = 0x0D,
922 NVME_FEAT_TIMESTAMP = 0x0E,
923 NVME_FEAT_KEEP_ALIVE_TIMER = 0x0F,
924 NVME_FEAT_HOST_CONTROLLED_THERMAL_MGMT = 0x10,
925 NVME_FEAT_NON_OP_POWER_STATE_CONFIG = 0x11,
926 NVME_FEAT_READ_RECOVERY_LEVEL_CONFIG = 0x12,
927 NVME_FEAT_PREDICTABLE_LATENCY_MODE_CONFIG = 0x13,
928 NVME_FEAT_PREDICTABLE_LATENCY_MODE_WINDOW = 0x14,
929 NVME_FEAT_LBA_STATUS_INFORMATION_ATTRIBUTES = 0x15,
930 NVME_FEAT_HOST_BEHAVIOR_SUPPORT = 0x16,
931 NVME_FEAT_SANITIZE_CONFIG = 0x17,
932 NVME_FEAT_ENDURANCE_GROUP_EVENT_CONFIGURATION = 0x18,
933 /* 0x19-0x77 - reserved */
934 /* 0x78-0x7f - NVMe Management Interface */
935 NVME_FEAT_SOFTWARE_PROGRESS_MARKER = 0x80,
936 NVME_FEAT_HOST_IDENTIFIER = 0x81,
937 NVME_FEAT_RESERVATION_NOTIFICATION_MASK = 0x82,
938 NVME_FEAT_RESERVATION_PERSISTENCE = 0x83,
939 NVME_FEAT_NAMESPACE_WRITE_PROTECTION_CONFIG = 0x84,
940 /* 0x85-0xBF - command set specific (reserved) */
941 /* 0xC0-0xFF - vendor specific */
942 };
943
944 enum nvme_dsm_attribute {
945 NVME_DSM_ATTR_INTEGRAL_READ = 0x1,
946 NVME_DSM_ATTR_INTEGRAL_WRITE = 0x2,
947 NVME_DSM_ATTR_DEALLOCATE = 0x4,
948 };
949
950 enum nvme_activate_action {
951 NVME_AA_REPLACE_NO_ACTIVATE = 0x0,
952 NVME_AA_REPLACE_ACTIVATE = 0x1,
953 NVME_AA_ACTIVATE = 0x2,
954 };
955
956 struct nvme_power_state {
957 /** Maximum Power */
958 uint16_t mp; /* Maximum Power */
959 uint8_t ps_rsvd1;
960 uint8_t mps_nops; /* Max Power Scale, Non-Operational State */
961
962 uint32_t enlat; /* Entry Latency */
963 uint32_t exlat; /* Exit Latency */
964
965 uint8_t rrt; /* Relative Read Throughput */
966 uint8_t rrl; /* Relative Read Latency */
967 uint8_t rwt; /* Relative Write Throughput */
968 uint8_t rwl; /* Relative Write Latency */
969
970 uint16_t idlp; /* Idle Power */
971 uint8_t ips; /* Idle Power Scale */
972 uint8_t ps_rsvd8;
973
974 uint16_t actp; /* Active Power */
975 uint8_t apw_aps; /* Active Power Workload, Active Power Scale */
976 uint8_t ps_rsvd10[9];
977 } __packed;
978
979 _Static_assert(sizeof(struct nvme_power_state) == 32, "bad size for nvme_power_state");
980
981 #define NVME_SERIAL_NUMBER_LENGTH 20
982 #define NVME_MODEL_NUMBER_LENGTH 40
983 #define NVME_FIRMWARE_REVISION_LENGTH 8
984
985 struct nvme_controller_data {
986 /* bytes 0-255: controller capabilities and features */
987
988 /** pci vendor id */
989 uint16_t vid;
990
991 /** pci subsystem vendor id */
992 uint16_t ssvid;
993
994 /** serial number */
995 uint8_t sn[NVME_SERIAL_NUMBER_LENGTH];
996
997 /** model number */
998 uint8_t mn[NVME_MODEL_NUMBER_LENGTH];
999
1000 /** firmware revision */
1001 uint8_t fr[NVME_FIRMWARE_REVISION_LENGTH];
1002
1003 /** recommended arbitration burst */
1004 uint8_t rab;
1005
1006 /** ieee oui identifier */
1007 uint8_t ieee[3];
1008
1009 /** multi-interface capabilities */
1010 uint8_t mic;
1011
1012 /** maximum data transfer size */
1013 uint8_t mdts;
1014
1015 /** Controller ID */
1016 uint16_t ctrlr_id;
1017
1018 /** Version */
1019 uint32_t ver;
1020
1021 /** RTD3 Resume Latency */
1022 uint32_t rtd3r;
1023
1024 /** RTD3 Enter Latency */
1025 uint32_t rtd3e;
1026
1027 /** Optional Asynchronous Events Supported */
1028 uint32_t oaes; /* bitfield really */
1029
1030 /** Controller Attributes */
1031 uint32_t ctratt; /* bitfield really */
1032
1033 /** Read Recovery Levels Supported */
1034 uint16_t rrls;
1035
1036 uint8_t reserved1[9];
1037
1038 /** Controller Type */
1039 uint8_t cntrltype;
1040
1041 /** FRU Globally Unique Identifier */
1042 uint8_t fguid[16];
1043
1044 /** Command Retry Delay Time 1 */
1045 uint16_t crdt1;
1046
1047 /** Command Retry Delay Time 2 */
1048 uint16_t crdt2;
1049
1050 /** Command Retry Delay Time 3 */
1051 uint16_t crdt3;
1052
1053 uint8_t reserved2[122];
1054
1055 /* bytes 256-511: admin command set attributes */
1056
1057 /** optional admin command support */
1058 uint16_t oacs;
1059
1060 /** abort command limit */
1061 uint8_t acl;
1062
1063 /** asynchronous event request limit */
1064 uint8_t aerl;
1065
1066 /** firmware updates */
1067 uint8_t frmw;
1068
1069 /** log page attributes */
1070 uint8_t lpa;
1071
1072 /** error log page entries */
1073 uint8_t elpe;
1074
1075 /** number of power states supported */
1076 uint8_t npss;
1077
1078 /** admin vendor specific command configuration */
1079 uint8_t avscc;
1080
1081 /** Autonomous Power State Transition Attributes */
1082 uint8_t apsta;
1083
1084 /** Warning Composite Temperature Threshold */
1085 uint16_t wctemp;
1086
1087 /** Critical Composite Temperature Threshold */
1088 uint16_t cctemp;
1089
1090 /** Maximum Time for Firmware Activation */
1091 uint16_t mtfa;
1092
1093 /** Host Memory Buffer Preferred Size */
1094 uint32_t hmpre;
1095
1096 /** Host Memory Buffer Minimum Size */
1097 uint32_t hmmin;
1098
1099 /** Name space capabilities */
1100 struct {
1101 /* if nsmgmt, report tnvmcap and unvmcap */
1102 uint8_t tnvmcap[16];
1103 uint8_t unvmcap[16];
1104 } __packed untncap;
1105
1106 /** Replay Protected Memory Block Support */
1107 uint32_t rpmbs; /* Really a bitfield */
1108
1109 /** Extended Device Self-test Time */
1110 uint16_t edstt;
1111
1112 /** Device Self-test Options */
1113 uint8_t dsto; /* Really a bitfield */
1114
1115 /** Firmware Update Granularity */
1116 uint8_t fwug;
1117
1118 /** Keep Alive Support */
1119 uint16_t kas;
1120
1121 /** Host Controlled Thermal Management Attributes */
1122 uint16_t hctma; /* Really a bitfield */
1123
1124 /** Minimum Thermal Management Temperature */
1125 uint16_t mntmt;
1126
1127 /** Maximum Thermal Management Temperature */
1128 uint16_t mxtmt;
1129
1130 /** Sanitize Capabilities */
1131 uint32_t sanicap; /* Really a bitfield */
1132
1133 /** Host Memory Buffer Minimum Descriptor Entry Size */
1134 uint32_t hmminds;
1135
1136 /** Host Memory Maximum Descriptors Entries */
1137 uint16_t hmmaxd;
1138
1139 /** NVM Set Identifier Maximum */
1140 uint16_t nsetidmax;
1141
1142 /** Endurance Group Identifier Maximum */
1143 uint16_t endgidmax;
1144
1145 /** ANA Transition Time */
1146 uint8_t anatt;
1147
1148 /** Asymmetric Namespace Access Capabilities */
1149 uint8_t anacap;
1150
1151 /** ANA Group Identifier Maximum */
1152 uint32_t anagrpmax;
1153
1154 /** Number of ANA Group Identifiers */
1155 uint32_t nanagrpid;
1156
1157 /** Persistent Event Log Size */
1158 uint32_t pels;
1159
1160 uint8_t reserved3[156];
1161 /* bytes 512-703: nvm command set attributes */
1162
1163 /** submission queue entry size */
1164 uint8_t sqes;
1165
1166 /** completion queue entry size */
1167 uint8_t cqes;
1168
1169 /** Maximum Outstanding Commands */
1170 uint16_t maxcmd;
1171
1172 /** number of namespaces */
1173 uint32_t nn;
1174
1175 /** optional nvm command support */
1176 uint16_t oncs;
1177
1178 /** fused operation support */
1179 uint16_t fuses;
1180
1181 /** format nvm attributes */
1182 uint8_t fna;
1183
1184 /** volatile write cache */
1185 uint8_t vwc;
1186
1187 /** Atomic Write Unit Normal */
1188 uint16_t awun;
1189
1190 /** Atomic Write Unit Power Fail */
1191 uint16_t awupf;
1192
1193 /** NVM Vendor Specific Command Configuration */
1194 uint8_t nvscc;
1195
1196 /** Namespace Write Protection Capabilities */
1197 uint8_t nwpc;
1198
1199 /** Atomic Compare & Write Unit */
1200 uint16_t acwu;
1201 uint16_t reserved6;
1202
1203 /** SGL Support */
1204 uint32_t sgls;
1205
1206 /** Maximum Number of Allowed Namespaces */
1207 uint32_t mnan;
1208
1209 /* bytes 540-767: Reserved */
1210 uint8_t reserved7[224];
1211
1212 /** NVM Subsystem NVMe Qualified Name */
1213 uint8_t subnqn[256];
1214
1215 /* bytes 1024-1791: Reserved */
1216 uint8_t reserved8[768];
1217
1218 /* bytes 1792-2047: NVMe over Fabrics specification */
1219 uint8_t reserved9[256];
1220
1221 /* bytes 2048-3071: power state descriptors */
1222 struct nvme_power_state power_state[32];
1223
1224 /* bytes 3072-4095: vendor specific */
1225 uint8_t vs[1024];
1226 } __packed __aligned(4);
1227
1228 _Static_assert(sizeof(struct nvme_controller_data) == 4096, "bad size for nvme_controller_data");
1229
1230 struct nvme_namespace_data {
1231 /** namespace size */
1232 uint64_t nsze;
1233
1234 /** namespace capacity */
1235 uint64_t ncap;
1236
1237 /** namespace utilization */
1238 uint64_t nuse;
1239
1240 /** namespace features */
1241 uint8_t nsfeat;
1242
1243 /** number of lba formats */
1244 uint8_t nlbaf;
1245
1246 /** formatted lba size */
1247 uint8_t flbas;
1248
1249 /** metadata capabilities */
1250 uint8_t mc;
1251
1252 /** end-to-end data protection capabilities */
1253 uint8_t dpc;
1254
1255 /** end-to-end data protection type settings */
1256 uint8_t dps;
1257
1258 /** Namespace Multi-path I/O and Namespace Sharing Capabilities */
1259 uint8_t nmic;
1260
1261 /** Reservation Capabilities */
1262 uint8_t rescap;
1263
1264 /** Format Progress Indicator */
1265 uint8_t fpi;
1266
1267 /** Deallocate Logical Block Features */
1268 uint8_t dlfeat;
1269
1270 /** Namespace Atomic Write Unit Normal */
1271 uint16_t nawun;
1272
1273 /** Namespace Atomic Write Unit Power Fail */
1274 uint16_t nawupf;
1275
1276 /** Namespace Atomic Compare & Write Unit */
1277 uint16_t nacwu;
1278
1279 /** Namespace Atomic Boundary Size Normal */
1280 uint16_t nabsn;
1281
1282 /** Namespace Atomic Boundary Offset */
1283 uint16_t nabo;
1284
1285 /** Namespace Atomic Boundary Size Power Fail */
1286 uint16_t nabspf;
1287
1288 /** Namespace Optimal IO Boundary */
1289 uint16_t noiob;
1290
1291 /** NVM Capacity */
1292 uint8_t nvmcap[16];
1293
1294 /** Namespace Preferred Write Granularity */
1295 uint16_t npwg;
1296
1297 /** Namespace Preferred Write Alignment */
1298 uint16_t npwa;
1299
1300 /** Namespace Preferred Deallocate Granularity */
1301 uint16_t npdg;
1302
1303 /** Namespace Preferred Deallocate Alignment */
1304 uint16_t npda;
1305
1306 /** Namespace Optimal Write Size */
1307 uint16_t nows;
1308
1309 /* bytes 74-91: Reserved */
1310 uint8_t reserved5[18];
1311
1312 /** ANA Group Identifier */
1313 uint32_t anagrpid;
1314
1315 /* bytes 96-98: Reserved */
1316 uint8_t reserved6[3];
1317
1318 /** Namespace Attributes */
1319 uint8_t nsattr;
1320
1321 /** NVM Set Identifier */
1322 uint16_t nvmsetid;
1323
1324 /** Endurance Group Identifier */
1325 uint16_t endgid;
1326
1327 /** Namespace Globally Unique Identifier */
1328 uint8_t nguid[16];
1329
1330 /** IEEE Extended Unique Identifier */
1331 uint8_t eui64[8];
1332
1333 /** lba format support */
1334 uint32_t lbaf[16];
1335
1336 uint8_t reserved7[192];
1337
1338 uint8_t vendor_specific[3712];
1339 } __packed __aligned(4);
1340
1341 _Static_assert(sizeof(struct nvme_namespace_data) == 4096, "bad size for nvme_namepsace_data");
1342
1343 enum nvme_log_page {
1344 /* 0x00 - reserved */
1345 NVME_LOG_ERROR = 0x01,
1346 NVME_LOG_HEALTH_INFORMATION = 0x02,
1347 NVME_LOG_FIRMWARE_SLOT = 0x03,
1348 NVME_LOG_CHANGED_NAMESPACE = 0x04,
1349 NVME_LOG_COMMAND_EFFECT = 0x05,
1350 NVME_LOG_DEVICE_SELF_TEST = 0x06,
1351 NVME_LOG_TELEMETRY_HOST_INITIATED = 0x07,
1352 NVME_LOG_TELEMETRY_CONTROLLER_INITIATED = 0x08,
1353 NVME_LOG_ENDURANCE_GROUP_INFORMATION = 0x09,
1354 NVME_LOG_PREDICTABLE_LATENCY_PER_NVM_SET = 0x0a,
1355 NVME_LOG_PREDICTABLE_LATENCY_EVENT_AGGREGATE = 0x0b,
1356 NVME_LOG_ASYMMETRIC_NAMESPACE_ACCESS = 0x0c,
1357 NVME_LOG_PERSISTENT_EVENT_LOG = 0x0d,
1358 NVME_LOG_LBA_STATUS_INFORMATION = 0x0e,
1359 NVME_LOG_ENDURANCE_GROUP_EVENT_AGGREGATE = 0x0f,
1360 /* 0x06-0x7F - reserved */
1361 /* 0x80-0xBF - I/O command set specific */
1362 NVME_LOG_RES_NOTIFICATION = 0x80,
1363 NVME_LOG_SANITIZE_STATUS = 0x81,
1364 /* 0x82-0xBF - reserved */
1365 /* 0xC0-0xFF - vendor specific */
1366
1367 /*
1368 * The following are Intel Specific log pages, but they seem
1369 * to be widely implemented.
1370 */
1371 INTEL_LOG_READ_LAT_LOG = 0xc1,
1372 INTEL_LOG_WRITE_LAT_LOG = 0xc2,
1373 INTEL_LOG_TEMP_STATS = 0xc5,
1374 INTEL_LOG_ADD_SMART = 0xca,
1375 INTEL_LOG_DRIVE_MKT_NAME = 0xdd,
1376
1377 /*
1378 * HGST log page, with lots ofs sub pages.
1379 */
1380 HGST_INFO_LOG = 0xc1,
1381 };
1382
1383 struct nvme_error_information_entry {
1384 uint64_t error_count;
1385 uint16_t sqid;
1386 uint16_t cid;
1387 uint16_t status;
1388 uint16_t error_location;
1389 uint64_t lba;
1390 uint32_t nsid;
1391 uint8_t vendor_specific;
1392 uint8_t trtype;
1393 uint16_t reserved30;
1394 uint64_t csi;
1395 uint16_t ttsi;
1396 uint8_t reserved[22];
1397 } __packed __aligned(4);
1398
1399 _Static_assert(sizeof(struct nvme_error_information_entry) == 64, "bad size for nvme_error_information_entry");
1400
1401 struct nvme_health_information_page {
1402 uint8_t critical_warning;
1403 uint16_t temperature;
1404 uint8_t available_spare;
1405 uint8_t available_spare_threshold;
1406 uint8_t percentage_used;
1407
1408 uint8_t reserved[26];
1409
1410 /*
1411 * Note that the following are 128-bit values, but are
1412 * defined as an array of 2 64-bit values.
1413 */
1414 /* Data Units Read is always in 512-byte units. */
1415 uint64_t data_units_read[2];
1416 /* Data Units Written is always in 512-byte units. */
1417 uint64_t data_units_written[2];
1418 /* For NVM command set, this includes Compare commands. */
1419 uint64_t host_read_commands[2];
1420 uint64_t host_write_commands[2];
1421 /* Controller Busy Time is reported in minutes. */
1422 uint64_t controller_busy_time[2];
1423 uint64_t power_cycles[2];
1424 uint64_t power_on_hours[2];
1425 uint64_t unsafe_shutdowns[2];
1426 uint64_t media_errors[2];
1427 uint64_t num_error_info_log_entries[2];
1428 uint32_t warning_temp_time;
1429 uint32_t error_temp_time;
1430 uint16_t temp_sensor[8];
1431 /* Thermal Management Temperature 1 Transition Count */
1432 uint32_t tmt1tc;
1433 /* Thermal Management Temperature 2 Transition Count */
1434 uint32_t tmt2tc;
1435 /* Total Time For Thermal Management Temperature 1 */
1436 uint32_t ttftmt1;
1437 /* Total Time For Thermal Management Temperature 2 */
1438 uint32_t ttftmt2;
1439
1440 uint8_t reserved2[280];
1441 } __packed __aligned(4);
1442
1443 /* Currently sparse/smatch incorrectly packs this struct in some situations. */
1444 #ifndef __CHECKER__
1445 _Static_assert(sizeof(struct nvme_health_information_page) == 512, "bad size for nvme_health_information_page");
1446 #endif
1447
1448 struct nvme_firmware_page {
1449 uint8_t afi;
1450 uint8_t reserved[7];
1451 uint64_t revision[7]; /* revisions for 7 slots */
1452 uint8_t reserved2[448];
1453 } __packed __aligned(4);
1454
1455 _Static_assert(sizeof(struct nvme_firmware_page) == 512, "bad size for nvme_firmware_page");
1456
1457 struct nvme_ns_list {
1458 uint32_t ns[1024];
1459 } __packed __aligned(4);
1460
1461 _Static_assert(sizeof(struct nvme_ns_list) == 4096, "bad size for nvme_ns_list");
1462
1463 struct nvme_command_effects_page {
1464 uint32_t acs[256];
1465 uint32_t iocs[256];
1466 uint8_t reserved[2048];
1467 } __packed __aligned(4);
1468
1469 _Static_assert(sizeof(struct nvme_command_effects_page) == 4096,
1470 "bad size for nvme_command_effects_page");
1471
1472 struct nvme_device_self_test_page {
1473 uint8_t curr_operation;
1474 uint8_t curr_compl;
1475 uint8_t rsvd2[2];
1476 struct {
1477 uint8_t status;
1478 uint8_t segment_num;
1479 uint8_t valid_diag_info;
1480 uint8_t rsvd3;
1481 uint64_t poh;
1482 uint32_t nsid;
1483 /* Define as an array to simplify alignment issues */
1484 uint8_t failing_lba[8];
1485 uint8_t status_code_type;
1486 uint8_t status_code;
1487 uint8_t vendor_specific[2];
1488 } __packed result[20];
1489 } __packed __aligned(4);
1490
1491 /* Currently sparse/smatch incorrectly packs this struct in some situations. */
1492 #ifndef __CHECKER__
1493 _Static_assert(sizeof(struct nvme_device_self_test_page) == 564,
1494 "bad size for nvme_device_self_test_page");
1495 #endif
1496
1497 struct nvme_res_notification_page {
1498 uint64_t log_page_count;
1499 uint8_t log_page_type;
1500 uint8_t available_log_pages;
1501 uint8_t reserved2;
1502 uint32_t nsid;
1503 uint8_t reserved[48];
1504 } __packed __aligned(4);
1505
1506 _Static_assert(sizeof(struct nvme_res_notification_page) == 64,
1507 "bad size for nvme_res_notification_page");
1508
1509 struct nvme_sanitize_status_page {
1510 uint16_t sprog;
1511 uint16_t sstat;
1512 uint32_t scdw10;
1513 uint32_t etfo;
1514 uint32_t etfbe;
1515 uint32_t etfce;
1516 uint32_t etfownd;
1517 uint32_t etfbewnd;
1518 uint32_t etfcewnd;
1519 uint8_t reserved[480];
1520 } __packed __aligned(4);
1521
1522 _Static_assert(sizeof(struct nvme_sanitize_status_page) == 512,
1523 "bad size for nvme_sanitize_status_page");
1524
1525 struct intel_log_temp_stats {
1526 uint64_t current;
1527 uint64_t overtemp_flag_last;
1528 uint64_t overtemp_flag_life;
1529 uint64_t max_temp;
1530 uint64_t min_temp;
1531 uint64_t _rsvd[5];
1532 uint64_t max_oper_temp;
1533 uint64_t min_oper_temp;
1534 uint64_t est_offset;
1535 } __packed __aligned(4);
1536
1537 _Static_assert(sizeof(struct intel_log_temp_stats) == 13 * 8, "bad size for intel_log_temp_stats");
1538
1539 struct nvme_resv_reg_ctrlr {
1540 uint16_t ctrlr_id; /* Controller ID */
1541 uint8_t rcsts; /* Reservation Status */
1542 uint8_t reserved3[5];
1543 uint64_t hostid; /* Host Identifier */
1544 uint64_t rkey; /* Reservation Key */
1545 } __packed __aligned(4);
1546
1547 _Static_assert(sizeof(struct nvme_resv_reg_ctrlr) == 24, "bad size for nvme_resv_reg_ctrlr");
1548
1549 struct nvme_resv_reg_ctrlr_ext {
1550 uint16_t ctrlr_id; /* Controller ID */
1551 uint8_t rcsts; /* Reservation Status */
1552 uint8_t reserved3[5];
1553 uint64_t rkey; /* Reservation Key */
1554 uint64_t hostid[2]; /* Host Identifier */
1555 uint8_t reserved32[32];
1556 } __packed __aligned(4);
1557
1558 _Static_assert(sizeof(struct nvme_resv_reg_ctrlr_ext) == 64, "bad size for nvme_resv_reg_ctrlr_ext");
1559
1560 struct nvme_resv_status {
1561 uint32_t gen; /* Generation */
1562 uint8_t rtype; /* Reservation Type */
1563 uint8_t regctl[2]; /* Number of Registered Controllers */
1564 uint8_t reserved7[2];
1565 uint8_t ptpls; /* Persist Through Power Loss State */
1566 uint8_t reserved10[14];
1567 struct nvme_resv_reg_ctrlr ctrlr[0];
1568 } __packed __aligned(4);
1569
1570 _Static_assert(sizeof(struct nvme_resv_status) == 24, "bad size for nvme_resv_status");
1571
1572 struct nvme_resv_status_ext {
1573 uint32_t gen; /* Generation */
1574 uint8_t rtype; /* Reservation Type */
1575 uint8_t regctl[2]; /* Number of Registered Controllers */
1576 uint8_t reserved7[2];
1577 uint8_t ptpls; /* Persist Through Power Loss State */
1578 uint8_t reserved10[14];
1579 uint8_t reserved24[40];
1580 struct nvme_resv_reg_ctrlr_ext ctrlr[0];
1581 } __packed __aligned(4);
1582
1583 _Static_assert(sizeof(struct nvme_resv_status_ext) == 64, "bad size for nvme_resv_status_ext");
1584
1585 #define NVME_TEST_MAX_THREADS 128
1586
1587 struct nvme_io_test {
1588 enum nvme_nvm_opcode opc;
1589 uint32_t size;
1590 uint32_t time; /* in seconds */
1591 uint32_t num_threads;
1592 uint32_t flags;
1593 uint64_t io_completed[NVME_TEST_MAX_THREADS];
1594 };
1595
1596 enum nvme_io_test_flags {
1597 /*
1598 * Specifies whether dev_refthread/dev_relthread should be
1599 * called during NVME_BIO_TEST. Ignored for other test
1600 * types.
1601 */
1602 NVME_TEST_FLAG_REFTHREAD = 0x1,
1603 };
1604
1605 struct nvme_pt_command {
1606 /*
1607 * cmd is used to specify a passthrough command to a controller or
1608 * namespace.
1609 *
1610 * The following fields from cmd may be specified by the caller:
1611 * * opc (opcode)
1612 * * nsid (namespace id) - for admin commands only
1613 * * cdw10-cdw15
1614 *
1615 * Remaining fields must be set to 0 by the caller.
1616 */
1617 struct nvme_command cmd;
1618
1619 /*
1620 * cpl returns completion status for the passthrough command
1621 * specified by cmd.
1622 *
1623 * The following fields will be filled out by the driver, for
1624 * consumption by the caller:
1625 * * cdw0
1626 * * status (except for phase)
1627 *
1628 * Remaining fields will be set to 0 by the driver.
1629 */
1630 struct nvme_completion cpl;
1631
1632 /* buf is the data buffer associated with this passthrough command. */
1633 void * buf;
1634
1635 /*
1636 * len is the length of the data buffer associated with this
1637 * passthrough command.
1638 */
1639 uint32_t len;
1640
1641 /*
1642 * is_read = 1 if the passthrough command will read data into the
1643 * supplied buffer from the controller.
1644 *
1645 * is_read = 0 if the passthrough command will write data from the
1646 * supplied buffer to the controller.
1647 */
1648 uint32_t is_read;
1649
1650 /*
1651 * driver_lock is used by the driver only. It must be set to 0
1652 * by the caller.
1653 */
1654 struct mtx * driver_lock;
1655 };
1656
1657 struct nvme_get_nsid {
1658 char cdev[SPECNAMELEN + 1];
1659 uint32_t nsid;
1660 };
1661
1662 struct nvme_hmb_desc {
1663 uint64_t addr;
1664 uint32_t size;
1665 uint32_t reserved;
1666 };
1667
1668 #define nvme_completion_is_error(cpl) \
1669 (NVME_STATUS_GET_SC((cpl)->status) != 0 || NVME_STATUS_GET_SCT((cpl)->status) != 0)
1670
1671 void nvme_strvis(uint8_t *dst, const uint8_t *src, int dstlen, int srclen);
1672
1673 #ifdef _KERNEL
1674
1675 struct bio;
1676 struct thread;
1677
1678 struct nvme_namespace;
1679 struct nvme_controller;
1680 struct nvme_consumer;
1681
1682 typedef void (*nvme_cb_fn_t)(void *, const struct nvme_completion *);
1683
1684 typedef void *(*nvme_cons_ns_fn_t)(struct nvme_namespace *, void *);
1685 typedef void *(*nvme_cons_ctrlr_fn_t)(struct nvme_controller *);
1686 typedef void (*nvme_cons_async_fn_t)(void *, const struct nvme_completion *,
1687 uint32_t, void *, uint32_t);
1688 typedef void (*nvme_cons_fail_fn_t)(void *);
1689
1690 enum nvme_namespace_flags {
1691 NVME_NS_DEALLOCATE_SUPPORTED = 0x1,
1692 NVME_NS_FLUSH_SUPPORTED = 0x2,
1693 };
1694
1695 int nvme_ctrlr_passthrough_cmd(struct nvme_controller *ctrlr,
1696 struct nvme_pt_command *pt,
1697 uint32_t nsid, int is_user_buffer,
1698 int is_admin_cmd);
1699
1700 /* Admin functions */
1701 void nvme_ctrlr_cmd_set_feature(struct nvme_controller *ctrlr,
1702 uint8_t feature, uint32_t cdw11,
1703 uint32_t cdw12, uint32_t cdw13,
1704 uint32_t cdw14, uint32_t cdw15,
1705 void *payload, uint32_t payload_size,
1706 nvme_cb_fn_t cb_fn, void *cb_arg);
1707 void nvme_ctrlr_cmd_get_feature(struct nvme_controller *ctrlr,
1708 uint8_t feature, uint32_t cdw11,
1709 void *payload, uint32_t payload_size,
1710 nvme_cb_fn_t cb_fn, void *cb_arg);
1711 void nvme_ctrlr_cmd_get_log_page(struct nvme_controller *ctrlr,
1712 uint8_t log_page, uint32_t nsid,
1713 void *payload, uint32_t payload_size,
1714 nvme_cb_fn_t cb_fn, void *cb_arg);
1715
1716 /* NVM I/O functions */
1717 int nvme_ns_cmd_write(struct nvme_namespace *ns, void *payload,
1718 uint64_t lba, uint32_t lba_count, nvme_cb_fn_t cb_fn,
1719 void *cb_arg);
1720 int nvme_ns_cmd_write_bio(struct nvme_namespace *ns, struct bio *bp,
1721 nvme_cb_fn_t cb_fn, void *cb_arg);
1722 int nvme_ns_cmd_read(struct nvme_namespace *ns, void *payload,
1723 uint64_t lba, uint32_t lba_count, nvme_cb_fn_t cb_fn,
1724 void *cb_arg);
1725 int nvme_ns_cmd_read_bio(struct nvme_namespace *ns, struct bio *bp,
1726 nvme_cb_fn_t cb_fn, void *cb_arg);
1727 int nvme_ns_cmd_deallocate(struct nvme_namespace *ns, void *payload,
1728 uint8_t num_ranges, nvme_cb_fn_t cb_fn,
1729 void *cb_arg);
1730 int nvme_ns_cmd_flush(struct nvme_namespace *ns, nvme_cb_fn_t cb_fn,
1731 void *cb_arg);
1732 int nvme_ns_dump(struct nvme_namespace *ns, void *virt, off_t offset,
1733 size_t len);
1734
1735 /* Registration functions */
1736 struct nvme_consumer * nvme_register_consumer(nvme_cons_ns_fn_t ns_fn,
1737 nvme_cons_ctrlr_fn_t ctrlr_fn,
1738 nvme_cons_async_fn_t async_fn,
1739 nvme_cons_fail_fn_t fail_fn);
1740 void nvme_unregister_consumer(struct nvme_consumer *consumer);
1741
1742 /* Controller helper functions */
1743 device_t nvme_ctrlr_get_device(struct nvme_controller *ctrlr);
1744 const struct nvme_controller_data *
1745 nvme_ctrlr_get_data(struct nvme_controller *ctrlr);
1746 static inline bool
nvme_ctrlr_has_dataset_mgmt(const struct nvme_controller_data * cd)1747 nvme_ctrlr_has_dataset_mgmt(const struct nvme_controller_data *cd)
1748 {
1749 /* Assumes cd was byte swapped by nvme_controller_data_swapbytes() */
1750 return ((cd->oncs >> NVME_CTRLR_DATA_ONCS_DSM_SHIFT) &
1751 NVME_CTRLR_DATA_ONCS_DSM_MASK);
1752 }
1753
1754 /* Namespace helper functions */
1755 uint32_t nvme_ns_get_max_io_xfer_size(struct nvme_namespace *ns);
1756 uint32_t nvme_ns_get_sector_size(struct nvme_namespace *ns);
1757 uint64_t nvme_ns_get_num_sectors(struct nvme_namespace *ns);
1758 uint64_t nvme_ns_get_size(struct nvme_namespace *ns);
1759 uint32_t nvme_ns_get_flags(struct nvme_namespace *ns);
1760 const char * nvme_ns_get_serial_number(struct nvme_namespace *ns);
1761 const char * nvme_ns_get_model_number(struct nvme_namespace *ns);
1762 const struct nvme_namespace_data *
1763 nvme_ns_get_data(struct nvme_namespace *ns);
1764 uint32_t nvme_ns_get_stripesize(struct nvme_namespace *ns);
1765
1766 int nvme_ns_bio_process(struct nvme_namespace *ns, struct bio *bp,
1767 nvme_cb_fn_t cb_fn);
1768 int nvme_ns_ioctl_process(struct nvme_namespace *ns, u_long cmd,
1769 caddr_t arg, int flag, struct thread *td);
1770
1771 /*
1772 * Command building helper functions -- shared with CAM
1773 * These functions assume allocator zeros out cmd structure
1774 * CAM's xpt_get_ccb and the request allocator for nvme both
1775 * do zero'd allocations.
1776 */
1777 static inline
nvme_ns_flush_cmd(struct nvme_command * cmd,uint32_t nsid)1778 void nvme_ns_flush_cmd(struct nvme_command *cmd, uint32_t nsid)
1779 {
1780
1781 cmd->opc = NVME_OPC_FLUSH;
1782 cmd->nsid = htole32(nsid);
1783 }
1784
1785 static inline
nvme_ns_rw_cmd(struct nvme_command * cmd,uint32_t rwcmd,uint32_t nsid,uint64_t lba,uint32_t count)1786 void nvme_ns_rw_cmd(struct nvme_command *cmd, uint32_t rwcmd, uint32_t nsid,
1787 uint64_t lba, uint32_t count)
1788 {
1789 cmd->opc = rwcmd;
1790 cmd->nsid = htole32(nsid);
1791 cmd->cdw10 = htole32(lba & 0xffffffffu);
1792 cmd->cdw11 = htole32(lba >> 32);
1793 cmd->cdw12 = htole32(count-1);
1794 }
1795
1796 static inline
nvme_ns_write_cmd(struct nvme_command * cmd,uint32_t nsid,uint64_t lba,uint32_t count)1797 void nvme_ns_write_cmd(struct nvme_command *cmd, uint32_t nsid,
1798 uint64_t lba, uint32_t count)
1799 {
1800 nvme_ns_rw_cmd(cmd, NVME_OPC_WRITE, nsid, lba, count);
1801 }
1802
1803 static inline
nvme_ns_read_cmd(struct nvme_command * cmd,uint32_t nsid,uint64_t lba,uint32_t count)1804 void nvme_ns_read_cmd(struct nvme_command *cmd, uint32_t nsid,
1805 uint64_t lba, uint32_t count)
1806 {
1807 nvme_ns_rw_cmd(cmd, NVME_OPC_READ, nsid, lba, count);
1808 }
1809
1810 static inline
nvme_ns_trim_cmd(struct nvme_command * cmd,uint32_t nsid,uint32_t num_ranges)1811 void nvme_ns_trim_cmd(struct nvme_command *cmd, uint32_t nsid,
1812 uint32_t num_ranges)
1813 {
1814 cmd->opc = NVME_OPC_DATASET_MANAGEMENT;
1815 cmd->nsid = htole32(nsid);
1816 cmd->cdw10 = htole32(num_ranges - 1);
1817 cmd->cdw11 = htole32(NVME_DSM_ATTR_DEALLOCATE);
1818 }
1819
1820 extern int nvme_use_nvd;
1821
1822 #endif /* _KERNEL */
1823
1824 /* Endianess conversion functions for NVMe structs */
1825 static inline
nvme_completion_swapbytes(struct nvme_completion * s __unused)1826 void nvme_completion_swapbytes(struct nvme_completion *s __unused)
1827 {
1828 #ifndef _LITTLE_ENDIAN
1829
1830 s->cdw0 = le32toh(s->cdw0);
1831 /* omit rsvd1 */
1832 s->sqhd = le16toh(s->sqhd);
1833 s->sqid = le16toh(s->sqid);
1834 /* omit cid */
1835 s->status = le16toh(s->status);
1836 #endif
1837 }
1838
1839 static inline
nvme_power_state_swapbytes(struct nvme_power_state * s __unused)1840 void nvme_power_state_swapbytes(struct nvme_power_state *s __unused)
1841 {
1842 #ifndef _LITTLE_ENDIAN
1843
1844 s->mp = le16toh(s->mp);
1845 s->enlat = le32toh(s->enlat);
1846 s->exlat = le32toh(s->exlat);
1847 s->idlp = le16toh(s->idlp);
1848 s->actp = le16toh(s->actp);
1849 #endif
1850 }
1851
1852 static inline
nvme_controller_data_swapbytes(struct nvme_controller_data * s __unused)1853 void nvme_controller_data_swapbytes(struct nvme_controller_data *s __unused)
1854 {
1855 #ifndef _LITTLE_ENDIAN
1856 int i;
1857
1858 s->vid = le16toh(s->vid);
1859 s->ssvid = le16toh(s->ssvid);
1860 s->ctrlr_id = le16toh(s->ctrlr_id);
1861 s->ver = le32toh(s->ver);
1862 s->rtd3r = le32toh(s->rtd3r);
1863 s->rtd3e = le32toh(s->rtd3e);
1864 s->oaes = le32toh(s->oaes);
1865 s->ctratt = le32toh(s->ctratt);
1866 s->rrls = le16toh(s->rrls);
1867 s->crdt1 = le16toh(s->crdt1);
1868 s->crdt2 = le16toh(s->crdt2);
1869 s->crdt3 = le16toh(s->crdt3);
1870 s->oacs = le16toh(s->oacs);
1871 s->wctemp = le16toh(s->wctemp);
1872 s->cctemp = le16toh(s->cctemp);
1873 s->mtfa = le16toh(s->mtfa);
1874 s->hmpre = le32toh(s->hmpre);
1875 s->hmmin = le32toh(s->hmmin);
1876 s->rpmbs = le32toh(s->rpmbs);
1877 s->edstt = le16toh(s->edstt);
1878 s->kas = le16toh(s->kas);
1879 s->hctma = le16toh(s->hctma);
1880 s->mntmt = le16toh(s->mntmt);
1881 s->mxtmt = le16toh(s->mxtmt);
1882 s->sanicap = le32toh(s->sanicap);
1883 s->hmminds = le32toh(s->hmminds);
1884 s->hmmaxd = le16toh(s->hmmaxd);
1885 s->nsetidmax = le16toh(s->nsetidmax);
1886 s->endgidmax = le16toh(s->endgidmax);
1887 s->anagrpmax = le32toh(s->anagrpmax);
1888 s->nanagrpid = le32toh(s->nanagrpid);
1889 s->pels = le32toh(s->pels);
1890 s->maxcmd = le16toh(s->maxcmd);
1891 s->nn = le32toh(s->nn);
1892 s->oncs = le16toh(s->oncs);
1893 s->fuses = le16toh(s->fuses);
1894 s->awun = le16toh(s->awun);
1895 s->awupf = le16toh(s->awupf);
1896 s->acwu = le16toh(s->acwu);
1897 s->sgls = le32toh(s->sgls);
1898 s->mnan = le32toh(s->mnan);
1899 for (i = 0; i < 32; i++)
1900 nvme_power_state_swapbytes(&s->power_state[i]);
1901 #endif
1902 }
1903
1904 static inline
nvme_namespace_data_swapbytes(struct nvme_namespace_data * s __unused)1905 void nvme_namespace_data_swapbytes(struct nvme_namespace_data *s __unused)
1906 {
1907 #ifndef _LITTLE_ENDIAN
1908 int i;
1909
1910 s->nsze = le64toh(s->nsze);
1911 s->ncap = le64toh(s->ncap);
1912 s->nuse = le64toh(s->nuse);
1913 s->nawun = le16toh(s->nawun);
1914 s->nawupf = le16toh(s->nawupf);
1915 s->nacwu = le16toh(s->nacwu);
1916 s->nabsn = le16toh(s->nabsn);
1917 s->nabo = le16toh(s->nabo);
1918 s->nabspf = le16toh(s->nabspf);
1919 s->noiob = le16toh(s->noiob);
1920 s->npwg = le16toh(s->npwg);
1921 s->npwa = le16toh(s->npwa);
1922 s->npdg = le16toh(s->npdg);
1923 s->npda = le16toh(s->npda);
1924 s->nows = le16toh(s->nows);
1925 s->anagrpid = le32toh(s->anagrpid);
1926 s->nvmsetid = le16toh(s->nvmsetid);
1927 s->endgid = le16toh(s->endgid);
1928 for (i = 0; i < 16; i++)
1929 s->lbaf[i] = le32toh(s->lbaf[i]);
1930 #endif
1931 }
1932
1933 static inline
nvme_error_information_entry_swapbytes(struct nvme_error_information_entry * s __unused)1934 void nvme_error_information_entry_swapbytes(
1935 struct nvme_error_information_entry *s __unused)
1936 {
1937 #ifndef _LITTLE_ENDIAN
1938
1939 s->error_count = le64toh(s->error_count);
1940 s->sqid = le16toh(s->sqid);
1941 s->cid = le16toh(s->cid);
1942 s->status = le16toh(s->status);
1943 s->error_location = le16toh(s->error_location);
1944 s->lba = le64toh(s->lba);
1945 s->nsid = le32toh(s->nsid);
1946 s->csi = le64toh(s->csi);
1947 s->ttsi = le16toh(s->ttsi);
1948 #endif
1949 }
1950
1951 static inline
nvme_le128toh(void * p __unused)1952 void nvme_le128toh(void *p __unused)
1953 {
1954 #ifndef _LITTLE_ENDIAN
1955 /* Swap 16 bytes in place */
1956 char *tmp = (char*)p;
1957 char b;
1958 int i;
1959 for (i = 0; i < 8; i++) {
1960 b = tmp[i];
1961 tmp[i] = tmp[15-i];
1962 tmp[15-i] = b;
1963 }
1964 #endif
1965 }
1966
1967 static inline
nvme_health_information_page_swapbytes(struct nvme_health_information_page * s __unused)1968 void nvme_health_information_page_swapbytes(
1969 struct nvme_health_information_page *s __unused)
1970 {
1971 #ifndef _LITTLE_ENDIAN
1972 int i;
1973
1974 s->temperature = le16toh(s->temperature);
1975 nvme_le128toh((void *)s->data_units_read);
1976 nvme_le128toh((void *)s->data_units_written);
1977 nvme_le128toh((void *)s->host_read_commands);
1978 nvme_le128toh((void *)s->host_write_commands);
1979 nvme_le128toh((void *)s->controller_busy_time);
1980 nvme_le128toh((void *)s->power_cycles);
1981 nvme_le128toh((void *)s->power_on_hours);
1982 nvme_le128toh((void *)s->unsafe_shutdowns);
1983 nvme_le128toh((void *)s->media_errors);
1984 nvme_le128toh((void *)s->num_error_info_log_entries);
1985 s->warning_temp_time = le32toh(s->warning_temp_time);
1986 s->error_temp_time = le32toh(s->error_temp_time);
1987 for (i = 0; i < 8; i++)
1988 s->temp_sensor[i] = le16toh(s->temp_sensor[i]);
1989 s->tmt1tc = le32toh(s->tmt1tc);
1990 s->tmt2tc = le32toh(s->tmt2tc);
1991 s->ttftmt1 = le32toh(s->ttftmt1);
1992 s->ttftmt2 = le32toh(s->ttftmt2);
1993 #endif
1994 }
1995
1996 static inline
nvme_firmware_page_swapbytes(struct nvme_firmware_page * s __unused)1997 void nvme_firmware_page_swapbytes(struct nvme_firmware_page *s __unused)
1998 {
1999 #ifndef _LITTLE_ENDIAN
2000 int i;
2001
2002 for (i = 0; i < 7; i++)
2003 s->revision[i] = le64toh(s->revision[i]);
2004 #endif
2005 }
2006
2007 static inline
nvme_ns_list_swapbytes(struct nvme_ns_list * s __unused)2008 void nvme_ns_list_swapbytes(struct nvme_ns_list *s __unused)
2009 {
2010 #ifndef _LITTLE_ENDIAN
2011 int i;
2012
2013 for (i = 0; i < 1024; i++)
2014 s->ns[i] = le32toh(s->ns[i]);
2015 #endif
2016 }
2017
2018 static inline
nvme_command_effects_page_swapbytes(struct nvme_command_effects_page * s __unused)2019 void nvme_command_effects_page_swapbytes(
2020 struct nvme_command_effects_page *s __unused)
2021 {
2022 #ifndef _LITTLE_ENDIAN
2023 int i;
2024
2025 for (i = 0; i < 256; i++)
2026 s->acs[i] = le32toh(s->acs[i]);
2027 for (i = 0; i < 256; i++)
2028 s->iocs[i] = le32toh(s->iocs[i]);
2029 #endif
2030 }
2031
2032 static inline
nvme_res_notification_page_swapbytes(struct nvme_res_notification_page * s __unused)2033 void nvme_res_notification_page_swapbytes(
2034 struct nvme_res_notification_page *s __unused)
2035 {
2036 #ifndef _LITTLE_ENDIAN
2037 s->log_page_count = le64toh(s->log_page_count);
2038 s->nsid = le32toh(s->nsid);
2039 #endif
2040 }
2041
2042 static inline
nvme_sanitize_status_page_swapbytes(struct nvme_sanitize_status_page * s __unused)2043 void nvme_sanitize_status_page_swapbytes(
2044 struct nvme_sanitize_status_page *s __unused)
2045 {
2046 #ifndef _LITTLE_ENDIAN
2047 s->sprog = le16toh(s->sprog);
2048 s->sstat = le16toh(s->sstat);
2049 s->scdw10 = le32toh(s->scdw10);
2050 s->etfo = le32toh(s->etfo);
2051 s->etfbe = le32toh(s->etfbe);
2052 s->etfce = le32toh(s->etfce);
2053 s->etfownd = le32toh(s->etfownd);
2054 s->etfbewnd = le32toh(s->etfbewnd);
2055 s->etfcewnd = le32toh(s->etfcewnd);
2056 #endif
2057 }
2058
2059 static inline
intel_log_temp_stats_swapbytes(struct intel_log_temp_stats * s __unused)2060 void intel_log_temp_stats_swapbytes(struct intel_log_temp_stats *s __unused)
2061 {
2062 #ifndef _LITTLE_ENDIAN
2063
2064 s->current = le64toh(s->current);
2065 s->overtemp_flag_last = le64toh(s->overtemp_flag_last);
2066 s->overtemp_flag_life = le64toh(s->overtemp_flag_life);
2067 s->max_temp = le64toh(s->max_temp);
2068 s->min_temp = le64toh(s->min_temp);
2069 /* omit _rsvd[] */
2070 s->max_oper_temp = le64toh(s->max_oper_temp);
2071 s->min_oper_temp = le64toh(s->min_oper_temp);
2072 s->est_offset = le64toh(s->est_offset);
2073 #endif
2074 }
2075
2076 static inline
nvme_resv_status_swapbytes(struct nvme_resv_status * s __unused,size_t size __unused)2077 void nvme_resv_status_swapbytes(struct nvme_resv_status *s __unused,
2078 size_t size __unused)
2079 {
2080 #ifndef _LITTLE_ENDIAN
2081 size_t i, n;
2082
2083 s->gen = le32toh(s->gen);
2084 n = (s->regctl[1] << 8) | s->regctl[0];
2085 n = MIN(n, (size - sizeof(s)) / sizeof(s->ctrlr[0]));
2086 for (i = 0; i < n; i++) {
2087 s->ctrlr[i].ctrlr_id = le16toh(s->ctrlr[i].ctrlr_id);
2088 s->ctrlr[i].hostid = le64toh(s->ctrlr[i].hostid);
2089 s->ctrlr[i].rkey = le64toh(s->ctrlr[i].rkey);
2090 }
2091 #endif
2092 }
2093
2094 static inline
nvme_resv_status_ext_swapbytes(struct nvme_resv_status_ext * s __unused,size_t size __unused)2095 void nvme_resv_status_ext_swapbytes(struct nvme_resv_status_ext *s __unused,
2096 size_t size __unused)
2097 {
2098 #ifndef _LITTLE_ENDIAN
2099 size_t i, n;
2100
2101 s->gen = le32toh(s->gen);
2102 n = (s->regctl[1] << 8) | s->regctl[0];
2103 n = MIN(n, (size - sizeof(s)) / sizeof(s->ctrlr[0]));
2104 for (i = 0; i < n; i++) {
2105 s->ctrlr[i].ctrlr_id = le16toh(s->ctrlr[i].ctrlr_id);
2106 s->ctrlr[i].rkey = le64toh(s->ctrlr[i].rkey);
2107 nvme_le128toh((void *)s->ctrlr[i].hostid);
2108 }
2109 #endif
2110 }
2111
2112 static inline void
nvme_device_self_test_swapbytes(struct nvme_device_self_test_page * s __unused)2113 nvme_device_self_test_swapbytes(struct nvme_device_self_test_page *s __unused)
2114 {
2115 #ifndef _LITTLE_ENDIAN
2116 uint8_t *tmp;
2117 uint32_t r, i;
2118 uint8_t b;
2119
2120 for (r = 0; r < 20; r++) {
2121 s->result[r].poh = le64toh(s->result[r].poh);
2122 s->result[r].nsid = le32toh(s->result[r].nsid);
2123 /* Unaligned 64-bit loads fail on some architectures */
2124 tmp = s->result[r].failing_lba;
2125 for (i = 0; i < 4; i++) {
2126 b = tmp[i];
2127 tmp[i] = tmp[7-i];
2128 tmp[7-i] = b;
2129 }
2130 }
2131 #endif
2132 }
2133 #endif /* __NVME_H__ */
2134