1 #ifndef UAE_PCI_HW_H 2 #define UAE_PCI_HW_H 3 4 #include "uae/types.h" 5 #ifdef FSUAE 6 #include "uae/memory.h" 7 #endif 8 9 #define MAX_PCI_BOARDS 6 10 #define MAX_PCI_BARS 7 11 12 typedef uae_u32(REGPARAM3 *pci_get_func)(struct pci_board_state*,uaecptr) REGPARAM; 13 typedef void (REGPARAM3 *pci_put_func)(struct pci_board_state*,uaecptr,uae_u32) REGPARAM; 14 typedef void (*pci_dev_irq)(struct pci_board_state*,bool); 15 typedef bool(*pci_dev_init)(struct pci_board_state*); 16 typedef void(*pci_dev_reset)(struct pci_board_state*); 17 typedef void(*pci_dev_hsync)(struct pci_board_state*); 18 typedef void(*pci_dev_free)(struct pci_board_state*); 19 20 typedef struct 21 { 22 pci_get_func lget, wget, bget; 23 pci_put_func lput, wput, bput; 24 } pci_addrbank; 25 26 typedef int(*pci_slot_index)(uaecptr); 27 28 struct pci_config 29 { 30 uae_u16 vendor; 31 uae_u16 device; 32 uae_u16 command; 33 uae_u16 status; 34 uae_u8 revision; 35 uae_u32 deviceclass; 36 uae_u8 header; 37 uae_u16 subsystenvendor; 38 uae_u16 subsystem; 39 uae_u8 interruptpin; 40 uae_u8 min_grant; 41 uae_u8 max_latency; 42 uae_u32 bars[MAX_PCI_BARS]; 43 }; 44 45 struct pci_board 46 { 47 const TCHAR *label; 48 const struct pci_config *config; 49 pci_dev_init init; 50 pci_dev_free free; 51 pci_dev_reset reset; 52 pci_dev_hsync hsync; 53 pci_dev_irq irq; 54 pci_addrbank bars[MAX_PCI_BARS]; 55 }; 56 57 struct pci_board_state 58 { 59 uae_u8 config_data[256 + 3]; 60 uaecptr bar[MAX_PCI_BARS]; 61 uaecptr bar_old[MAX_PCI_BARS]; 62 bool bar_enabled[MAX_PCI_BARS]; 63 uaecptr bar_start[MAX_PCI_BARS]; 64 uaecptr bar_end[MAX_PCI_BARS]; 65 uae_u32 bar_size[MAX_PCI_BARS]; 66 int selected_bar; 67 const struct pci_board *board; 68 int slot; 69 int func; 70 bool memory_map_active; 71 bool io_map_active; 72 struct pci_bridge *bridge; 73 }; 74 75 struct pci_bridge 76 { 77 const TCHAR *label; 78 int type; 79 int endian_swap_config; 80 uae_u32 io_offset; 81 int endian_swap_io; 82 uae_u32 memory_offset; 83 int endian_swap_memory; 84 bool pcipcidma; 85 bool amigapicdma; 86 uae_u8 intena; 87 uae_u8 irq; 88 uae_u16 intreq_mask; 89 pci_slot_index get_index; 90 struct pci_board_state boards[MAX_PCI_BOARDS]; 91 uae_u8 config[16]; 92 uae_u8 *data; 93 int configured; 94 int configured_2; 95 int bank_zorro; 96 int bank_2_zorro; 97 addrbank *bank; 98 addrbank *bank_2; 99 int board_size; 100 int board_size_2; 101 uaecptr baseaddress; 102 uaecptr baseaddress_end; 103 uaecptr baseaddress_offset; 104 uaecptr baseaddress_2; 105 uaecptr baseaddress_end_2; 106 uaecptr baseaddress_offset_2; 107 uae_u8 acmemory[128]; 108 uae_u8 acmemory_2[128]; 109 struct romconfig *rc; 110 uae_u16 window; 111 int slot_cnt; 112 }; 113 114 extern void pci_free(void); 115 extern void pci_reset(void); 116 extern void pci_rethink(void); 117 118 extern addrbank *dkb_wildfire_pci_init(struct romconfig *rc); 119 120 extern void pci_irq_callback(struct pci_board_state *pcibs, bool irq); 121 extern void pci_write_dma(struct pci_board_state *pcibs, uaecptr addr, uae_u8*, int size); 122 extern void pci_read_dma(struct pci_board_state *pcibs, uaecptr addr, uae_u8*, int size); 123 124 extern const struct pci_board ne2000_pci_board; 125 extern const struct pci_board es1370_pci_board; 126 extern const struct pci_board fm801_pci_board; 127 extern const struct pci_board fm801_pci_board_func1; 128 extern const struct pci_board solo1_pci_board; 129 130 #endif /* UAE_PCI_HW_H */ 131