1 //===-- ARMBaseInstrInfo.h - ARM Base Instruction Information ---*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Base ARM implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
14 #define LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
15 
16 #include "MCTargetDesc/ARMBaseInfo.h"
17 #include "llvm/ADT/DenseMap.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/MachineInstr.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineOperand.h"
23 #include "llvm/CodeGen/TargetInstrInfo.h"
24 #include "llvm/IR/IntrinsicInst.h"
25 #include "llvm/IR/IntrinsicsARM.h"
26 #include <array>
27 #include <cstdint>
28 
29 #define GET_INSTRINFO_HEADER
30 #include "ARMGenInstrInfo.inc"
31 
32 namespace llvm {
33 
34 class ARMBaseRegisterInfo;
35 class ARMSubtarget;
36 
37 class ARMBaseInstrInfo : public ARMGenInstrInfo {
38   const ARMSubtarget &Subtarget;
39 
40 protected:
41   // Can be only subclassed.
42   explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
43 
44   void expandLoadStackGuardBase(MachineBasicBlock::iterator MI,
45                                 unsigned LoadImmOpc, unsigned LoadOpc) const;
46 
47   /// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI
48   /// and \p DefIdx.
49   /// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of
50   /// the list is modeled as <Reg:SubReg, SubIdx>.
51   /// E.g., REG_SEQUENCE %1:sub1, sub0, %2, sub1 would produce
52   /// two elements:
53   /// - %1:sub1, sub0
54   /// - %2<:0>, sub1
55   ///
56   /// \returns true if it is possible to build such an input sequence
57   /// with the pair \p MI, \p DefIdx. False otherwise.
58   ///
59   /// \pre MI.isRegSequenceLike().
60   bool getRegSequenceLikeInputs(
61       const MachineInstr &MI, unsigned DefIdx,
62       SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const override;
63 
64   /// Build the equivalent inputs of a EXTRACT_SUBREG for the given \p MI
65   /// and \p DefIdx.
66   /// \p [out] InputReg of the equivalent EXTRACT_SUBREG.
67   /// E.g., EXTRACT_SUBREG %1:sub1, sub0, sub1 would produce:
68   /// - %1:sub1, sub0
69   ///
70   /// \returns true if it is possible to build such an input sequence
71   /// with the pair \p MI, \p DefIdx. False otherwise.
72   ///
73   /// \pre MI.isExtractSubregLike().
74   bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
75                                   RegSubRegPairAndIdx &InputReg) const override;
76 
77   /// Build the equivalent inputs of a INSERT_SUBREG for the given \p MI
78   /// and \p DefIdx.
79   /// \p [out] BaseReg and \p [out] InsertedReg contain
80   /// the equivalent inputs of INSERT_SUBREG.
81   /// E.g., INSERT_SUBREG %0:sub0, %1:sub1, sub3 would produce:
82   /// - BaseReg: %0:sub0
83   /// - InsertedReg: %1:sub1, sub3
84   ///
85   /// \returns true if it is possible to build such an input sequence
86   /// with the pair \p MI, \p DefIdx. False otherwise.
87   ///
88   /// \pre MI.isInsertSubregLike().
89   bool
90   getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
91                             RegSubRegPair &BaseReg,
92                             RegSubRegPairAndIdx &InsertedReg) const override;
93 
94   /// Commutes the operands in the given instruction.
95   /// The commutable operands are specified by their indices OpIdx1 and OpIdx2.
96   ///
97   /// Do not call this method for a non-commutable instruction or for
98   /// non-commutable pair of operand indices OpIdx1 and OpIdx2.
99   /// Even though the instruction is commutable, the method may still
100   /// fail to commute the operands, null pointer is returned in such cases.
101   MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
102                                        unsigned OpIdx1,
103                                        unsigned OpIdx2) const override;
104   /// If the specific machine instruction is an instruction that moves/copies
105   /// value from one register to another register return destination and source
106   /// registers as machine operands.
107   std::optional<DestSourcePair>
108   isCopyInstrImpl(const MachineInstr &MI) const override;
109 
110   /// Specialization of \ref TargetInstrInfo::describeLoadedValue, used to
111   /// enhance debug entry value descriptions for ARM targets.
112   std::optional<ParamLoadedValue>
113   describeLoadedValue(const MachineInstr &MI, Register Reg) const override;
114 
115 public:
116   // Return whether the target has an explicit NOP encoding.
117   bool hasNOP() const;
118 
119   // Return the non-pre/post incrementing version of 'Opc'. Return 0
120   // if there is not such an opcode.
121   virtual unsigned getUnindexedOpcode(unsigned Opc) const = 0;
122 
123   MachineInstr *convertToThreeAddress(MachineInstr &MI, LiveVariables *LV,
124                                       LiveIntervals *LIS) const override;
125 
126   virtual const ARMBaseRegisterInfo &getRegisterInfo() const = 0;
getSubtarget()127   const ARMSubtarget &getSubtarget() const { return Subtarget; }
128 
129   ScheduleHazardRecognizer *
130   CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
131                                const ScheduleDAG *DAG) const override;
132 
133   ScheduleHazardRecognizer *
134   CreateTargetMIHazardRecognizer(const InstrItineraryData *II,
135                                  const ScheduleDAGMI *DAG) const override;
136 
137   ScheduleHazardRecognizer *
138   CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
139                                      const ScheduleDAG *DAG) const override;
140 
141   // Branch analysis.
142   bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
143                      MachineBasicBlock *&FBB,
144                      SmallVectorImpl<MachineOperand> &Cond,
145                      bool AllowModify = false) const override;
146   unsigned removeBranch(MachineBasicBlock &MBB,
147                         int *BytesRemoved = nullptr) const override;
148   unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
149                         MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
150                         const DebugLoc &DL,
151                         int *BytesAdded = nullptr) const override;
152 
153   bool
154   reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
155 
156   // Predication support.
157   bool isPredicated(const MachineInstr &MI) const override;
158 
159   // MIR printer helper function to annotate Operands with a comment.
160   std::string
161   createMIROperandComment(const MachineInstr &MI, const MachineOperand &Op,
162                           unsigned OpIdx,
163                           const TargetRegisterInfo *TRI) const override;
164 
getPredicate(const MachineInstr & MI)165   ARMCC::CondCodes getPredicate(const MachineInstr &MI) const {
166     int PIdx = MI.findFirstPredOperandIdx();
167     return PIdx != -1 ? (ARMCC::CondCodes)MI.getOperand(PIdx).getImm()
168                       : ARMCC::AL;
169   }
170 
171   bool PredicateInstruction(MachineInstr &MI,
172                             ArrayRef<MachineOperand> Pred) const override;
173 
174   bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
175                          ArrayRef<MachineOperand> Pred2) const override;
176 
177   bool ClobbersPredicate(MachineInstr &MI, std::vector<MachineOperand> &Pred,
178                          bool SkipDead) const override;
179 
180   bool isPredicable(const MachineInstr &MI) const override;
181 
182   // CPSR defined in instruction
183   static bool isCPSRDefined(const MachineInstr &MI);
184 
185   /// GetInstSize - Returns the size of the specified MachineInstr.
186   ///
187   unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
188 
189   unsigned isLoadFromStackSlot(const MachineInstr &MI,
190                                int &FrameIndex) const override;
191   unsigned isStoreToStackSlot(const MachineInstr &MI,
192                               int &FrameIndex) const override;
193   unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI,
194                                      int &FrameIndex) const override;
195   unsigned isStoreToStackSlotPostFE(const MachineInstr &MI,
196                                     int &FrameIndex) const override;
197 
198   void copyToCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
199                   unsigned SrcReg, bool KillSrc,
200                   const ARMSubtarget &Subtarget) const;
201   void copyFromCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
202                     unsigned DestReg, bool KillSrc,
203                     const ARMSubtarget &Subtarget) const;
204 
205   void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
206                    const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
207                    bool KillSrc) const override;
208 
209   void storeRegToStackSlot(MachineBasicBlock &MBB,
210                            MachineBasicBlock::iterator MBBI, Register SrcReg,
211                            bool isKill, int FrameIndex,
212                            const TargetRegisterClass *RC,
213                            const TargetRegisterInfo *TRI,
214                            Register VReg) const override;
215 
216   void loadRegFromStackSlot(MachineBasicBlock &MBB,
217                             MachineBasicBlock::iterator MBBI, Register DestReg,
218                             int FrameIndex, const TargetRegisterClass *RC,
219                             const TargetRegisterInfo *TRI,
220                             Register VReg) const override;
221 
222   bool expandPostRAPseudo(MachineInstr &MI) const override;
223 
224   bool shouldSink(const MachineInstr &MI) const override;
225 
226   void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
227                      Register DestReg, unsigned SubIdx,
228                      const MachineInstr &Orig,
229                      const TargetRegisterInfo &TRI) const override;
230 
231   MachineInstr &
232   duplicate(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore,
233             const MachineInstr &Orig) const override;
234 
235   const MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
236                                      unsigned SubIdx, unsigned State,
237                                      const TargetRegisterInfo *TRI) const;
238 
239   bool produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1,
240                         const MachineRegisterInfo *MRI) const override;
241 
242   /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
243   /// determine if two loads are loading from the same base address. It should
244   /// only return true if the base pointers are the same and the only
245   /// differences between the two addresses is the offset. It also returns the
246   /// offsets by reference.
247   bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
248                                int64_t &Offset2) const override;
249 
250   /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
251   /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads
252   /// should be scheduled togther. On some targets if two loads are loading from
253   /// addresses in the same cache line, it's better if they are scheduled
254   /// together. This function takes two integers that represent the load offsets
255   /// from the common base address. It returns true if it decides it's desirable
256   /// to schedule the two loads together. "NumLoads" is the number of loads that
257   /// have already been scheduled after Load1.
258   bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
259                                int64_t Offset1, int64_t Offset2,
260                                unsigned NumLoads) const override;
261 
262   bool isSchedulingBoundary(const MachineInstr &MI,
263                             const MachineBasicBlock *MBB,
264                             const MachineFunction &MF) const override;
265 
266   bool isProfitableToIfCvt(MachineBasicBlock &MBB,
267                            unsigned NumCycles, unsigned ExtraPredCycles,
268                            BranchProbability Probability) const override;
269 
270   bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumT,
271                            unsigned ExtraT, MachineBasicBlock &FMBB,
272                            unsigned NumF, unsigned ExtraF,
273                            BranchProbability Probability) const override;
274 
isProfitableToDupForIfCvt(MachineBasicBlock & MBB,unsigned NumCycles,BranchProbability Probability)275   bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
276                                  BranchProbability Probability) const override {
277     return NumCycles == 1;
278   }
279 
280   unsigned extraSizeToPredicateInstructions(const MachineFunction &MF,
281                                             unsigned NumInsts) const override;
282   unsigned predictBranchSizeForIfCvt(MachineInstr &MI) const override;
283 
284   bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
285                                  MachineBasicBlock &FMBB) const override;
286 
287   /// analyzeCompare - For a comparison instruction, return the source registers
288   /// in SrcReg and SrcReg2 if having two register operands, and the value it
289   /// compares against in CmpValue. Return true if the comparison instruction
290   /// can be analyzed.
291   bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
292                       Register &SrcReg2, int64_t &CmpMask,
293                       int64_t &CmpValue) const override;
294 
295   /// optimizeCompareInstr - Convert the instruction to set the zero flag so
296   /// that we can remove a "comparison with zero"; Remove a redundant CMP
297   /// instruction if the flags can be updated in the same way by an earlier
298   /// instruction such as SUB.
299   bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
300                             Register SrcReg2, int64_t CmpMask, int64_t CmpValue,
301                             const MachineRegisterInfo *MRI) const override;
302 
303   bool analyzeSelect(const MachineInstr &MI,
304                      SmallVectorImpl<MachineOperand> &Cond, unsigned &TrueOp,
305                      unsigned &FalseOp, bool &Optimizable) const override;
306 
307   MachineInstr *optimizeSelect(MachineInstr &MI,
308                                SmallPtrSetImpl<MachineInstr *> &SeenMIs,
309                                bool) const override;
310 
311   /// FoldImmediate - 'Reg' is known to be defined by a move immediate
312   /// instruction, try to fold the immediate into the use instruction.
313   bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg,
314                      MachineRegisterInfo *MRI) const override;
315 
316   unsigned getNumMicroOps(const InstrItineraryData *ItinData,
317                           const MachineInstr &MI) const override;
318 
319   int getOperandLatency(const InstrItineraryData *ItinData,
320                         const MachineInstr &DefMI, unsigned DefIdx,
321                         const MachineInstr &UseMI,
322                         unsigned UseIdx) const override;
323   int getOperandLatency(const InstrItineraryData *ItinData,
324                         SDNode *DefNode, unsigned DefIdx,
325                         SDNode *UseNode, unsigned UseIdx) const override;
326 
327   /// VFP/NEON execution domains.
328   std::pair<uint16_t, uint16_t>
329   getExecutionDomain(const MachineInstr &MI) const override;
330   void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override;
331 
332   unsigned
333   getPartialRegUpdateClearance(const MachineInstr &, unsigned,
334                                const TargetRegisterInfo *) const override;
335   void breakPartialRegDependency(MachineInstr &, unsigned,
336                                  const TargetRegisterInfo *TRI) const override;
337 
338   /// Get the number of addresses by LDM or VLDM or zero for unknown.
339   unsigned getNumLDMAddresses(const MachineInstr &MI) const;
340 
341   std::pair<unsigned, unsigned>
342   decomposeMachineOperandsTargetFlags(unsigned TF) const override;
343   ArrayRef<std::pair<unsigned, const char *>>
344   getSerializableDirectMachineOperandTargetFlags() const override;
345   ArrayRef<std::pair<unsigned, const char *>>
346   getSerializableBitmaskMachineOperandTargetFlags() const override;
347 
348   /// ARM supports the MachineOutliner.
349   bool isFunctionSafeToOutlineFrom(MachineFunction &MF,
350                                    bool OutlineFromLinkOnceODRs) const override;
351   outliner::OutlinedFunction getOutliningCandidateInfo(
352       std::vector<outliner::Candidate> &RepeatedSequenceLocs) const override;
353   void mergeOutliningCandidateAttributes(
354       Function &F, std::vector<outliner::Candidate> &Candidates) const override;
355   outliner::InstrType getOutliningType(MachineBasicBlock::iterator &MIT,
356                                        unsigned Flags) const override;
357   bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB,
358                               unsigned &Flags) const override;
359   void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF,
360                           const outliner::OutlinedFunction &OF) const override;
361   MachineBasicBlock::iterator
362   insertOutlinedCall(Module &M, MachineBasicBlock &MBB,
363                      MachineBasicBlock::iterator &It, MachineFunction &MF,
364                      outliner::Candidate &C) const override;
365 
366   /// Enable outlining by default at -Oz.
367   bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override;
368 
isUnspillableTerminatorImpl(const MachineInstr * MI)369   bool isUnspillableTerminatorImpl(const MachineInstr *MI) const override {
370     return MI->getOpcode() == ARM::t2LoopEndDec ||
371            MI->getOpcode() == ARM::t2DoLoopStartTP ||
372            MI->getOpcode() == ARM::t2WhileLoopStartLR ||
373            MI->getOpcode() == ARM::t2WhileLoopStartTP;
374   }
375 
376   /// Analyze loop L, which must be a single-basic-block loop, and if the
377   /// conditions can be understood enough produce a PipelinerLoopInfo object.
378   std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo>
379   analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override;
380 
381 private:
382   /// Returns an unused general-purpose register which can be used for
383   /// constructing an outlined call if one exists. Returns 0 otherwise.
384   Register findRegisterToSaveLRTo(outliner::Candidate &C) const;
385 
386   /// Adds an instruction which saves the link register on top of the stack into
387   /// the MachineBasicBlock \p MBB at position \p It. If \p Auth is true,
388   /// compute and store an authentication code alongiside the link register.
389   /// If \p CFI is true, emit CFI instructions.
390   void saveLROnStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator It,
391                      bool CFI, bool Auth) const;
392 
393   /// Adds an instruction which restores the link register from the top the
394   /// stack into the MachineBasicBlock \p MBB at position \p It. If \p Auth is
395   /// true, restore an authentication code and authenticate LR.
396   /// If \p CFI is true, emit CFI instructions.
397   void restoreLRFromStack(MachineBasicBlock &MBB,
398                           MachineBasicBlock::iterator It, bool CFI,
399                           bool Auth) const;
400 
401   /// Emit CFI instructions into the MachineBasicBlock \p MBB at position \p It,
402   /// for the case when the LR is saved in the register \p Reg.
403   void emitCFIForLRSaveToReg(MachineBasicBlock &MBB,
404                              MachineBasicBlock::iterator It,
405                              Register Reg) const;
406 
407   /// Emit CFI instructions into the MachineBasicBlock \p MBB at position \p It,
408   /// after the LR is was restored from a register.
409   void emitCFIForLRRestoreFromReg(MachineBasicBlock &MBB,
410                                   MachineBasicBlock::iterator It) const;
411   /// \brief Sets the offsets on outlined instructions in \p MBB which use SP
412   /// so that they will be valid post-outlining.
413   ///
414   /// \param MBB A \p MachineBasicBlock in an outlined function.
415   void fixupPostOutline(MachineBasicBlock &MBB) const;
416 
417   /// Returns true if the machine instruction offset can handle the stack fixup
418   /// and updates it if requested.
419   bool checkAndUpdateStackOffset(MachineInstr *MI, int64_t Fixup,
420                                  bool Updt) const;
421 
422   unsigned getInstBundleLength(const MachineInstr &MI) const;
423 
424   int getVLDMDefCycle(const InstrItineraryData *ItinData,
425                       const MCInstrDesc &DefMCID,
426                       unsigned DefClass,
427                       unsigned DefIdx, unsigned DefAlign) const;
428   int getLDMDefCycle(const InstrItineraryData *ItinData,
429                      const MCInstrDesc &DefMCID,
430                      unsigned DefClass,
431                      unsigned DefIdx, unsigned DefAlign) const;
432   int getVSTMUseCycle(const InstrItineraryData *ItinData,
433                       const MCInstrDesc &UseMCID,
434                       unsigned UseClass,
435                       unsigned UseIdx, unsigned UseAlign) const;
436   int getSTMUseCycle(const InstrItineraryData *ItinData,
437                      const MCInstrDesc &UseMCID,
438                      unsigned UseClass,
439                      unsigned UseIdx, unsigned UseAlign) const;
440   int getOperandLatency(const InstrItineraryData *ItinData,
441                         const MCInstrDesc &DefMCID,
442                         unsigned DefIdx, unsigned DefAlign,
443                         const MCInstrDesc &UseMCID,
444                         unsigned UseIdx, unsigned UseAlign) const;
445 
446   int getOperandLatencyImpl(const InstrItineraryData *ItinData,
447                             const MachineInstr &DefMI, unsigned DefIdx,
448                             const MCInstrDesc &DefMCID, unsigned DefAdj,
449                             const MachineOperand &DefMO, unsigned Reg,
450                             const MachineInstr &UseMI, unsigned UseIdx,
451                             const MCInstrDesc &UseMCID, unsigned UseAdj) const;
452 
453   unsigned getPredicationCost(const MachineInstr &MI) const override;
454 
455   unsigned getInstrLatency(const InstrItineraryData *ItinData,
456                            const MachineInstr &MI,
457                            unsigned *PredCost = nullptr) const override;
458 
459   int getInstrLatency(const InstrItineraryData *ItinData,
460                       SDNode *Node) const override;
461 
462   bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
463                              const MachineRegisterInfo *MRI,
464                              const MachineInstr &DefMI, unsigned DefIdx,
465                              const MachineInstr &UseMI,
466                              unsigned UseIdx) const override;
467   bool hasLowDefLatency(const TargetSchedModel &SchedModel,
468                         const MachineInstr &DefMI,
469                         unsigned DefIdx) const override;
470 
471   /// verifyInstruction - Perform target specific instruction verification.
472   bool verifyInstruction(const MachineInstr &MI,
473                          StringRef &ErrInfo) const override;
474 
475   virtual void expandLoadStackGuard(MachineBasicBlock::iterator MI) const = 0;
476 
477   void expandMEMCPY(MachineBasicBlock::iterator) const;
478 
479   /// Identify instructions that can be folded into a MOVCC instruction, and
480   /// return the defining instruction.
481   MachineInstr *canFoldIntoMOVCC(Register Reg, const MachineRegisterInfo &MRI,
482                                  const TargetInstrInfo *TII) const;
483 
484   bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override;
485 
486 private:
487   /// Modeling special VFP / NEON fp MLA / MLS hazards.
488 
489   /// MLxEntryMap - Map fp MLA / MLS to the corresponding entry in the internal
490   /// MLx table.
491   DenseMap<unsigned, unsigned> MLxEntryMap;
492 
493   /// MLxHazardOpcodes - Set of add / sub and multiply opcodes that would cause
494   /// stalls when scheduled together with fp MLA / MLS opcodes.
495   SmallSet<unsigned, 16> MLxHazardOpcodes;
496 
497 public:
498   /// isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS
499   /// instruction.
isFpMLxInstruction(unsigned Opcode)500   bool isFpMLxInstruction(unsigned Opcode) const {
501     return MLxEntryMap.count(Opcode);
502   }
503 
504   /// isFpMLxInstruction - This version also returns the multiply opcode and the
505   /// addition / subtraction opcode to expand to. Return true for 'HasLane' for
506   /// the MLX instructions with an extra lane operand.
507   bool isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
508                           unsigned &AddSubOpc, bool &NegAcc,
509                           bool &HasLane) const;
510 
511   /// canCauseFpMLxStall - Return true if an instruction of the specified opcode
512   /// will cause stalls when scheduled after (within 4-cycle window) a fp
513   /// MLA / MLS instruction.
canCauseFpMLxStall(unsigned Opcode)514   bool canCauseFpMLxStall(unsigned Opcode) const {
515     return MLxHazardOpcodes.count(Opcode);
516   }
517 
518   /// Returns true if the instruction has a shift by immediate that can be
519   /// executed in one cycle less.
520   bool isSwiftFastImmShift(const MachineInstr *MI) const;
521 
522   /// Returns predicate register associated with the given frame instruction.
getFramePred(const MachineInstr & MI)523   unsigned getFramePred(const MachineInstr &MI) const {
524     assert(isFrameInstr(MI));
525     // Operands of ADJCALLSTACKDOWN/ADJCALLSTACKUP:
526     // - argument declared in the pattern:
527     // 0 - frame size
528     // 1 - arg of CALLSEQ_START/CALLSEQ_END
529     // 2 - predicate code (like ARMCC::AL)
530     // - added by predOps:
531     // 3 - predicate reg
532     return MI.getOperand(3).getReg();
533   }
534 
535   std::optional<RegImmPair> isAddImmediate(const MachineInstr &MI,
536                                            Register Reg) const override;
537 };
538 
539 /// Get the operands corresponding to the given \p Pred value. By default, the
540 /// predicate register is assumed to be 0 (no register), but you can pass in a
541 /// \p PredReg if that is not the case.
542 static inline std::array<MachineOperand, 2> predOps(ARMCC::CondCodes Pred,
543                                                     unsigned PredReg = 0) {
544   return {{MachineOperand::CreateImm(static_cast<int64_t>(Pred)),
545            MachineOperand::CreateReg(PredReg, false)}};
546 }
547 
548 /// Get the operand corresponding to the conditional code result. By default,
549 /// this is 0 (no register).
550 static inline MachineOperand condCodeOp(unsigned CCReg = 0) {
551   return MachineOperand::CreateReg(CCReg, false);
552 }
553 
554 /// Get the operand corresponding to the conditional code result for Thumb1.
555 /// This operand will always refer to CPSR and it will have the Define flag set.
556 /// You can optionally set the Dead flag by means of \p isDead.
557 static inline MachineOperand t1CondCodeOp(bool isDead = false) {
558   return MachineOperand::CreateReg(ARM::CPSR,
559                                    /*Define*/ true, /*Implicit*/ false,
560                                    /*Kill*/ false, isDead);
561 }
562 
563 static inline
isUncondBranchOpcode(int Opc)564 bool isUncondBranchOpcode(int Opc) {
565   return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
566 }
567 
568 // This table shows the VPT instruction variants, i.e. the different
569 // mask field encodings, see also B5.6. Predication/conditional execution in
570 // the ArmARM.
isVPTOpcode(int Opc)571 static inline bool isVPTOpcode(int Opc) {
572   return Opc == ARM::MVE_VPTv16i8 || Opc == ARM::MVE_VPTv16u8 ||
573          Opc == ARM::MVE_VPTv16s8 || Opc == ARM::MVE_VPTv8i16 ||
574          Opc == ARM::MVE_VPTv8u16 || Opc == ARM::MVE_VPTv8s16 ||
575          Opc == ARM::MVE_VPTv4i32 || Opc == ARM::MVE_VPTv4u32 ||
576          Opc == ARM::MVE_VPTv4s32 || Opc == ARM::MVE_VPTv4f32 ||
577          Opc == ARM::MVE_VPTv8f16 || Opc == ARM::MVE_VPTv16i8r ||
578          Opc == ARM::MVE_VPTv16u8r || Opc == ARM::MVE_VPTv16s8r ||
579          Opc == ARM::MVE_VPTv8i16r || Opc == ARM::MVE_VPTv8u16r ||
580          Opc == ARM::MVE_VPTv8s16r || Opc == ARM::MVE_VPTv4i32r ||
581          Opc == ARM::MVE_VPTv4u32r || Opc == ARM::MVE_VPTv4s32r ||
582          Opc == ARM::MVE_VPTv4f32r || Opc == ARM::MVE_VPTv8f16r ||
583          Opc == ARM::MVE_VPST;
584 }
585 
586 static inline
VCMPOpcodeToVPT(unsigned Opcode)587 unsigned VCMPOpcodeToVPT(unsigned Opcode) {
588   switch (Opcode) {
589   default:
590     return 0;
591   case ARM::MVE_VCMPf32:
592     return ARM::MVE_VPTv4f32;
593   case ARM::MVE_VCMPf16:
594     return ARM::MVE_VPTv8f16;
595   case ARM::MVE_VCMPi8:
596     return ARM::MVE_VPTv16i8;
597   case ARM::MVE_VCMPi16:
598     return ARM::MVE_VPTv8i16;
599   case ARM::MVE_VCMPi32:
600     return ARM::MVE_VPTv4i32;
601   case ARM::MVE_VCMPu8:
602     return ARM::MVE_VPTv16u8;
603   case ARM::MVE_VCMPu16:
604     return ARM::MVE_VPTv8u16;
605   case ARM::MVE_VCMPu32:
606     return ARM::MVE_VPTv4u32;
607   case ARM::MVE_VCMPs8:
608     return ARM::MVE_VPTv16s8;
609   case ARM::MVE_VCMPs16:
610     return ARM::MVE_VPTv8s16;
611   case ARM::MVE_VCMPs32:
612     return ARM::MVE_VPTv4s32;
613 
614   case ARM::MVE_VCMPf32r:
615     return ARM::MVE_VPTv4f32r;
616   case ARM::MVE_VCMPf16r:
617     return ARM::MVE_VPTv8f16r;
618   case ARM::MVE_VCMPi8r:
619     return ARM::MVE_VPTv16i8r;
620   case ARM::MVE_VCMPi16r:
621     return ARM::MVE_VPTv8i16r;
622   case ARM::MVE_VCMPi32r:
623     return ARM::MVE_VPTv4i32r;
624   case ARM::MVE_VCMPu8r:
625     return ARM::MVE_VPTv16u8r;
626   case ARM::MVE_VCMPu16r:
627     return ARM::MVE_VPTv8u16r;
628   case ARM::MVE_VCMPu32r:
629     return ARM::MVE_VPTv4u32r;
630   case ARM::MVE_VCMPs8r:
631     return ARM::MVE_VPTv16s8r;
632   case ARM::MVE_VCMPs16r:
633     return ARM::MVE_VPTv8s16r;
634   case ARM::MVE_VCMPs32r:
635     return ARM::MVE_VPTv4s32r;
636   }
637 }
638 
639 static inline
isCondBranchOpcode(int Opc)640 bool isCondBranchOpcode(int Opc) {
641   return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc;
642 }
643 
isJumpTableBranchOpcode(int Opc)644 static inline bool isJumpTableBranchOpcode(int Opc) {
645   return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm_i12 ||
646          Opc == ARM::BR_JTm_rs || Opc == ARM::BR_JTadd || Opc == ARM::tBR_JTr ||
647          Opc == ARM::t2BR_JT;
648 }
649 
650 static inline
isIndirectBranchOpcode(int Opc)651 bool isIndirectBranchOpcode(int Opc) {
652   return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND;
653 }
654 
isIndirectCall(const MachineInstr & MI)655 static inline bool isIndirectCall(const MachineInstr &MI) {
656   int Opc = MI.getOpcode();
657   switch (Opc) {
658     // indirect calls:
659   case ARM::BLX:
660   case ARM::BLX_noip:
661   case ARM::BLX_pred:
662   case ARM::BLX_pred_noip:
663   case ARM::BX_CALL:
664   case ARM::BMOVPCRX_CALL:
665   case ARM::TCRETURNri:
666   case ARM::TAILJMPr:
667   case ARM::TAILJMPr4:
668   case ARM::tBLXr:
669   case ARM::tBLXr_noip:
670   case ARM::tBLXNSr:
671   case ARM::tBLXNS_CALL:
672   case ARM::tBX_CALL:
673   case ARM::tTAILJMPr:
674     assert(MI.isCall(MachineInstr::IgnoreBundle));
675     return true;
676     // direct calls:
677   case ARM::BL:
678   case ARM::BL_pred:
679   case ARM::BMOVPCB_CALL:
680   case ARM::BL_PUSHLR:
681   case ARM::BLXi:
682   case ARM::TCRETURNdi:
683   case ARM::TAILJMPd:
684   case ARM::SVC:
685   case ARM::HVC:
686   case ARM::TPsoft:
687   case ARM::tTAILJMPd:
688   case ARM::t2SMC:
689   case ARM::t2HVC:
690   case ARM::tBL:
691   case ARM::tBLXi:
692   case ARM::tBL_PUSHLR:
693   case ARM::tTAILJMPdND:
694   case ARM::tSVC:
695   case ARM::tTPsoft:
696     assert(MI.isCall(MachineInstr::IgnoreBundle));
697     return false;
698   }
699   assert(!MI.isCall(MachineInstr::IgnoreBundle));
700   return false;
701 }
702 
isIndirectControlFlowNotComingBack(const MachineInstr & MI)703 static inline bool isIndirectControlFlowNotComingBack(const MachineInstr &MI) {
704   int opc = MI.getOpcode();
705   return MI.isReturn() || isIndirectBranchOpcode(MI.getOpcode()) ||
706          isJumpTableBranchOpcode(opc);
707 }
708 
isSpeculationBarrierEndBBOpcode(int Opc)709 static inline bool isSpeculationBarrierEndBBOpcode(int Opc) {
710   return Opc == ARM::SpeculationBarrierISBDSBEndBB ||
711          Opc == ARM::SpeculationBarrierSBEndBB ||
712          Opc == ARM::t2SpeculationBarrierISBDSBEndBB ||
713          Opc == ARM::t2SpeculationBarrierSBEndBB;
714 }
715 
isPopOpcode(int Opc)716 static inline bool isPopOpcode(int Opc) {
717   return Opc == ARM::tPOP_RET || Opc == ARM::LDMIA_RET ||
718          Opc == ARM::t2LDMIA_RET || Opc == ARM::tPOP || Opc == ARM::LDMIA_UPD ||
719          Opc == ARM::t2LDMIA_UPD || Opc == ARM::VLDMDIA_UPD;
720 }
721 
isPushOpcode(int Opc)722 static inline bool isPushOpcode(int Opc) {
723   return Opc == ARM::tPUSH || Opc == ARM::t2STMDB_UPD ||
724          Opc == ARM::STMDB_UPD || Opc == ARM::VSTMDDB_UPD;
725 }
726 
isSubImmOpcode(int Opc)727 static inline bool isSubImmOpcode(int Opc) {
728   return Opc == ARM::SUBri ||
729          Opc == ARM::tSUBi3 || Opc == ARM::tSUBi8 ||
730          Opc == ARM::tSUBSi3 || Opc == ARM::tSUBSi8 ||
731          Opc == ARM::t2SUBri || Opc == ARM::t2SUBri12 || Opc == ARM::t2SUBSri;
732 }
733 
isMovRegOpcode(int Opc)734 static inline bool isMovRegOpcode(int Opc) {
735   return Opc == ARM::MOVr || Opc == ARM::tMOVr || Opc == ARM::t2MOVr;
736 }
737 /// isValidCoprocessorNumber - decide whether an explicit coprocessor
738 /// number is legal in generic instructions like CDP. The answer can
739 /// vary with the subtarget.
isValidCoprocessorNumber(unsigned Num,const FeatureBitset & featureBits)740 static inline bool isValidCoprocessorNumber(unsigned Num,
741                                             const FeatureBitset& featureBits) {
742   // In Armv7 and Armv8-M CP10 and CP11 clash with VFP/NEON, however, the
743   // coprocessor is still valid for CDP/MCR/MRC and friends. Allowing it is
744   // useful for code which is shared with older architectures which do not know
745   // the new VFP/NEON mnemonics.
746 
747   // Armv8-A disallows everything *other* than 111x (CP14 and CP15).
748   if (featureBits[ARM::HasV8Ops] && (Num & 0xE) != 0xE)
749     return false;
750 
751   // Armv8.1-M disallows 100x (CP8,CP9) and 111x (CP14,CP15)
752   // which clash with MVE.
753   if (featureBits[ARM::HasV8_1MMainlineOps] &&
754       ((Num & 0xE) == 0x8 || (Num & 0xE) == 0xE))
755     return false;
756 
757   return true;
758 }
759 
isSEHInstruction(const MachineInstr & MI)760 static inline bool isSEHInstruction(const MachineInstr &MI) {
761   unsigned Opc = MI.getOpcode();
762   switch (Opc) {
763   case ARM::SEH_StackAlloc:
764   case ARM::SEH_SaveRegs:
765   case ARM::SEH_SaveRegs_Ret:
766   case ARM::SEH_SaveSP:
767   case ARM::SEH_SaveFRegs:
768   case ARM::SEH_SaveLR:
769   case ARM::SEH_Nop:
770   case ARM::SEH_Nop_Ret:
771   case ARM::SEH_PrologEnd:
772   case ARM::SEH_EpilogStart:
773   case ARM::SEH_EpilogEnd:
774     return true;
775   default:
776     return false;
777   }
778 }
779 
780 /// getInstrPredicate - If instruction is predicated, returns its predicate
781 /// condition, otherwise returns AL. It also returns the condition code
782 /// register by reference.
783 ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, Register &PredReg);
784 
785 unsigned getMatchingCondBranchOpcode(unsigned Opc);
786 
787 /// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether
788 /// the instruction is encoded with an 'S' bit is determined by the optional
789 /// CPSR def operand.
790 unsigned convertAddSubFlagsOpcode(unsigned OldOpc);
791 
792 /// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of
793 /// instructions to materializea destreg = basereg + immediate in ARM / Thumb2
794 /// code.
795 void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
796                              MachineBasicBlock::iterator &MBBI,
797                              const DebugLoc &dl, Register DestReg,
798                              Register BaseReg, int NumBytes,
799                              ARMCC::CondCodes Pred, Register PredReg,
800                              const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
801 
802 void emitT2RegPlusImmediate(MachineBasicBlock &MBB,
803                             MachineBasicBlock::iterator &MBBI,
804                             const DebugLoc &dl, Register DestReg,
805                             Register BaseReg, int NumBytes,
806                             ARMCC::CondCodes Pred, Register PredReg,
807                             const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
808 void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
809                                MachineBasicBlock::iterator &MBBI,
810                                const DebugLoc &dl, Register DestReg,
811                                Register BaseReg, int NumBytes,
812                                const TargetInstrInfo &TII,
813                                const ARMBaseRegisterInfo &MRI,
814                                unsigned MIFlags = 0);
815 
816 /// Tries to add registers to the reglist of a given base-updating
817 /// push/pop instruction to adjust the stack by an additional
818 /// NumBytes. This can save a few bytes per function in code-size, but
819 /// obviously generates more memory traffic. As such, it only takes
820 /// effect in functions being optimised for size.
821 bool tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget,
822                                 MachineFunction &MF, MachineInstr *MI,
823                                 unsigned NumBytes);
824 
825 /// rewriteARMFrameIndex / rewriteT2FrameIndex -
826 /// Rewrite MI to access 'Offset' bytes from the FP. Return false if the
827 /// offset could not be handled directly in MI, and return the left-over
828 /// portion by reference.
829 bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
830                           Register FrameReg, int &Offset,
831                           const ARMBaseInstrInfo &TII);
832 
833 bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
834                          Register FrameReg, int &Offset,
835                          const ARMBaseInstrInfo &TII,
836                          const TargetRegisterInfo *TRI);
837 
838 /// Return true if Reg is defd between From and To
839 bool registerDefinedBetween(unsigned Reg, MachineBasicBlock::iterator From,
840                             MachineBasicBlock::iterator To,
841                             const TargetRegisterInfo *TRI);
842 
843 /// Search backwards from a tBcc to find a tCMPi8 against 0, meaning
844 /// we can convert them to a tCBZ or tCBNZ. Return nullptr if not found.
845 MachineInstr *findCMPToFoldIntoCBZ(MachineInstr *Br,
846                                    const TargetRegisterInfo *TRI);
847 
848 void addUnpredicatedMveVpredNOp(MachineInstrBuilder &MIB);
849 void addUnpredicatedMveVpredROp(MachineInstrBuilder &MIB, Register DestReg);
850 
851 void addPredicatedMveVpredNOp(MachineInstrBuilder &MIB, unsigned Cond);
852 void addPredicatedMveVpredROp(MachineInstrBuilder &MIB, unsigned Cond,
853                               unsigned Inactive);
854 
855 /// Returns the number of instructions required to materialize the given
856 /// constant in a register, or 3 if a literal pool load is needed.
857 /// If ForCodesize is specified, an approximate cost in bytes is returned.
858 unsigned ConstantMaterializationCost(unsigned Val,
859                                      const ARMSubtarget *Subtarget,
860                                      bool ForCodesize = false);
861 
862 /// Returns true if Val1 has a lower Constant Materialization Cost than Val2.
863 /// Uses the cost from ConstantMaterializationCost, first with ForCodesize as
864 /// specified. If the scores are equal, return the comparison for !ForCodesize.
865 bool HasLowerConstantMaterializationCost(unsigned Val1, unsigned Val2,
866                                          const ARMSubtarget *Subtarget,
867                                          bool ForCodesize = false);
868 
869 // Return the immediate if this is ADDri or SUBri, scaled as appropriate.
870 // Returns 0 for unknown instructions.
getAddSubImmediate(MachineInstr & MI)871 inline int getAddSubImmediate(MachineInstr &MI) {
872   int Scale = 1;
873   unsigned ImmOp;
874   switch (MI.getOpcode()) {
875   case ARM::t2ADDri:
876     ImmOp = 2;
877     break;
878   case ARM::t2SUBri:
879   case ARM::t2SUBri12:
880     ImmOp = 2;
881     Scale = -1;
882     break;
883   case ARM::tSUBi3:
884   case ARM::tSUBi8:
885     ImmOp = 3;
886     Scale = -1;
887     break;
888   default:
889     return 0;
890   }
891   return Scale * MI.getOperand(ImmOp).getImm();
892 }
893 
894 // Given a memory access Opcode, check that the give Imm would be a valid Offset
895 // for this instruction using its addressing mode.
isLegalAddressImm(unsigned Opcode,int Imm,const TargetInstrInfo * TII)896 inline bool isLegalAddressImm(unsigned Opcode, int Imm,
897                               const TargetInstrInfo *TII) {
898   const MCInstrDesc &Desc = TII->get(Opcode);
899   unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
900   switch (AddrMode) {
901   case ARMII::AddrModeT2_i7:
902     return std::abs(Imm) < ((1 << 7) * 1);
903   case ARMII::AddrModeT2_i7s2:
904     return std::abs(Imm) < ((1 << 7) * 2) && Imm % 2 == 0;
905   case ARMII::AddrModeT2_i7s4:
906     return std::abs(Imm) < ((1 << 7) * 4) && Imm % 4 == 0;
907   case ARMII::AddrModeT2_i8:
908     return std::abs(Imm) < ((1 << 8) * 1);
909   case ARMII::AddrModeT2_i8pos:
910     return Imm >= 0 && Imm < ((1 << 8) * 1);
911   case ARMII::AddrModeT2_i8neg:
912     return Imm < 0 && -Imm < ((1 << 8) * 1);
913   case ARMII::AddrModeT2_i8s4:
914     return std::abs(Imm) < ((1 << 8) * 4) && Imm % 4 == 0;
915   case ARMII::AddrModeT2_i12:
916     return Imm >= 0 && Imm < ((1 << 12) * 1);
917   case ARMII::AddrMode2:
918     return std::abs(Imm) < ((1 << 12) * 1);
919   default:
920     llvm_unreachable("Unhandled Addressing mode");
921   }
922 }
923 
924 // Return true if the given intrinsic is a gather
isGather(IntrinsicInst * IntInst)925 inline bool isGather(IntrinsicInst *IntInst) {
926   if (IntInst == nullptr)
927     return false;
928   unsigned IntrinsicID = IntInst->getIntrinsicID();
929   return (IntrinsicID == Intrinsic::masked_gather ||
930           IntrinsicID == Intrinsic::arm_mve_vldr_gather_base ||
931           IntrinsicID == Intrinsic::arm_mve_vldr_gather_base_predicated ||
932           IntrinsicID == Intrinsic::arm_mve_vldr_gather_base_wb ||
933           IntrinsicID == Intrinsic::arm_mve_vldr_gather_base_wb_predicated ||
934           IntrinsicID == Intrinsic::arm_mve_vldr_gather_offset ||
935           IntrinsicID == Intrinsic::arm_mve_vldr_gather_offset_predicated);
936 }
937 
938 // Return true if the given intrinsic is a scatter
isScatter(IntrinsicInst * IntInst)939 inline bool isScatter(IntrinsicInst *IntInst) {
940   if (IntInst == nullptr)
941     return false;
942   unsigned IntrinsicID = IntInst->getIntrinsicID();
943   return (IntrinsicID == Intrinsic::masked_scatter ||
944           IntrinsicID == Intrinsic::arm_mve_vstr_scatter_base ||
945           IntrinsicID == Intrinsic::arm_mve_vstr_scatter_base_predicated ||
946           IntrinsicID == Intrinsic::arm_mve_vstr_scatter_base_wb ||
947           IntrinsicID == Intrinsic::arm_mve_vstr_scatter_base_wb_predicated ||
948           IntrinsicID == Intrinsic::arm_mve_vstr_scatter_offset ||
949           IntrinsicID == Intrinsic::arm_mve_vstr_scatter_offset_predicated);
950 }
951 
952 // Return true if the given intrinsic is a gather or scatter
isGatherScatter(IntrinsicInst * IntInst)953 inline bool isGatherScatter(IntrinsicInst *IntInst) {
954   if (IntInst == nullptr)
955     return false;
956   return isGather(IntInst) || isScatter(IntInst);
957 }
958 
959 unsigned getBLXOpcode(const MachineFunction &MF);
960 unsigned gettBLXrOpcode(const MachineFunction &MF);
961 unsigned getBLXpredOpcode(const MachineFunction &MF);
962 
963 } // end namespace llvm
964 
965 #endif // LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
966