1 //===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the PPC specific subclass of TargetSubtargetInfo.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "PPCSubtarget.h"
14 #include "GISel/PPCCallLowering.h"
15 #include "GISel/PPCLegalizerInfo.h"
16 #include "GISel/PPCRegisterBankInfo.h"
17 #include "PPC.h"
18 #include "PPCRegisterInfo.h"
19 #include "PPCTargetMachine.h"
20 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineScheduler.h"
23 #include "llvm/IR/Attributes.h"
24 #include "llvm/IR/Function.h"
25 #include "llvm/IR/GlobalValue.h"
26 #include "llvm/Support/CommandLine.h"
27 #include "llvm/Support/TargetRegistry.h"
28 #include "llvm/Target/TargetMachine.h"
29 #include <cstdlib>
30
31 using namespace llvm;
32
33 #define DEBUG_TYPE "ppc-subtarget"
34
35 #define GET_SUBTARGETINFO_TARGET_DESC
36 #define GET_SUBTARGETINFO_CTOR
37 #include "PPCGenSubtargetInfo.inc"
38
39 static cl::opt<bool> UseSubRegLiveness("ppc-track-subreg-liveness",
40 cl::desc("Enable subregister liveness tracking for PPC"), cl::Hidden);
41
42 static cl::opt<bool>
43 EnableMachinePipeliner("ppc-enable-pipeliner",
44 cl::desc("Enable Machine Pipeliner for PPC"),
45 cl::init(false), cl::Hidden);
46
initializeSubtargetDependencies(StringRef CPU,StringRef FS)47 PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU,
48 StringRef FS) {
49 initializeEnvironment();
50 initSubtargetFeatures(CPU, FS);
51 return *this;
52 }
53
PPCSubtarget(const Triple & TT,const std::string & CPU,const std::string & FS,const PPCTargetMachine & TM)54 PPCSubtarget::PPCSubtarget(const Triple &TT, const std::string &CPU,
55 const std::string &FS, const PPCTargetMachine &TM)
56 : PPCGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), TargetTriple(TT),
57 IsPPC64(TargetTriple.getArch() == Triple::ppc64 ||
58 TargetTriple.getArch() == Triple::ppc64le),
59 TM(TM), FrameLowering(initializeSubtargetDependencies(CPU, FS)),
60 InstrInfo(*this), TLInfo(TM, *this) {
61 CallLoweringInfo.reset(new PPCCallLowering(*getTargetLowering()));
62 Legalizer.reset(new PPCLegalizerInfo(*this));
63 auto *RBI = new PPCRegisterBankInfo(*getRegisterInfo());
64 RegBankInfo.reset(RBI);
65
66 InstSelector.reset(createPPCInstructionSelector(
67 *static_cast<const PPCTargetMachine *>(&TM), *this, *RBI));
68 }
69
initializeEnvironment()70 void PPCSubtarget::initializeEnvironment() {
71 StackAlignment = Align(16);
72 CPUDirective = PPC::DIR_NONE;
73 HasMFOCRF = false;
74 Has64BitSupport = false;
75 Use64BitRegs = false;
76 UseCRBits = false;
77 HasHardFloat = false;
78 HasAltivec = false;
79 HasSPE = false;
80 HasEFPU2 = false;
81 HasFPU = false;
82 HasVSX = false;
83 NeedsTwoConstNR = false;
84 HasP8Vector = false;
85 HasP8Altivec = false;
86 HasP8Crypto = false;
87 HasP9Vector = false;
88 HasP9Altivec = false;
89 HasMMA = false;
90 HasROPProtect = false;
91 HasPrivileged = false;
92 HasP10Vector = false;
93 HasPrefixInstrs = false;
94 HasPCRelativeMemops = false;
95 HasFCPSGN = false;
96 HasFSQRT = false;
97 HasFRE = false;
98 HasFRES = false;
99 HasFRSQRTE = false;
100 HasFRSQRTES = false;
101 HasRecipPrec = false;
102 HasSTFIWX = false;
103 HasLFIWAX = false;
104 HasFPRND = false;
105 HasFPCVT = false;
106 HasISEL = false;
107 HasBPERMD = false;
108 HasExtDiv = false;
109 HasCMPB = false;
110 HasLDBRX = false;
111 IsBookE = false;
112 HasOnlyMSYNC = false;
113 IsPPC4xx = false;
114 IsPPC6xx = false;
115 IsE500 = false;
116 FeatureMFTB = false;
117 AllowsUnalignedFPAccess = false;
118 DeprecatedDST = false;
119 HasICBT = false;
120 HasInvariantFunctionDescriptors = false;
121 HasPartwordAtomics = false;
122 HasDirectMove = false;
123 HasHTM = false;
124 HasFloat128 = false;
125 HasFusion = false;
126 HasStoreFusion = false;
127 HasAddiLoadFusion = false;
128 HasAddisLoadFusion = false;
129 IsISA3_0 = false;
130 IsISA3_1 = false;
131 UseLongCalls = false;
132 SecurePlt = false;
133 VectorsUseTwoUnits = false;
134 UsePPCPreRASchedStrategy = false;
135 UsePPCPostRASchedStrategy = false;
136 PairedVectorMemops = false;
137 PredictableSelectIsExpensive = false;
138 HasModernAIXAs = false;
139 IsAIX = false;
140
141 HasPOPCNTD = POPCNTD_Unavailable;
142 }
143
initSubtargetFeatures(StringRef CPU,StringRef FS)144 void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
145 // Determine default and user specified characteristics
146 std::string CPUName = std::string(CPU);
147 if (CPUName.empty() || CPU == "generic") {
148 // If cross-compiling with -march=ppc64le without -mcpu
149 if (TargetTriple.getArch() == Triple::ppc64le)
150 CPUName = "ppc64le";
151 else if (TargetTriple.getSubArch() == Triple::PPCSubArch_spe)
152 CPUName = "e500";
153 else
154 CPUName = "generic";
155 }
156
157 // Initialize scheduling itinerary for the specified CPU.
158 InstrItins = getInstrItineraryForCPU(CPUName);
159
160 // Parse features string.
161 ParseSubtargetFeatures(CPUName, /*TuneCPU*/ CPUName, FS);
162
163 // If the user requested use of 64-bit regs, but the cpu selected doesn't
164 // support it, ignore.
165 if (IsPPC64 && has64BitSupport())
166 Use64BitRegs = true;
167
168 if ((TargetTriple.isOSFreeBSD() && TargetTriple.getOSMajorVersion() >= 13) ||
169 TargetTriple.isOSNetBSD() || TargetTriple.isOSOpenBSD() ||
170 TargetTriple.isMusl())
171 SecurePlt = true;
172
173 if (HasSPE && IsPPC64)
174 report_fatal_error( "SPE is only supported for 32-bit targets.\n", false);
175 if (HasSPE && (HasAltivec || HasVSX || HasFPU))
176 report_fatal_error(
177 "SPE and traditional floating point cannot both be enabled.\n", false);
178
179 // If not SPE, set standard FPU
180 if (!HasSPE)
181 HasFPU = true;
182
183 StackAlignment = getPlatformStackAlignment();
184
185 // Determine endianness.
186 IsLittleEndian = TM.isLittleEndian();
187 }
188
enableMachineScheduler() const189 bool PPCSubtarget::enableMachineScheduler() const { return true; }
190
enableMachinePipeliner() const191 bool PPCSubtarget::enableMachinePipeliner() const {
192 return getSchedModel().hasInstrSchedModel() && EnableMachinePipeliner;
193 }
194
useDFAforSMS() const195 bool PPCSubtarget::useDFAforSMS() const { return false; }
196
197 // This overrides the PostRAScheduler bit in the SchedModel for each CPU.
enablePostRAScheduler() const198 bool PPCSubtarget::enablePostRAScheduler() const { return true; }
199
getAntiDepBreakMode() const200 PPCGenSubtargetInfo::AntiDepBreakMode PPCSubtarget::getAntiDepBreakMode() const {
201 return TargetSubtargetInfo::ANTIDEP_ALL;
202 }
203
getCriticalPathRCs(RegClassVector & CriticalPathRCs) const204 void PPCSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
205 CriticalPathRCs.clear();
206 CriticalPathRCs.push_back(isPPC64() ?
207 &PPC::G8RCRegClass : &PPC::GPRCRegClass);
208 }
209
overrideSchedPolicy(MachineSchedPolicy & Policy,unsigned NumRegionInstrs) const210 void PPCSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
211 unsigned NumRegionInstrs) const {
212 // The GenericScheduler that we use defaults to scheduling bottom up only.
213 // We want to schedule from both the top and the bottom and so we set
214 // OnlyBottomUp to false.
215 // We want to do bi-directional scheduling since it provides a more balanced
216 // schedule leading to better performance.
217 Policy.OnlyBottomUp = false;
218 // Spilling is generally expensive on all PPC cores, so always enable
219 // register-pressure tracking.
220 Policy.ShouldTrackPressure = true;
221 }
222
useAA() const223 bool PPCSubtarget::useAA() const {
224 return true;
225 }
226
enableSubRegLiveness() const227 bool PPCSubtarget::enableSubRegLiveness() const {
228 return UseSubRegLiveness;
229 }
230
isGVIndirectSymbol(const GlobalValue * GV) const231 bool PPCSubtarget::isGVIndirectSymbol(const GlobalValue *GV) const {
232 // Large code model always uses the TOC even for local symbols.
233 if (TM.getCodeModel() == CodeModel::Large)
234 return true;
235 if (TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
236 return false;
237 return true;
238 }
239
isELFv2ABI() const240 bool PPCSubtarget::isELFv2ABI() const { return TM.isELFv2ABI(); }
isPPC64() const241 bool PPCSubtarget::isPPC64() const { return TM.isPPC64(); }
242
isUsingPCRelativeCalls() const243 bool PPCSubtarget::isUsingPCRelativeCalls() const {
244 return isPPC64() && hasPCRelativeMemops() && isELFv2ABI() &&
245 CodeModel::Medium == getTargetMachine().getCodeModel();
246 }
247
248 // GlobalISEL
getCallLowering() const249 const CallLowering *PPCSubtarget::getCallLowering() const {
250 return CallLoweringInfo.get();
251 }
252
getRegBankInfo() const253 const RegisterBankInfo *PPCSubtarget::getRegBankInfo() const {
254 return RegBankInfo.get();
255 }
256
getLegalizerInfo() const257 const LegalizerInfo *PPCSubtarget::getLegalizerInfo() const {
258 return Legalizer.get();
259 }
260
getInstructionSelector() const261 InstructionSelector *PPCSubtarget::getInstructionSelector() const {
262 return InstSelector.get();
263 }
264