1 /* $OpenBSD: shpcic_machdep.c,v 1.6 2017/09/08 05:36:52 deraadt Exp $ */
2 /* $NetBSD: shpcic_machdep.c,v 1.1 2006/09/01 21:26:18 uwe Exp $ */
3
4 /*
5 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
6 * Copyright (c) 1994 Charles M. Hannum. All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Charles M. Hannum.
19 * 4. The name of the author may not be used to endorse or promote products
20 * derived from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 /*
35 * Machine-specific functions for PCI autoconfiguration.
36 */
37
38 #include <sys/param.h>
39 #include <sys/time.h>
40 #include <sys/systm.h>
41 #include <sys/errno.h>
42 #include <sys/extent.h>
43 #include <sys/device.h>
44
45 #include <uvm/uvm_extern.h>
46
47 #include <dev/pci/pcivar.h>
48 #include <dev/pci/pcireg.h>
49 #include <dev/pci/pcidevs.h>
50 #if 0
51 #include <dev/pci/pciconf.h>
52 #endif
53
54 #include <machine/bus.h>
55 #include <machine/intr.h>
56
57 bus_space_tag_t
shpcic_get_bus_io_tag(void)58 shpcic_get_bus_io_tag(void)
59 {
60 extern struct _bus_space landisk_pci_bus_io;
61
62 return &landisk_pci_bus_io;
63 }
64
65 bus_space_tag_t
shpcic_get_bus_mem_tag(void)66 shpcic_get_bus_mem_tag(void)
67 {
68 extern struct _bus_space landisk_pci_bus_mem;
69
70 return &landisk_pci_bus_mem;
71 }
72
73 bus_dma_tag_t
shpcic_get_bus_dma_tag(void)74 shpcic_get_bus_dma_tag(void)
75 {
76 extern struct _bus_dma_tag landisk_bus_dma;
77
78 return &landisk_bus_dma;
79 }
80
81 void
landisk_pci_attach_hook(struct device * parent,struct device * self,struct pcibus_attach_args * pba)82 landisk_pci_attach_hook(struct device *parent, struct device *self,
83 struct pcibus_attach_args *pba)
84 {
85 /* Nothing to do */
86 }
87
88 int
landisk_pci_intr_map(struct pci_attach_args * pa,pci_intr_handle_t * ihp)89 landisk_pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp)
90 {
91 int pin = pa->pa_intrpin;
92 int line = pa->pa_intrline;
93
94 {
95 /* HACK */
96 int dev = pa->pa_device;
97 static const int irq[4] = { 5, 6, 7, 8 };
98
99 if ((dev >= 0 && dev <= 3) && (pin >= 1 && pin <= 4))
100 line = irq[(dev + pin - 1) & 3];
101 }
102
103 if (pin == 0) {
104 /* No IRQ used. */
105 goto bad;
106 }
107
108 if (pin > 4) {
109 printf("pci_intr_map: bad interrupt pin %d\n", pin);
110 goto bad;
111 }
112
113 if (line == 0 || line == 255) {
114 printf("pci_intr_map: no mapping for pin %c\n", '@' + pin);
115 goto bad;
116 }
117
118 *ihp = line;
119 return 0;
120
121 bad:
122 *ihp = -1;
123 return 1;
124 }
125
126 const char *
landisk_pci_intr_string(void * v,pci_intr_handle_t ih)127 landisk_pci_intr_string(void *v, pci_intr_handle_t ih)
128 {
129 static char irqstr[8]; /* 4 + 2 + NULL + sanity */
130
131 if (ih == 0)
132 panic("pci_intr_string: bogus handle 0x%x", ih);
133
134 snprintf(irqstr, sizeof irqstr, "irq %d", ih);
135
136 return (irqstr);
137 }
138
139 void *
landisk_pci_intr_establish(void * v,pci_intr_handle_t ih,int level,int (* ih_fun)(void *),void * ih_arg,const char * ih_name)140 landisk_pci_intr_establish(void *v, pci_intr_handle_t ih, int level,
141 int (*ih_fun)(void *), void *ih_arg, const char *ih_name)
142 {
143 if (ih == 0)
144 panic("pci_intr_establish: bogus handle 0x%x", ih);
145
146 return extintr_establish(ih, level, ih_fun, ih_arg, ih_name);
147 }
148
149 void
landisk_pci_intr_disestablish(void * v,void * cookie)150 landisk_pci_intr_disestablish(void *v, void *cookie)
151 {
152 extintr_disestablish(cookie);
153 }
154
155 #if 0
156 void
157 landisk_pci_conf_interrupt(void *v, int bus, int dev, int pin, int swiz,
158 int *iline)
159 {
160 static const int irq[4] = { 5, 6, 7, 8 };
161
162 *iline = -1;
163 if ((dev >= 0 && dev <= 3) && (pin >= 1 && pin <= 4)) {
164 *iline = irq[(dev + pin - 1) & 3];
165 }
166 }
167
168 int
169 landisk_pci_conf_hook(void *v, int bus, int dev, int func, pcireg_t id)
170 {
171
172 return (PCI_CONF_ALL & ~PCI_CONF_MAP_ROM);
173 }
174 #endif
175
176 /*
177 * shpcic bus space
178 */
179 struct _bus_space landisk_pci_bus_io =
180 {
181 .bs_cookie = NULL,
182
183 .bs_map = shpcic_iomem_map,
184 .bs_unmap = shpcic_iomem_unmap,
185 .bs_subregion = shpcic_iomem_subregion,
186
187 .bs_alloc = shpcic_iomem_alloc,
188 .bs_free = shpcic_iomem_free,
189
190 .bs_vaddr = shpcic_iomem_vaddr,
191
192 .bs_r_1 = shpcic_io_read_1,
193 .bs_r_2 = shpcic_io_read_2,
194 .bs_r_4 = shpcic_io_read_4,
195
196 .bs_rm_1 = shpcic_io_read_multi_1,
197 .bs_rm_2 = shpcic_io_read_multi_2,
198 .bs_rm_4 = shpcic_io_read_multi_4,
199
200 .bs_rrm_2 = shpcic_io_read_raw_multi_2,
201 .bs_rrm_4 = shpcic_io_read_raw_multi_4,
202
203 .bs_rr_1 = shpcic_io_read_region_1,
204 .bs_rr_2 = shpcic_io_read_region_2,
205 .bs_rr_4 = shpcic_io_read_region_4,
206
207 .bs_rrr_2 = shpcic_io_read_raw_region_2,
208 .bs_rrr_4 = shpcic_io_read_raw_region_4,
209
210 .bs_w_1 = shpcic_io_write_1,
211 .bs_w_2 = shpcic_io_write_2,
212 .bs_w_4 = shpcic_io_write_4,
213
214 .bs_wm_1 = shpcic_io_write_multi_1,
215 .bs_wm_2 = shpcic_io_write_multi_2,
216 .bs_wm_4 = shpcic_io_write_multi_4,
217
218 .bs_wrm_2 = shpcic_io_write_raw_multi_2,
219 .bs_wrm_4 = shpcic_io_write_raw_multi_4,
220
221 .bs_wr_1 = shpcic_io_write_region_1,
222 .bs_wr_2 = shpcic_io_write_region_2,
223 .bs_wr_4 = shpcic_io_write_region_4,
224
225 .bs_wrr_2 = shpcic_io_write_raw_region_2,
226 .bs_wrr_4 = shpcic_io_write_raw_region_4,
227
228 .bs_sm_1 = shpcic_io_set_multi_1,
229 .bs_sm_2 = shpcic_io_set_multi_2,
230 .bs_sm_4 = shpcic_io_set_multi_4,
231
232 .bs_sr_1 = shpcic_io_set_region_1,
233 .bs_sr_2 = shpcic_io_set_region_2,
234 .bs_sr_4 = shpcic_io_set_region_4,
235
236 .bs_c_1 = shpcic_io_copy_1,
237 .bs_c_2 = shpcic_io_copy_2,
238 .bs_c_4 = shpcic_io_copy_4,
239 };
240
241 struct _bus_space landisk_pci_bus_mem =
242 {
243 .bs_cookie = NULL,
244
245 .bs_map = shpcic_iomem_map,
246 .bs_unmap = shpcic_iomem_unmap,
247 .bs_subregion = shpcic_iomem_subregion,
248
249 .bs_alloc = shpcic_iomem_alloc,
250 .bs_free = shpcic_iomem_free,
251
252 .bs_vaddr = shpcic_iomem_vaddr,
253
254 .bs_r_1 = shpcic_mem_read_1,
255 .bs_r_2 = shpcic_mem_read_2,
256 .bs_r_4 = shpcic_mem_read_4,
257
258 .bs_rm_1 = shpcic_mem_read_multi_1,
259 .bs_rm_2 = shpcic_mem_read_multi_2,
260 .bs_rm_4 = shpcic_mem_read_multi_4,
261
262 .bs_rrm_2 = shpcic_mem_read_raw_multi_2,
263 .bs_rrm_4 = shpcic_mem_read_raw_multi_4,
264
265 .bs_rr_1 = shpcic_mem_read_region_1,
266 .bs_rr_2 = shpcic_mem_read_region_2,
267 .bs_rr_4 = shpcic_mem_read_region_4,
268
269 .bs_rrr_2 = shpcic_mem_read_raw_region_2,
270 .bs_rrr_4 = shpcic_mem_read_raw_region_4,
271
272 .bs_w_1 = shpcic_mem_write_1,
273 .bs_w_2 = shpcic_mem_write_2,
274 .bs_w_4 = shpcic_mem_write_4,
275
276 .bs_wm_1 = shpcic_mem_write_multi_1,
277 .bs_wm_2 = shpcic_mem_write_multi_2,
278 .bs_wm_4 = shpcic_mem_write_multi_4,
279
280 .bs_wrm_2 = shpcic_mem_write_raw_multi_2,
281 .bs_wrm_4 = shpcic_mem_write_raw_multi_4,
282
283 .bs_wr_1 = shpcic_mem_write_region_1,
284 .bs_wr_2 = shpcic_mem_write_region_2,
285 .bs_wr_4 = shpcic_mem_write_region_4,
286
287 .bs_wrr_2 = shpcic_mem_write_raw_region_2,
288 .bs_wrr_4 = shpcic_mem_write_raw_region_4,
289
290 .bs_sm_1 = shpcic_mem_set_multi_1,
291 .bs_sm_2 = shpcic_mem_set_multi_2,
292 .bs_sm_4 = shpcic_mem_set_multi_4,
293
294 .bs_sr_1 = shpcic_mem_set_region_1,
295 .bs_sr_2 = shpcic_mem_set_region_2,
296 .bs_sr_4 = shpcic_mem_set_region_4,
297
298 .bs_c_1 = shpcic_mem_copy_1,
299 .bs_c_2 = shpcic_mem_copy_2,
300 .bs_c_4 = shpcic_mem_copy_4,
301 };
302