xref: /openbsd/sys/dev/pci/ydsreg.h (revision d8f12e49)
1 /*	$OpenBSD: ydsreg.h,v 1.7 2010/09/17 07:55:52 jakemsr Exp $	*/
2 /*	$NetBSD$	*/
3 
4 /*
5  * Copyright (c) 2000, 2001 Kazuki Sakamoto and Minoura Makoto.
6  * All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions and the following disclaimer.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  *
17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27  */
28 
29 /*
30  * YMF724/740/744/754 registers
31  */
32 
33 #ifndef _DEV_PCI_YDSREG_H_
34 #define	_DEV_PCI_YDSREG_H_
35 
36 /*
37  * PCI Config Registers
38  */
39 #define	YDS_PCI_MBA		0x10
40 #define	YDS_PCI_LEGACY		0x40
41 # define YDS_PCI_LEGACY_SBEN	0x0001
42 # define YDS_PCI_LEGACY_FMEN	0x0002
43 # define YDS_PCI_LEGACY_JPEN	0x0004
44 # define YDS_PCI_LEGACY_MEN	0x0008
45 # define YDS_PCI_LEGACY_MIEN	0x0010
46 # define YDS_PCI_LEGACY_IO	0x0020
47 # define YDS_PCI_LEGACY_SDMA0	0x0000
48 # define YDS_PCI_LEGACY_SDMA1	0x0040
49 # define YDS_PCI_LEGACY_SDMA3	0x00c0
50 # define YDS_PCI_LEGACY_SBIRQ5	0x0000
51 # define YDS_PCI_LEGACY_SBIRQ7	0x0100
52 # define YDS_PCI_LEGACY_SBIRQ9	0x0200
53 # define YDS_PCI_LEGACY_SBIRQ10	0x0300
54 # define YDS_PCI_LEGACY_SBIRQ11	0x0400
55 # define YDS_PCI_LEGACY_MPUIRQ5	0x0000
56 # define YDS_PCI_LEGACY_MPUIRQ7	0x0800
57 # define YDS_PCI_LEGACY_MPUIRQ9	0x1000
58 # define YDS_PCI_LEGACY_MPUIRQ10 0x1800
59 # define YDS_PCI_LEGACY_MPUIRQ11 0x2000
60 # define YDS_PCI_LEGACY_SIEN	0x4000
61 # define YDS_PCI_LEGACY_LAD	0x8000
62 
63 # define YDS_PCI_EX_LEGACY_FMIO_388	(0x0000 << 16)
64 # define YDS_PCI_EX_LEGACY_FMIO_398	(0x0001 << 16)
65 # define YDS_PCI_EX_LEGACY_FMIO_3A0	(0x0002 << 16)
66 # define YDS_PCI_EX_LEGACY_FMIO_3A8	(0x0003 << 16)
67 # define YDS_PCI_EX_LEGACY_SBIO_220	(0x0000 << 16)
68 # define YDS_PCI_EX_LEGACY_SBIO_240	(0x0004 << 16)
69 # define YDS_PCI_EX_LEGACY_SBIO_260	(0x0008 << 16)
70 # define YDS_PCI_EX_LEGACY_SBIO_280	(0x000c << 16)
71 # define YDS_PCI_EX_LEGACY_MPUIO_330	(0x0000 << 16)
72 # define YDS_PCI_EX_LEGACY_MPUIO_300	(0x0010 << 16)
73 # define YDS_PCI_EX_LEGACY_MPUIO_332	(0x0020 << 16)
74 # define YDS_PCI_EX_LEGACY_MPUIO_334	(0x0030 << 16)
75 # define YDS_PCI_EX_LEGACY_JSIO_201	(0x0000 << 16)
76 # define YDS_PCI_EX_LEGACY_JSIO_202	(0x0040 << 16)
77 # define YDS_PCI_EX_LEGACY_JSIO_204	(0x0080 << 16)
78 # define YDS_PCI_EX_LEGACY_JSIO_205	(0x00c0 << 16)
79 # define YDS_PCI_EX_LEGACY_MAIM		(0x0100 << 16)
80 # define YDS_PCI_EX_LEGACY_SMOD_PCI	(0x0000 << 16)
81 # define YDS_PCI_EX_LEGACY_SMOD_DISABLE	(0x0800 << 16)
82 # define YDS_PCI_EX_LEGACY_SMOD_DDMA	(0x1000 << 16)
83 # define YDS_PCI_EX_LEGACY_SBVER_3	(0x0000 << 16)
84 # define YDS_PCI_EX_LEGACY_SBVER_2	(0x2000 << 16)
85 # define YDS_PCI_EX_LEGACY_SBVER_1	(0x4000 << 16)
86 # define YDS_PCI_EX_LEGACY_IMOD		(0x8000 << 16)
87 
88 #define	YDS_PCI_DSCTRL		0x48
89 # define YDS_DSCTRL_CRST	0x00000001
90 # define YDS_DSCTRL_WRST	0x00000004
91 
92 #define YDS_PCI_FM_BA		0x60
93 #define YDS_PCI_SB_BA		0x62
94 #define YDS_PCI_MPU_BA		0x64
95 #define YDS_PCI_JS_BA		0x66
96 
97 /*
98  * DS-1 PCI Audio part registers
99  */
100 #define YDS_INTERRUPT_FLAGS	0x0004
101 #define YDS_INTERRUPT_FLAGS_TI	0x0001
102 #define YDS_ACTIVITY		0x0006
103 # define YDS_ACTIVITY_DOCKA	0x0010
104 #define	YDS_GLOBAL_CONTROL	0x0008
105 # define YDS_GLCTRL_HVE		0x0001
106 # define YDS_GLCTRL_HVIE	0x0002
107 
108 #define YDS_GPIO_IIF		0x0050
109 # define YDS_GPIO_GIO0		0x0001
110 # define YDS_GPIO_GIO1		0x0002
111 # define YDS_GPIO_GIO2		0x0004
112 #define YDS_GPIO_IIE		0x0052
113 # define YDS_GPIO_GIE0		0x0001
114 # define YDS_GPIO_GIE1		0x0002
115 # define YDS_GPIO_GIE2		0x0004
116 #define YDS_GPIO_ISTAT		0x0054
117 # define YDS_GPIO_GPI0		0x0001
118 # define YDS_GPIO_GPI1		0x0002
119 # define YDS_GPIO_GPI2		0x0004
120 #define YDS_GPIO_OCTRL		0x0056
121 # define YDS_GPIO_GPO0		0x0001
122 # define YDS_GPIO_GPO1		0x0002
123 # define YDS_GPIO_GPO2		0x0004
124 #define YDS_GPIO_FUNCE		0x0058
125 # define YDS_GPIO_GPC0		0x0001
126 # define YDS_GPIO_GPC1		0x0002
127 # define YDS_GPIO_GPC2		0x0004
128 # define YDS_GPIO_GPE0		0x0010
129 # define YDS_GPIO_GPE1		0x0020
130 # define YDS_GPIO_GPE2		0x0040
131 #define YDS_GPIO_ITYPE		0x005a
132 # define YDS_GPIO_GPT0_LEVEL	0x0000
133 # define YDS_GPIO_GPT0_RISE	0x0001
134 # define YDS_GPIO_GPT0_FALL	0x0002
135 # define YDS_GPIO_GPT0_BOTH	0x0003
136 # define YDS_GPIO_GPT0_MASK	0x0003
137 # define YDS_GPIO_GPT1_LEVEL	0x0004
138 # define YDS_GPIO_GPT1_RISE	0x0005
139 # define YDS_GPIO_GPT1_FALL	0x0006
140 # define YDS_GPIO_GPT1_BOTH	0x0007
141 # define YDS_GPIO_GPT1_MASK	0x0007
142 # define YDS_GPIO_GPT2_LEVEL	0x0000
143 # define YDS_GPIO_GPT2_RISE	0x0010
144 # define YDS_GPIO_GPT2_FALL	0x0020
145 # define YDS_GPIO_GPT2_BOTH	0x0030
146 # define YDS_GPIO_GPT2_MASK	0x0030
147 
148 #define	YDS_GLOBAL_CONTROL	0x0008
149 # define YDS_GLCTRL_HVE		0x0001
150 # define YDS_GLCTRL_HVIE	0x0002
151 
152 #define	AC97_CMD_DATA		0x0060
153 #define	AC97_CMD_ADDR		0x0062
154 # define AC97_ID(id)		((id) << 8)
155 # define AC97_CMD_READ		0x8000
156 # define AC97_CMD_WRITE		0x0000
157 #define	AC97_STAT_DATA1		0x0064
158 #define	AC97_STAT_ADDR1		0x0066
159 #define	AC97_STAT_DATA2		0x0068
160 #define	AC97_STAT_ADDR2		0x006a
161 # define AC97_BUSY		0x8000
162 
163 #define	YDS_LEGACY_OUT_VOLUME	0x0080
164 #define	YDS_DAC_OUT_VOLUME	0x0084
165 #define	YDS_DAC_OUT_VOL_L	0x0084
166 #define	YDS_DAC_OUT_VOL_R	0x0086
167 #define	YDS_ZV_OUT_VOLUME	0x0088
168 #define	YDS_2ND_OUT_VOLUME	0x008C
169 #define	YDS_ADC_OUT_VOLUME	0x0090
170 #define	YDS_LEGACY_REC_VOLUME	0x0094
171 #define	YDS_DAC_REC_VOLUME	0x0098
172 #define	YDS_ZV_REC_VOLUME	0x009C
173 #define	YDS_2ND_REC_VOLUME	0x00A0
174 #define	YDS_ADC_REC_VOLUME	0x00A4
175 #define	YDS_ADC_IN_VOLUME	0x00A8
176 #define	YDS_REC_IN_VOLUME	0x00AC
177 #define	YDS_P44_OUT_VOLUME	0x00B0
178 #define	YDS_P44_REC_VOLUME	0x00B4
179 #define	YDS_SPDIFIN_OUT_VOLUME	0x00B8
180 #define	YDS_SPDIFIN_REC_VOLUME	0x00BC
181 
182 #define	YDS_ADC_SAMPLE_RATE	0x00c0
183 #define	YDS_REC_SAMPLE_RATE	0x00c4
184 #define	YDS_ADC_FORMAT		0x00c8
185 #define	YDS_REC_FORMAT		0x00cc
186 # define YDS_FORMAT_8BIT	0x01
187 # define YDS_FORMAT_STEREO	0x02
188 
189 #define	YDS_STATUS		0x0100
190 # define YDS_STAT_ACT		0x00000001
191 # define YDS_STAT_WORK		0x00000002
192 # define YDS_STAT_TINT		0x00008000
193 # define YDS_STAT_INT		0x80000000
194 #define	YDS_CONTROL_SELECT	0x0104
195 # define YDS_CSEL		0x00000001
196 #define	YDS_MODE		0x0108
197 # define YDS_MODE_ACTV		0x00000001
198 # define YDS_MODE_ACTV2		0x00000002
199 # define YDS_MODE_TOUT		0x00008000
200 # define YDS_MODE_RESET		0x00010000
201 # define YDS_MODE_AC3		0x40000000
202 # define YDS_MODE_MUTE		0x80000000
203 
204 #define	YDS_CONFIG		0x0114
205 # define YDS_DSP_DISABLE	0
206 # define YDS_DSP_SETUP		0x00000001
207 
208 #define	YDS_PLAY_CTRLSIZE	0x0140
209 #define	YDS_REC_CTRLSIZE	0x0144
210 #define	YDS_EFFECT_CTRLSIZE	0x0148
211 #define	YDS_WORK_SIZE		0x014c
212 #define	YDS_MAPOF_REC		0x0150
213 # define YDS_RECSLOT_VALID	0x00000001
214 # define YDS_ADCSLOT_VALID	0x00000002
215 #define	YDS_MAPOF_EFFECT	0x0154
216 # define YDS_DL_VALID		0x00000001
217 # define YDS_DR_VALID		0x00000002
218 # define YDS_EFFECT1_VALID	0x00000004
219 # define YDS_EFFECT2_VALID	0x00000008
220 # define YDS_EFFECT3_VALID	0x00000010
221 
222 #define	YDS_PLAY_CTRLBASE	0x0158
223 #define	YDS_REC_CTRLBASE	0x015c
224 #define	YDS_EFFECT_CTRLBASE	0x0160
225 #define	YDS_WORK_BASE		0x0164
226 
227 #define	YDS_DSP_INSTRAM		0x1000
228 #define	YDS_CTRL_INSTRAM	0x4000
229 
230 typedef enum {
231 	YDS_DS_1,
232 	YDS_DS_1E
233 } yds_dstype_t;
234 
235 #define	AC97_TIMEOUT		1000
236 #define	YDS_WORK_TIMEOUT	250000
237 
238 /* slot control data structures */
239 #define	MAX_PLAY_SLOT_CTRL	64
240 #define	N_PLAY_SLOT_CTRL_BANK	2
241 #define	N_REC_SLOT_CTRL		2
242 #define	N_REC_SLOT_CTRL_BANK	2
243 
244 /*
245  * play slot
246  */
247 union play_slot_table {
248 	u_int32_t numofplay;
249 	u_int32_t slotbase;
250 };
251 
252 struct play_slot_ctrl_bank {
253 	u_int32_t format;
254 #define	PSLT_FORMAT_STEREO	0x00010000
255 #define	PSLT_FORMAT_8BIT	0x80000000
256 #define	PSLT_FORMAT_SRC441	0x10000000
257 #define PSLT_FORMAT_RCH		0x00000001
258 	u_int32_t loopdefault;
259 	u_int32_t pgbase;
260 	u_int32_t pgloop;
261 	u_int32_t pgloopend;
262 	u_int32_t pgloopfrac;
263 	u_int32_t pgdeltaend;
264 	u_int32_t lpfkend;
265 	u_int32_t eggainend;
266 	u_int32_t lchgainend;
267 	u_int32_t rchgainend;
268 	u_int32_t effect1gainend;
269 	u_int32_t effect2gainend;
270 	u_int32_t effect3gainend;
271 	u_int32_t lpfq;
272 	u_int32_t status;
273 #define	PSLT_STATUS_DEND	0x00000001
274 	u_int32_t numofframes;
275 	u_int32_t loopcount;
276 	u_int32_t pgstart;
277 	u_int32_t pgstartfrac;
278 	u_int32_t pgdelta;
279 	u_int32_t lpfk;
280 	u_int32_t eggain;
281 	u_int32_t lchgain;
282 	u_int32_t rchgain;
283 	u_int32_t effect1gain;
284 	u_int32_t effect2gain;
285 	u_int32_t effect3gain;
286 	u_int32_t lpfd1;
287 	u_int32_t lpfd2;
288 };
289 
290 /*
291  * rec slot
292  */
293 struct rec_slot_ctrl_bank {
294 	u_int32_t pgbase;
295 	u_int32_t pgloopendadr;
296 	u_int32_t pgstartadr;
297 	u_int32_t numofloops;
298 };
299 
300 struct rec_slot {
301 	struct rec_slot_ctrl {
302 		struct rec_slot_ctrl_bank bank[N_REC_SLOT_CTRL_BANK];
303 	} ctrl[N_REC_SLOT_CTRL];
304 };
305 
306 /*
307  * effect slot
308  */
309 struct effect_slot_ctrl_bank {
310 	u_int32_t pgbase;
311 	u_int32_t pgloopend;
312 	u_int32_t pgstart;
313 	u_int32_t temp;
314 };
315 
316 #define N_PLAY_SLOTS		2		/* We use only 2 (R and L) */
317 #define	N_PLAY_SLOT_CTRL	2
318 #define WORK_SIZE		0x0400
319 
320 /*
321  * softc
322  */
323 struct yds_dma {
324 	bus_dmamap_t map;
325 	caddr_t addr;			/* VA */
326 	bus_dma_segment_t segs[1];
327 	int nsegs;
328 	size_t size;
329 	struct yds_dma *next;
330 };
331 
332 struct yds_codec_softc {
333 	struct device sc_dev;		/* base device */
334 	struct yds_softc *sc;
335 	int id;
336 	int status_data;
337 	int status_addr;
338 	struct ac97_host_if host_if;
339 	struct ac97_codec_if *codec_if;
340 };
341 
342 struct yds_softc {
343 	struct device		sc_dev;		/* base device */
344 	pci_chipset_tag_t	sc_pc;
345 	pcitag_t		sc_pcitag;
346 	pcireg_t		sc_id;
347 	int			sc_revision;
348 	void			*sc_ih;		/* interrupt vectoring */
349 	bus_space_tag_t		memt;
350 	bus_space_handle_t	memh;
351 	bus_dma_tag_t		sc_dmatag;	/* DMA tag */
352 	u_int			sc_flags;
353 
354 	struct yds_codec_softc	sc_codec[2];	/* Primary/Secondary AC97 */
355 
356 	struct yds_dma		*sc_dmas;	/* List of DMA handles */
357 
358 	/*
359 	 * Play/record status
360 	 */
361 	struct {
362 		void		(*intr)(void *); /* rint/pint */
363 		void		*intr_arg;	/* arg for intr */
364 		u_int	 	offset;		/* filled up to here */
365 		u_int	 	blksize;
366 		u_int	 	factor;		/* byte per sample */
367 		u_int		length;		/* ring buffer length */
368 		struct yds_dma	*dma;		/* DMA handle for ring buf */
369 	} sc_play, sc_rec;
370 
371 	/*
372 	 * DSP control data
373 	 *
374 	 * Work space, play control data table, play slot control data,
375 	 * rec slot control data and effect slot control data are
376 	 * stored in a single memory segment in this order.
377 	 */
378 	struct yds_dma			sc_ctrldata;
379 	/* KVA and offset in buffer of play ctrl data tbl */
380 	u_int32_t			*ptbl;
381 	off_t				ptbloff;
382 	/* KVA and offset in buffer of rec slot ctrl data */
383 	struct rec_slot_ctrl_bank	*rbank;
384 	off_t				rbankoff;
385 	/* Array of KVA pointers and offset of play slot control data */
386 	struct play_slot_ctrl_bank	*pbankp[N_PLAY_SLOT_CTRL_BANK
387 					       *N_PLAY_SLOTS];
388 	off_t				pbankoff;
389 
390 	/*
391 	 * Legacy support
392 	 */
393 	bus_space_tag_t		sc_legacy_iot;
394 	bus_space_handle_t	sc_opl_ioh;
395 	struct device		*sc_mpu;
396 	bus_space_handle_t	sc_mpu_ioh;
397 
398 	/*
399 	 * Suspend/resume support
400 	 */
401 	int			suspend;
402 	int			sc_resume_active;
403 };
404 #define sc_opl_iot	sc_legacy_iot
405 #define sc_mpu_iot	sc_legacy_iot
406 
407 #endif /* _DEV_PCI_YDSREG_H_ */
408