1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_1394_ADAPTERS_HCI1394_OHCI_H 27 #define _SYS_1394_ADAPTERS_HCI1394_OHCI_H 28 29 /* 30 * hci1394_ohci.h 31 * Provides access macros and routines to the OpenHCI HW. 32 */ 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #include <sys/ddi.h> 39 #include <sys/modctl.h> 40 #include <sys/sunddi.h> 41 #include <sys/types.h> 42 #include <sys/note.h> 43 44 #include <sys/1394/adapters/hci1394_def.h> 45 #include <sys/1394/adapters/hci1394_buf.h> 46 47 48 #define OHCI_MAX_SELFID_SIZE 2048 49 #define OHCI_BUSGEN_MAX 0xFF 50 51 52 /* Misc */ 53 #define OHCI_REG_SET 1 /* ddi_regs_map_setup */ 54 #define OHCI_CHIP_RESET_TIME_IN_uSEC ((clock_t)100) /* 100uS */ 55 #define OHCI_BUS_RESET_TIME_IN_uSEC ((clock_t)100000) /* 100mS */ 56 #define OHCI_MAX_COOKIE 16 57 #define OHCI_uS_PER_BUS_CYCLE 125 58 #define OHCI_nS_PER_BUS_CYCLE 125000 59 #define OHCI_BUS_CYCLE_TO_uS(cycles) (cycles * OHCI_uS_PER_BUS_CYCLE) 60 #define OHCI_BUS_CYCLE_TO_nS(cycles) (cycles * OHCI_nS_PER_BUS_CYCLE) 61 #define OHCI_CYCLE_SEC_SHIFT 13 62 #define OHCI_CYCLE_SEC_MASK 0xE000 63 #define OHCI_CYCLE_CNT_MASK 0x1FFF 64 #define OHCI_MAX_CYCLE_CNT 8000 65 #define OHCI_TIMESTAMP_MASK 0xFFFF 66 #define OHCI_REG_ADDR_MASK 0x7FC 67 68 /* OpenHCI Global Swap location in PCI space */ 69 #define OHCI_PCI_HCI_CONTROL_REG ((off_t)0x40) 70 #define OHCI_PCI_GLOBAL_SWAP 0x00000001 71 72 73 /* PHY Register #1 */ 74 #define OHCI_PHY_RHB 0x80 75 #define OHCI_PHY_IBR 0x40 76 #define OHCI_PHY_MAX_GAP 0x3F 77 78 /* PHY Register #4 */ 79 #define OHCI_PHY_EXTND_MASK 0xE0 80 #define OHCI_PHY_EXTND 0xE0 81 82 /* PHY Register #4 */ 83 #define OHCI_PHY_CNTDR 0x40 84 85 /* PHY Register #5 */ 86 #define OHCI_PHY_ISBR 0x40 87 #define OHCI_PHY_LOOP_ERR 0x20 88 #define OHCI_PHY_PWRFAIL_ERR 0x10 89 #define OHCI_PHY_TIMEOUT_ERR 0x08 90 #define OHCI_PHY_PORTEVT_ERR 0x04 91 #define OHCI_PHY_ENBL_ACCEL 0x02 92 #define OHCI_PHY_ENBL_MULTI 0x01 93 94 /* OpenHCI Event Codes. Refer to OHCI 1.0 section 3.1.1 */ 95 #define OHCI_EVT_NO_STATUS 0x0 96 #define OHCI_EVT_LONG_PACKET 0x2 97 #define OHCI_EVT_MISSING_ACK 0x3 98 #define OHCI_EVT_UNDERRUN 0x4 99 #define OHCI_EVT_OVERRUN 0x5 100 #define OHCI_EVT_DESCRIPTOR_READ 0x6 101 #define OHCI_EVT_DATA_READ 0x7 102 #define OHCI_EVT_DATA_WRITE 0x8 103 #define OHCI_EVT_BUS_RESET 0x9 104 #define OHCI_EVT_TIMEOUT 0xA 105 #define OHCI_EVT_TCODE_ERR 0xB 106 #define OHCI_EVT_UNKNOWN 0xE 107 #define OHCI_EVT_FLUSHED 0xF 108 #define OHCI_ACK_COMPLETE 0x11 109 #define OHCI_ACK_PENDING 0x12 110 #define OHCI_ACK_BUSY_X 0x14 111 #define OHCI_ACK_BUSY_A 0x15 112 #define OHCI_ACK_BUSY_B 0x16 113 #define OHCI_ACK_TARDY 0x1B 114 #define OHCI_ACK_CONFLICT_ERROR 0x1C 115 #define OHCI_ACK_DATA_ERROR 0x1D 116 #define OHCI_ACK_TYPE_ERROR 0x1E 117 #define OHCI_ACK_ADDRESS_ERROR 0x1F 118 119 #define OHCI_REG_NODEID_ROOT 0x40000000 120 #define OHCI_REG_BUSOPTIONS_CMC 0x40000000 121 122 /* hci_regs_s.ir_ctxt_regs.ctxt_match */ 123 #define OHCI_MTC_TAG3_MASK 0x80000000 124 #define OHCI_MTC_TAG3_SHIFT 31 125 #define OHCI_MTC_TAG2_MASK 0x40000000 126 #define OHCI_MTC_TAG2_SHIFT 30 127 #define OHCI_MTC_TAG1_MASK 0x20000000 128 #define OHCI_MTC_TAG1_SHIFT 29 129 #define OHCI_MTC_TAG0_MASK 0x10000000 130 #define OHCI_MTC_TAG0_SHIFT 28 131 #define OHCI_MTC_MATCH_MASK 0x07FFF000 132 #define OHCI_MTC_MATCH_SHIFT 12 133 #define OHCI_MTC_SYNC_MASK 0x00000F00 134 #define OHCI_MTC_SYNC_SHIFT 8 135 #define OHCI_MTC_TAG1SY_MASK 0x00000040 136 #define OHCI_MTC_TAG1SY_SHIFT 6 137 #define OHCI_MTC_CHAN_MASK 0x0000003F 138 #define OHCI_MTC_CHAN_SHIFT 0 139 140 /* hci_regs_s.self_id_buflo - See OpenHCI 1.00 section 11.1 */ 141 #define OHCI_SLF_BUF_LO 0xFFFFF800 142 143 /* hci_regs_s.self_id_count - See OpenHCI 1.00 section 11.2 */ 144 #define OHCI_SLFC_ERROR 0x80000000 145 #define OHCI_SLFC_GEN_MASK 0x00FF0000 146 #define OHCI_SLFC_GEN_SHIFT 16 147 #define OHCI_SLFC_NUM_QUADS_MASK 0x00001FFC 148 149 150 /* 151 * hci_regs_s.int_event_* and hci_regs_s.int_mask_* 152 * See OpenHCI 1.00 section 6 153 */ 154 #define OHCI_INTR_REQ_TX_CMPLT 0x00000001 155 #define OHCI_INTR_RESP_TX_CMPLT 0x00000002 156 #define OHCI_INTR_ARRQ 0x00000004 157 #define OHCI_INTR_ARRS 0x00000008 158 #define OHCI_INTR_RQPKT 0x00000010 159 #define OHCI_INTR_RSPKT 0x00000020 160 #define OHCI_INTR_ISOCH_TX 0x00000040 /* RO */ 161 #define OHCI_INTR_ISOCH_RX 0x00000080 /* RO */ 162 #define OHCI_INTR_POST_WR_ERR 0x00000100 163 #define OHCI_INTR_LOCK_RESP_ERR 0x00000200 164 #define OHCI_INTR_SELFID_CMPLT 0x00010000 165 #define OHCI_INTR_BUS_RESET 0x00020000 166 #define OHCI_INTR_PHY 0x00080000 167 #define OHCI_INTR_CYC_SYNCH 0x00100000 168 #define OHCI_INTR_CYC_64_SECS 0x00200000 169 #define OHCI_INTR_CYC_LOST 0x00400000 170 #define OHCI_INTR_CYC_INCONSISTENT 0x00800000 171 #define OHCI_INTR_UNRECOVERABLE_ERR 0x01000000 172 #define OHCI_INTR_CYC_TOO_LONG 0x02000000 173 #define OHCI_INTR_PHY_REG_RCVD 0x04000000 174 #define OHCI_INTR_VENDOR_SPECIFIC 0x40000000 175 #define OHCI_INTR_MASTER_INTR_ENBL 0x80000000 /* int_mask_* only */ 176 177 /* hci_regs_s.fairness_ctrl - See OpenHCI 1.00 section 5.8 */ 178 #define OHCI_FAIR_PRI_REQ 0x000000FF 179 180 /* hci_regs_s.link_ctrl_set/clr - See OpenHCI 1.00 section 5.9 */ 181 #define OHCI_LC_CYC_SRC 0x00400000 182 #define OHCI_LC_CYC_MAST 0x00200000 183 #define OHCI_LC_CTIME_ENBL 0x00100000 184 #define OHCI_LC_RCV_PHY 0x00000400 185 #define OHCI_LC_RCV_SELF 0x00000200 186 #define OHCI_LC_CYC_SYNC 0x00000010 187 188 /* Defines for registers in HCI register space */ 189 /* Note: bits are read/write unless otherwise noted (RO-read only) */ 190 191 /* hci_regs_s.version - See OpenHCI 1.00 section 5.2 */ 192 #define OHCI_VER_GUID_ROM 0x01000000 193 #define OHCI_VER_VERSION_MASK 0x00FF0000 194 #define OHCI_VER_VERSION_SHIFT 16 195 #define OHCI_VER_REVISION_MASK 0x000000FF 196 #define OHCI_VERSION(version) \ 197 ((version & OHCI_VER_VERSION_MASK) >> OHCI_VER_VERSION_SHIFT) 198 #define OHCI_REVISION(revision) \ 199 (revision & OHCI_VER_REVISION_MASK) 200 201 /* hci_regs_s.guid_rom - See OpenHCI 1.00 section 5.3 */ 202 #define OHCI_GROM_ADDR_RESET 0x80000000 /* 1-initiate reset */ 203 #define OHCI_GROM_RD_START 0x02000000 /* 1-start byte read */ 204 #define OHCI_GROM_RD_DATA 0x00FF0000 /* RO */ 205 206 /* hci_regs_s.at_retries - See OpenHCI 1.00 section 5.4 */ 207 #define OHCI_RET_SECLIM_MASK 0xE0000000 /* dual-phase retry */ 208 #define OHCI_RET_SECLIM_SHIFT 29 209 #define OHCI_RET_CYCLLIM_MASK 0xFFFF0000 /* dual-phase retry */ 210 #define OHCI_RET_CYCLLIM_SHIFT 16 211 #define OHCI_RET_MAX_PHYS_RESP_MASK 0x00000F00 /* physical resp rtry */ 212 #define OHCI_RET_MAX_PHYS_RESP_SHIFT 8 213 #define OHCI_RET_MAX_ATRESP_MASK 0x000000F0 /* AT response retry */ 214 #define OHCI_RET_MAX_ATRESP_SHIFT 4 215 #define OHCI_RET_MAX_ATREQ_MASK 0x0000000F /* AT request retry */ 216 #define OHCI_RET_MAX_ATREQ_SHIFT 0 217 218 /* hci_regs_s.csr_ctrl - See OpenHCI 1.00 section 5.5.1 */ 219 #define OHCI_CSR_DONE 0x80000000 /* RO 1-cmp_swap complete */ 220 #define OHCI_CSR_SELECT 0x00000003 221 222 #define OHCI_CSR_SEL_BUS_MGR_ID 0 /* bus manager ID register */ 223 #define OHCI_CSR_SEL_BANDWIDTH_AVAIL 1 /* bandwidth available reg */ 224 #define OHCI_CSR_SEL_CHANS_AVAIL_HI 2 /* channels_available_hi reg */ 225 #define OHCI_CSR_SEL_CHANS_AVAIL_LO 3 /* channels_available_lo reg */ 226 227 /* hci_regs_s.config_rom_hdr - See OpenHCI 1.00 section 5.5.6 */ 228 #define OHCI_CROM_INFO_LEN 0xFF000000 229 #define OHCI_CROM_CRC_LEN 0x00FF0000 230 #define OHCI_CROM_ROM_CRC_VAL 0x0000FFFF 231 232 /* hci_regs_s.bus_options - See OpenHCI 1.00 section 5.5.4 */ 233 #define OHCI_BOPT_IRMC 0x80000000 /* Isoch resrce mgr capable */ 234 #define OHCI_BOPT_CMC 0x40000000 /* cycle master capable */ 235 #define OHCI_BOPT_ISC 0x20000000 /* isochronous data capable */ 236 #define OHCI_BOPT_BMC 0x10000000 /* bus manager capable */ 237 #define OHCI_BOPT_PMC 0x80000000 /* power manager capable */ 238 #define OHCI_BOPT_CYC_CLK_ACC 0x00FF0000 239 #define OHCI_BOPT_MAX_REC 0x0000F000 240 #define OHCI_BOPT_GEN 0x000000C0 241 #define OHCI_BOPT_LINK_SPD 0x00000007 242 243 /* hci_regs_s.guid_hi - See OpenHCI 1.00 section 5.5.5 */ 244 #define OHCI_GUID_NODE_VENDOR_ID 0xFFFFFF00 245 #define OHCI_GUID_CHIP_ID_HI 0x000000FF 246 247 /* hci_regs_s.config_rom_maplo - See OpenHCI 1.00 section 5.5.6 */ 248 #define OHCI_CMAP_ADDR 0xFFFFFF00 /* 1k aligned */ 249 250 /* hci_regs_s.posted_write_addrhi - See OpenHCI 1.00 section 13.2.8.1 */ 251 #define OHCI_POST_SOURCE_ID 0xFFFF0000 252 #define OHCI_POST_OFFSET_HI 0x0000FFFF 253 254 /* hci_regs_s.vendor_id - See OpenHCI 1.00 section 5.2 */ 255 #define OHCI_VEND_ID 0x00FFFFFF 256 #define OHCI_VEND_UNIQUE 0xFF000000 257 258 /* hci_regs_s.hc_ctrl_set/clr - See OpenHCI 1.00 section 5.7 */ 259 #define OHCI_HC_NO_BSWAP 0x40000000 /* 1-big endian,0-little end */ 260 #define OHCI_HC_PROG_PHY_ENBL 0x00800000 /* 1-prog phy capabilities */ 261 #define OHCI_HC_APHY_ENBL 0x00040000 /* 1-Aphy enhancements enbld */ 262 #define OHCI_HC_LPS 0x00080000 /* 1-link pwr on, 0-off */ 263 #define OHCI_HC_POSTWR_ENBL 0x00040000 /* 1-enabled, 0-disabled */ 264 #define OHCI_HC_LINK_ENBL 0x00020000 /* 1-enabled, 0-disabled */ 265 #define OHCI_HC_SOFT_RESET 0x00010000 /* 1-reset in prog, 0-done */ 266 267 /* hci_regs_s.node_id - See OpenHCI 1.00 section 5.10 */ 268 #define OHCI_NDID_IDVALID 0x80000000 269 #define OHCI_NDID_ROOT_MASK 0x40000000 270 #define OHCI_NDID_ROOT_SHIFT 30 271 #define OHCI_NDID_CPS_MASK 0x08000000 272 #define OHCI_NDID_CPS_SHIFT 27 273 #define OHCI_NDID_BUSNUM_MASK 0x0000FFC0 274 #define OHCI_NDID_BUSNUM_SHIFT 6 275 #define OHCI_NDID_NODENUM_MASK 0x0000003F 276 #define OHCI_NDID_NODENUM_SHIFT 0 277 278 /* hci_regs_s.phy_ctrl - See OpenHCI 1.00 section 5.11, 1394-1994 J.4.1 */ 279 #define OHCI_PHYC_RDDONE 0x80000000 280 #define OHCI_PHYC_RDREG 0x00008000 281 #define OHCI_PHYC_WRREG 0x00004000 282 #define OHCI_PHYC_RDADDR_MASK 0x0F000000 283 #define OHCI_PHYC_RDADDR_SHIFT 24 284 #define OHCI_PHYC_RDDATA_MASK 0x00FF0000 285 #define OHCI_PHYC_RDDATA_SHIFT 16 286 #define OHCI_PHYC_REGADDR_MASK 0x00000F00 287 #define OHCI_PHYC_REGADDR_SHIFT 8 288 #define OHCI_PHYC_WRDATA_MASK 0x000000FF 289 #define OHCI_PHYC_WRDATA_SHIFT 0 290 291 /* hci_regs_s.context_ctrl -- several contexts */ 292 #define OHCI_CC_RUN_MASK 0x00008000 293 #define OHCI_CC_RUN_SHIFT 15 294 #define OHCI_CC_WAKE_MASK 0x00001000 295 #define OHCI_CC_WAKE_SHIFT 12 296 #define OHCI_CC_DEAD_MASK 0x00000800 297 #define OHCI_CC_DEAD_SHIFT 11 298 #define OHCI_CC_ACTIVE_MASK 0x00000400 299 #define OHCI_CC_ACTIVE_SHIFT 10 300 301 #define OHCI_CC_SPD_MASK 0x000000E0 302 #define OHCI_CC_SPD_SHIFT 5 303 #define OHCI_CC_EVT_MASK 0x0000001F 304 #define OHCI_CC_EVT_SHIFT 0 305 306 /* hci_regs context_ctrl for IR */ 307 #define OHCI_IRCTL_BFILL_MASK 0x80000000 308 #define OHCI_IRCTL_BFILL_SHIFT 31 309 #define OHCI_IRCTL_IHDR_MASK 0x40000000 310 #define OHCI_IRCTL_IHDR_SHIFT 30 311 #define OHCI_IRCTL_MTC_ENBL_MASK 0x20000000 312 #define OHCI_IRCTL_MTC_ENBL_SHIFT 29 313 #define OHCI_IRCTL_MULTI_MASK 0x10000000 314 #define OHCI_IRCTL_MULTI_SHIFT 28 315 316 /* hci_regs context_ctrl for IT */ 317 #define OHCI_ITCTL_MTC_ENBL_MASK 0x80000000 318 #define OHCI_ITCTL_MTC_ENBL_SHIFT 31 319 #define OHCI_ITCTL_MATCH_MASK 0x7FFF0000 320 #define OHCI_ITCTL_MATCH_SHIFT 16 321 322 323 #define HCI1394_IS_ARRESP(tcode) \ 324 ((tcode == IEEE1394_TCODE_WRITE_RESP) || \ 325 (tcode == IEEE1394_TCODE_READ_QUADLET_RESP) || \ 326 (tcode == IEEE1394_TCODE_READ_BLOCK_RESP) || \ 327 (tcode == IEEE1394_TCODE_LOCK_RESP)) 328 329 #define HCI1394_IS_ARREQ(tcode) \ 330 ((tcode == IEEE1394_TCODE_READ_QUADLET) || \ 331 (tcode == IEEE1394_TCODE_WRITE_QUADLET) || \ 332 (tcode == IEEE1394_TCODE_READ_BLOCK) || \ 333 (tcode == IEEE1394_TCODE_WRITE_BLOCK) || \ 334 (tcode == IEEE1394_TCODE_LOCK) || \ 335 (tcode == IEEE1394_TCODE_PHY)) 336 337 #define HCI1394_IRCTXT_CTRL_SET(HCIP, I, BFFILL, IHDR, MATCHENBL, MULTI, RUN, \ 338 WAKE) (ddi_put32((HCIP)->ohci->ohci_reg_handle, \ 339 &(HCIP)->ohci->ohci_regs->ir[(I)].ctxt_ctrl_set, \ 340 0 | (((BFFILL) << OHCI_IRCTL_BFILL_SHIFT) & OHCI_IRCTL_BFILL_MASK) | \ 341 (((IHDR) << OHCI_IRCTL_IHDR_SHIFT) & OHCI_IRCTL_IHDR_MASK) | \ 342 (((MATCHENBL) << OHCI_IRCTL_MTC_ENBL_SHIFT) & \ 343 OHCI_IRCTL_MTC_ENBL_MASK) | \ 344 (((MULTI) << OHCI_IRCTL_MULTI_SHIFT) & OHCI_IRCTL_MULTI_MASK) | \ 345 (((RUN) << OHCI_CC_RUN_SHIFT) & OHCI_CC_RUN_MASK) | \ 346 (((WAKE) << OHCI_CC_WAKE_SHIFT) & OHCI_CC_WAKE_MASK))) 347 348 #define HCI1394_IRCTXT_CTRL_CLR(HCIP, I, BFFILL, IHDR, MATCHENBL, MULTI, RUN) \ 349 (ddi_put32((HCIP)->ohci->ohci_reg_handle, \ 350 &(HCIP)->ohci->ohci_regs->ir[(I)].ctxt_ctrl_clr, \ 351 0 | (((BFFILL) << OHCI_IRCTL_BFILL_SHIFT) & OHCI_IRCTL_BFILL_MASK) | \ 352 (((IHDR) << OHCI_IRCTL_IHDR_SHIFT) & OHCI_IRCTL_IHDR_MASK) | \ 353 (((MATCHENBL) << OHCI_IRCTL_MTC_ENBL_SHIFT) & \ 354 OHCI_IRCTL_MTC_ENBL_MASK) | \ 355 (((MULTI) << OHCI_IRCTL_MULTI_SHIFT) & OHCI_IRCTL_MULTI_MASK) | \ 356 (((RUN) << OHCI_CC_RUN_SHIFT) & OHCI_CC_RUN_MASK))) 357 358 #define HCI1394_ITCTXT_CTRL_SET(HCIP, I, MATCHENBL, MATCH, RUN, WAKE) \ 359 (ddi_put32((HCIP)->ohci->ohci_reg_handle, \ 360 &(HCIP)->ohci->ohci_regs->it[(I)].ctxt_ctrl_set, 0 | \ 361 (((MATCHENBL) << OHCI_ITCTL_MTC_ENBL_SHIFT) & \ 362 OHCI_ITCTL_MTC_ENBL_MASK) | \ 363 (((MATCH) << OHCI_ITCTL_MATCH_SHIFT) & OHCI_ITCTL_MATCH_MASK) | \ 364 (((RUN) << OHCI_CC_RUN_SHIFT) & OHCI_CC_RUN_MASK) | \ 365 (((WAKE) << OHCI_CC_WAKE_SHIFT) & OHCI_CC_WAKE_MASK))) 366 367 #define HCI1394_ITCTXT_CTRL_CLR(HCIP, I, MATCHENBL, MATCH, RUN) \ 368 (ddi_put32((HCIP)->ohci->ohci_reg_handle, \ 369 &(HCIP)->ohci->ohci_regs->it[(I)].ctxt_ctrl_clr, 0 | \ 370 (((MATCHENBL) << OHCI_ITCTL_MTC_ENBL_SHIFT) & \ 371 OHCI_ITCTL_MTC_ENBL_MASK) | \ 372 (((MATCH) << OHCI_ITCTL_MATCH_SHIFT) & OHCI_ITCTL_MATCH_MASK) | \ 373 (((RUN) << OHCI_CC_RUN_SHIFT) & OHCI_CC_RUN_MASK))) 374 375 376 #define HCI1394_IRCTXT_MATCH_WRITE(HCIP, I, TAG3, TAG2, TAG1, TAG0, MATCH, \ 377 SYNC, TAG1SYNC, CHAN) (ddi_put32((HCIP)->ohci->ohci_reg_handle, \ 378 &(HCIP)->ohci->ohci_regs->ir[(I)].ctxt_match, 0 | \ 379 (((TAG3) << OHCI_MTC_TAG3_SHIFT) & OHCI_MTC_TAG3_MASK) | \ 380 (((TAG2) << OHCI_MTC_TAG2_SHIFT) & OHCI_MTC_TAG2_MASK) | \ 381 (((TAG1) << OHCI_MTC_TAG1_SHIFT) & OHCI_MTC_TAG1_MASK) | \ 382 (((TAG0) << OHCI_MTC_TAG0_SHIFT) & OHCI_MTC_TAG0_MASK) | \ 383 (((MATCH) << OHCI_MTC_MATCH_SHIFT) & OHCI_MTC_MATCH_MASK) | \ 384 (((SYNC) << OHCI_MTC_SYNC_SHIFT) & OHCI_MTC_SYNC_MASK) | \ 385 (((TAG1SYNC) << OHCI_MTC_TAG1SY_SHIFT) & OHCI_MTC_TAG1SY_MASK) | \ 386 (((CHAN) << OHCI_MTC_CHAN_SHIFT) & OHCI_MTC_CHAN_MASK))) 387 388 #define HCI1394_ISOCH_CTXT_ACTIVE(SOFTSTATEP, CTXTP) \ 389 (ddi_get32((SOFTSTATEP)->ohci->ohci_reg_handle, \ 390 &(CTXTP)->ctxt_regsp->ctxt_ctrl_set) & OHCI_CC_ACTIVE_MASK) 391 392 #define HCI1394_ISOCH_CTXT_RUN(SOFTSTATEP, CTXTP) \ 393 (ddi_get32((SOFTSTATEP)->ohci->ohci_reg_handle, \ 394 &(CTXTP)->ctxt_regsp->ctxt_ctrl_set) & OHCI_CC_RUN_MASK) 395 396 #define HCI1394_ISOCH_CTXT_CMD_PTR(SOFTSTATEP, CTXTP) \ 397 (ddi_get32((SOFTSTATEP)->ohci->ohci_reg_handle, \ 398 &(CTXTP)->ctxt_regsp->cmd_ptrlo)) 399 400 /* 401 * 1394 OpenHCI 1.0 general context register layout 402 * All contexts except for Isoch Receive have the following layout 403 * See the OpenHCI v1.0 specification for register definitions. 404 */ 405 typedef struct hci1394_ctxt_regs_s { 406 uint32_t ctxt_ctrl_set; 407 uint32_t ctxt_ctrl_clr; 408 uint32_t reserved; 409 uint32_t cmd_ptrlo; 410 } hci1394_ctxt_regs_t; 411 412 /* 413 * 1394 OpenHCI 1.0 Isochronous Receive context register layout 414 * See the OpenHCI v1.0 specification for register definitions. 415 */ 416 typedef struct hci1394_ir_ctxt_regs_s { 417 uint32_t ctxt_ctrl_set; 418 uint32_t ctxt_ctrl_clr; 419 uint32_t reserved0; 420 uint32_t cmd_ptrlo; 421 uint32_t ctxt_match; 422 uint32_t reserved1[3]; 423 } hci1394_ir_ctxt_regs_t; 424 425 /* 426 * 1394 OpenHCI 1.0 registers 427 * See the OpenHCI v1.0 specification for register definitions. 428 */ 429 typedef struct hci1394_regs_s { 430 uint32_t version; 431 uint32_t guid_rom; 432 uint32_t at_retries; 433 uint32_t csr_data; 434 uint32_t csr_compare_data; 435 uint32_t csr_ctrl; 436 uint32_t config_rom_hdr; 437 uint32_t bus_id; 438 uint32_t bus_options; 439 uint32_t guid_hi; 440 uint32_t guid_lo; 441 uint32_t reserved01; 442 uint32_t reserved02; 443 uint32_t config_rom_maplo; 444 uint32_t posted_write_addrlo; 445 uint32_t posted_write_addrhi; 446 uint32_t vendor_id; 447 uint32_t reserved03[3]; 448 uint32_t hc_ctrl_set; 449 uint32_t hc_ctrl_clr; 450 uint32_t reserved06[2]; 451 uint32_t reserved08; 452 uint32_t self_id_buflo; 453 uint32_t self_id_count; 454 uint32_t reserved09; 455 uint32_t ir_multi_maskhi_set; 456 uint32_t ir_multi_maskhi_clr; 457 uint32_t ir_multi_masklo_set; 458 uint32_t ir_multi_masklo_clr; 459 uint32_t intr_event_set; 460 uint32_t intr_event_clr; 461 uint32_t intr_mask_set; 462 uint32_t intr_mask_clr; 463 uint32_t it_intr_event_set; 464 uint32_t it_intr_event_clr; 465 uint32_t it_intr_mask_set; 466 uint32_t it_intr_mask_clr; 467 uint32_t ir_intr_event_set; 468 uint32_t ir_intr_event_clr; 469 uint32_t ir_intr_mask_set; 470 uint32_t ir_intr_mask_clr; 471 uint32_t reserved10[11]; 472 uint32_t fairness_ctrl; 473 uint32_t link_ctrl_set; 474 uint32_t link_ctrl_clr; 475 uint32_t node_id; 476 uint32_t phy_ctrl; 477 uint32_t isoch_cycle_timer; 478 uint32_t reserved21[3]; 479 uint32_t ar_req_filterhi_set; 480 uint32_t ar_req_filterhi_clr; 481 uint32_t ar_req_filterlo_set; 482 uint32_t ar_req_filterlo_clr; 483 uint32_t phys_req_filterhi_set; 484 uint32_t phys_req_filterhi_clr; 485 uint32_t phys_req_filterlo_set; 486 uint32_t phys_req_filterlo_clr; 487 uint32_t phys_upper_bound; 488 uint32_t reserved24[23]; 489 hci1394_ctxt_regs_t at_req; 490 uint32_t reserved47[4]; 491 hci1394_ctxt_regs_t at_resp; 492 uint32_t reserved51[4]; 493 hci1394_ctxt_regs_t ar_req; 494 uint32_t reserved55[4]; 495 hci1394_ctxt_regs_t ar_resp; 496 uint32_t reserved59[4]; 497 hci1394_ctxt_regs_t it[HCI1394_MAX_ISOCH_CONTEXTS]; 498 hci1394_ir_ctxt_regs_t ir[HCI1394_MAX_ISOCH_CONTEXTS]; 499 } hci1394_regs_t; 500 501 502 /* private structure to keep track of OpenHCI */ 503 typedef struct hci1394_ohci_s { 504 /* config ROM and selfid buffers */ 505 hci1394_buf_handle_t ohci_cfgrom_handle; 506 hci1394_buf_handle_t ohci_selfid_handle; 507 508 /* 509 * Phy register #1 cached settings. These are only used for 1394-1995 510 * phy's. When setting the root holdoff bit and gap count in 1394, 511 * you send out a PHY configuration packet. The 1995 PHY's will 512 * not look at the PHY packet if we sent it out which means we have 513 * to write directly to PHY register 1. This creates some ugly race 514 * conditions. Since we will be following up these settings with a bus 515 * reset shortly, we "cache" them until we generate the bus reset. This 516 * solution is not perfect, but it is the best of a bad thing. 517 */ 518 boolean_t ohci_set_root_holdoff; 519 boolean_t ohci_set_gap_count; 520 uint_t ohci_gap_count; 521 522 /* 523 * The bus time is kept using the cycle timer and then counting the 524 * rollovers via the cycle 64 seconds interrupt. (NOTE: every 2 525 * interrupts is one rollover) We do not wish to be interrupting 526 * the CPU if there is nothing plugged into the bus (since bus time 527 * really isn't used for anything yet (maybe when bridges come out?)). 528 * We will start with the interrupt disabled, if the bus master writes 529 * to the CSR bus time register, we will enable the interrupt. These 530 * fields keep track of the rollover and whether or not the interrupt 531 * is enabled. 532 */ 533 volatile uint_t ohci_bustime_count; 534 boolean_t ohci_bustime_enabled; 535 536 /* whether we have a 1394-1995 or 1394A phy */ 537 h1394_phy_t ohci_phy; 538 539 /* General Driver Info */ 540 hci1394_drvinfo_t *ohci_drvinfo; 541 542 /* 543 * self id buffer and config rom info. These are towards bottom of the 544 * structure to make debugging easier. 545 */ 546 hci1394_buf_info_t ohci_selfid; 547 hci1394_buf_info_t ohci_cfgrom; 548 549 /* OpenHCI registers */ 550 ddi_acc_handle_t ohci_reg_handle; 551 hci1394_regs_t *ohci_regs; 552 553 /* 554 * This mutex is used to protect "atomic" operations to the OpenHCI 555 * hardware. This includes reads and writes to the PHY, cswap 556 * operations to the HW implemented CSR registers, and any read/modify/ 557 * write operations such as updating atreq retries. 558 */ 559 kmutex_t ohci_mutex; 560 561 hci1394_state_t *soft_state; 562 } hci1394_ohci_t; 563 564 _NOTE(SCHEME_PROTECTS_DATA("Single thread modifies", \ 565 hci1394_ohci_s::ohci_bustime_count \ 566 hci1394_ohci_s::ohci_bustime_enabled \ 567 hci1394_ohci_s::ohci_gap_count \ 568 hci1394_ohci_s::ohci_set_gap_count \ 569 hci1394_ohci_s::ohci_set_root_holdoff)) 570 571 /* handle passed back from init() and used for rest of functions */ 572 typedef hci1394_ohci_t *hci1394_ohci_handle_t; 573 574 575 int hci1394_ohci_init(hci1394_state_t *soft_state, hci1394_drvinfo_t *drvinfo, 576 hci1394_ohci_handle_t *ohci_hdl); 577 void hci1394_ohci_fini(hci1394_ohci_handle_t *ohci_hdl); 578 579 void hci1394_ohci_reg_read(hci1394_ohci_handle_t ohci_hdl, uint_t offset, 580 uint32_t *data); 581 void hci1394_ohci_reg_write(hci1394_ohci_handle_t ohci_hdl, uint_t offset, 582 uint32_t data); 583 int hci1394_ohci_phy_init(hci1394_ohci_handle_t ohci_hdl); 584 int hci1394_ohci_phy_set(hci1394_ohci_handle_t ohci_hdl, uint_t regAddr, 585 uint_t bits); 586 int hci1394_ohci_phy_clr(hci1394_ohci_handle_t ohci_hdl, uint_t regAddr, 587 uint_t bits); 588 int hci1394_ohci_phy_read(hci1394_ohci_handle_t ohci_hdl, uint_t regAddr, 589 uint_t *rdData); 590 int hci1394_ohci_phy_write(hci1394_ohci_handle_t ohci_hdl, uint_t regAddr, 591 uint_t wrData); 592 int hci1394_ohci_phy_info(hci1394_ohci_handle_t ohci_hdl, uint32_t *info); 593 void hci1394_ohci_intr_master_enable(hci1394_ohci_handle_t ohci_hdl); 594 void hci1394_ohci_intr_master_disable(hci1394_ohci_handle_t ohci_hdl); 595 uint32_t hci1394_ohci_intr_asserted(hci1394_ohci_handle_t ohci_hdl); 596 void hci1394_ohci_intr_enable(hci1394_ohci_handle_t ohci_hdl, 597 uint32_t intr_mask); 598 void hci1394_ohci_intr_disable(hci1394_ohci_handle_t ohci_hdl, 599 uint32_t intr_mask); 600 void hci1394_ohci_intr_clear(hci1394_ohci_handle_t ohci_hdl, 601 uint32_t intr_mask); 602 uint32_t hci1394_ohci_it_intr_asserted(hci1394_ohci_handle_t ohci_hdl); 603 void hci1394_ohci_it_intr_enable(hci1394_ohci_handle_t ohci_hdl, 604 uint32_t intr_mask); 605 void hci1394_ohci_it_intr_disable(hci1394_ohci_handle_t ohci_hdl, 606 uint32_t intr_mask); 607 void hci1394_ohci_it_intr_clear(hci1394_ohci_handle_t ohci_hdl, 608 uint32_t intr_mask); 609 int hci1394_ohci_it_ctxt_count_get(hci1394_ohci_handle_t ohci_hdl); 610 void hci1394_ohci_it_cmd_ptr_set(hci1394_ohci_handle_t ohci_hdl, 611 uint_t context_number, uint32_t io_addr); 612 uint32_t hci1394_ohci_ir_intr_asserted(hci1394_ohci_handle_t ohci_hdl); 613 void hci1394_ohci_ir_intr_enable(hci1394_ohci_handle_t ohci_hdl, 614 uint32_t intr_mask); 615 void hci1394_ohci_ir_intr_disable(hci1394_ohci_handle_t ohci_hdl, 616 uint32_t intr_mask); 617 void hci1394_ohci_ir_intr_clear(hci1394_ohci_handle_t ohci_hdl, 618 uint32_t intr_mask); 619 int hci1394_ohci_ir_ctxt_count_get(hci1394_ohci_handle_t ohci_hdl); 620 void hci1394_ohci_ir_cmd_ptr_set(hci1394_ohci_handle_t ohci_hdl, 621 uint_t context_number, uint32_t io_addr); 622 void hci1394_ohci_link_enable(hci1394_ohci_handle_t ohci_hdl); 623 void hci1394_ohci_link_disable(hci1394_ohci_handle_t ohci_hdl); 624 uint_t hci1394_ohci_current_busgen(hci1394_ohci_handle_t ohci_hdl); 625 int hci1394_ohci_soft_reset(hci1394_ohci_handle_t ohci_hdl); 626 int hci1394_ohci_startup(hci1394_ohci_handle_t ohci_hdl); 627 uint64_t hci1394_ohci_guid(hci1394_ohci_handle_t ohci_hdl); 628 int hci1394_ohci_csr_read(hci1394_ohci_handle_t ohci_hdl, uint_t offset, 629 uint32_t *data); 630 int hci1394_ohci_csr_cswap(hci1394_ohci_handle_t ohci_hdl, uint_t generation, 631 uint_t offset, uint32_t compare, uint32_t swap, uint32_t *old); 632 int hci1394_ohci_bus_reset(hci1394_ohci_handle_t ohci_hdl); 633 int hci1394_ohci_bus_reset_nroot(hci1394_ohci_handle_t ohci_hdl); 634 int hci1394_ohci_bus_reset_short(hci1394_ohci_handle_t ohci_hdl); 635 void hci1394_ohci_postwr_addr(hci1394_ohci_handle_t ohci_hdl, uint64_t *addr); 636 int hci1394_ohci_contender_enable(hci1394_ohci_handle_t ohci_hdl); 637 int hci1394_ohci_root_holdoff_enable(hci1394_ohci_handle_t ohci_hdl); 638 int hci1394_ohci_gap_count_set(hci1394_ohci_handle_t ohci_hdl, 639 uint_t gap_count); 640 int hci1394_ohci_phy_filter_set(hci1394_ohci_handle_t ohci_hdl, 641 uint64_t mask, uint_t generation); 642 int hci1394_ohci_phy_filter_clr(hci1394_ohci_handle_t ohci_hdl, 643 uint64_t mask, uint_t generation); 644 void hci1394_ohci_cfgrom_update(hci1394_ohci_handle_t ohci_hdl, 645 void *local_buf, uint_t quadlet_count); 646 void hci1394_ohci_selfid_enable(hci1394_ohci_handle_t ohci_hdl); 647 void hci1394_ohci_selfid_read(hci1394_ohci_handle_t ohci_hdl, uint_t offset, 648 uint32_t *data); 649 void hci1394_ohci_selfid_info(hci1394_ohci_handle_t ohci_hdl, uint_t *busgen, 650 uint_t *size, boolean_t *error); 651 boolean_t hci1394_ohci_selfid_buf_current(hci1394_ohci_handle_t ohci_hdl); 652 void hci1394_ohci_selfid_sync(hci1394_ohci_handle_t ohci_hdl); 653 void hci1394_ohci_nodeid_set(hci1394_ohci_handle_t ohci_hdl, uint_t nodeid); 654 void hci1394_ohci_nodeid_get(hci1394_ohci_handle_t ohci_hdl, uint_t *nodeid); 655 void hci1394_ohci_nodeid_info(hci1394_ohci_handle_t ohci_hdl, 656 uint_t *nodeid, boolean_t *error); 657 void hci1394_ohci_cycletime_get(hci1394_ohci_handle_t ohci_hdl, 658 uint32_t *cycle_time); 659 void hci1394_ohci_cycletime_set(hci1394_ohci_handle_t ohci_hdl, 660 uint32_t cycle_time); 661 void hci1394_ohci_bustime_get(hci1394_ohci_handle_t ohci_hdl, 662 uint32_t *bus_time); 663 void hci1394_ohci_bustime_set(hci1394_ohci_handle_t ohci_hdl, 664 uint32_t bus_time); 665 void hci1394_ohci_atreq_retries_get(hci1394_ohci_handle_t ohci_hdl, 666 uint_t *atreq_retries); 667 void hci1394_ohci_atreq_retries_set(hci1394_ohci_handle_t ohci_hdl, 668 uint_t atreq_retries); 669 void hci1394_ohci_isr_cycle64seconds(hci1394_ohci_handle_t ohci_hdl); 670 void hci1394_ohci_isr_phy(hci1394_ohci_handle_t ohci_hdl); 671 boolean_t hci1394_ohci_root_check(hci1394_ohci_handle_t ohci_hdl); 672 boolean_t hci1394_ohci_cmc_check(hci1394_ohci_handle_t ohci_hdl); 673 void hci1394_ohci_cycle_master_enable(hci1394_ohci_handle_t ohci_hdl); 674 void hci1394_ohci_cycle_master_disable(hci1394_ohci_handle_t ohci_hdl); 675 int hci1394_ohci_resume(hci1394_ohci_handle_t ohci_hdl); 676 void hci1394_ohci_bus_capabilities(hci1394_ohci_handle_t ohci_hdl, 677 uint32_t *bus_capabilities); 678 boolean_t hci1394_ohci_at_active(hci1394_ohci_handle_t ohci_hdl); 679 void hci1394_ohci_atreq_start(hci1394_ohci_handle_t ohci_hdl, 680 uint32_t cmdptr); 681 void hci1394_ohci_atreq_wake(hci1394_ohci_handle_t ohci_hdl); 682 void hci1394_ohci_atreq_stop(hci1394_ohci_handle_t ohci_hdl); 683 void hci1394_ohci_arresp_start(hci1394_ohci_handle_t ohci_hdl, 684 uint32_t cmdptr); 685 void hci1394_ohci_arresp_wake(hci1394_ohci_handle_t ohci_hdl); 686 void hci1394_ohci_arresp_stop(hci1394_ohci_handle_t ohci_hdl); 687 void hci1394_ohci_arreq_start(hci1394_ohci_handle_t ohci_hdl, 688 uint32_t cmdptr); 689 void hci1394_ohci_arreq_wake(hci1394_ohci_handle_t ohci_hdl); 690 void hci1394_ohci_arreq_stop(hci1394_ohci_handle_t ohci_hdl); 691 void hci1394_ohci_atresp_start(hci1394_ohci_handle_t ohci_hdl, 692 uint32_t cmdptr); 693 void hci1394_ohci_atresp_wake(hci1394_ohci_handle_t ohci_hdl); 694 void hci1394_ohci_atresp_stop(hci1394_ohci_handle_t ohci_hdl); 695 696 697 #ifdef __cplusplus 698 } 699 #endif 700 701 #endif /* _SYS_1394_ADAPTERS_HCI1394_OHCI_H */ 702