1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
3 *
4 * Copyright (c) 2015-2023 Amazon.com, Inc. or its affiliates.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
16 * distribution.
17 * * Neither the name of copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef ENA_COM
35 #define ENA_COM
36
37 #include "ena_plat.h"
38
39 #define ENA_MAX_NUM_IO_QUEUES 128U
40 /* We need to queues for each IO (on for Tx and one for Rx) */
41 #define ENA_TOTAL_NUM_QUEUES (2 * (ENA_MAX_NUM_IO_QUEUES))
42
43 #define ENA_MAX_HANDLERS 256
44
45 #define ENA_MAX_PHYS_ADDR_SIZE_BITS 48
46
47 /* Unit in usec */
48 #define ENA_REG_READ_TIMEOUT 200000
49
50 #define ADMIN_SQ_SIZE(depth) ((depth) * sizeof(struct ena_admin_aq_entry))
51 #define ADMIN_CQ_SIZE(depth) ((depth) * sizeof(struct ena_admin_acq_entry))
52 #define ADMIN_AENQ_SIZE(depth) ((depth) * sizeof(struct ena_admin_aenq_entry))
53
54 #define ENA_CUSTOMER_METRICS_BUFFER_SIZE 512
55
56 /*****************************************************************************/
57 /*****************************************************************************/
58 /* ENA adaptive interrupt moderation settings */
59
60 #define ENA_INTR_INITIAL_TX_INTERVAL_USECS ENA_INTR_INITIAL_TX_INTERVAL_USECS_PLAT
61 #define ENA_INTR_INITIAL_RX_INTERVAL_USECS ENA_INTR_INITIAL_RX_INTERVAL_USECS_PLAT
62 #define ENA_DEFAULT_INTR_DELAY_RESOLUTION 1
63
64 #define ENA_HASH_KEY_SIZE 40
65
66 #define ENA_HW_HINTS_NO_TIMEOUT 0xFFFF
67
68 #define ENA_FEATURE_MAX_QUEUE_EXT_VER 1
69
70 struct ena_llq_configurations {
71 enum ena_admin_llq_header_location llq_header_location;
72 enum ena_admin_llq_ring_entry_size llq_ring_entry_size;
73 enum ena_admin_llq_stride_ctrl llq_stride_ctrl;
74 enum ena_admin_llq_num_descs_before_header llq_num_decs_before_header;
75 u16 llq_ring_entry_size_value;
76 };
77
78 enum queue_direction {
79 ENA_COM_IO_QUEUE_DIRECTION_TX,
80 ENA_COM_IO_QUEUE_DIRECTION_RX
81 };
82
83 struct ena_com_buf {
84 dma_addr_t paddr; /**< Buffer physical address */
85 u16 len; /**< Buffer length in bytes */
86 };
87
88 struct ena_com_rx_buf_info {
89 u16 len;
90 u16 req_id;
91 };
92
93 struct ena_com_io_desc_addr {
94 u8 __iomem *pbuf_dev_addr; /* LLQ address */
95 u8 *virt_addr;
96 dma_addr_t phys_addr;
97 ena_mem_handle_t mem_handle;
98 };
99
100 struct ena_com_tx_meta {
101 u16 mss;
102 u16 l3_hdr_len;
103 u16 l3_hdr_offset;
104 u16 l4_hdr_len; /* In words */
105 };
106
107 struct ena_com_llq_info {
108 u16 header_location_ctrl;
109 u16 desc_stride_ctrl;
110 u16 desc_list_entry_size_ctrl;
111 u16 desc_list_entry_size;
112 u16 descs_num_before_header;
113 u16 descs_per_entry;
114 u16 max_entries_in_tx_burst;
115 bool disable_meta_caching;
116 };
117
118 struct ena_com_io_cq {
119 struct ena_com_io_desc_addr cdesc_addr;
120 void *bus;
121
122 /* Interrupt unmask register */
123 u32 __iomem *unmask_reg;
124
125
126 /* numa configuration register (for TPH) */
127 u32 __iomem *numa_node_cfg_reg;
128
129 /* The value to write to the above register to unmask
130 * the interrupt of this queue
131 */
132 u32 msix_vector ____cacheline_aligned;
133
134 enum queue_direction direction;
135
136 /* holds the number of cdesc of the current packet */
137 u16 cur_rx_pkt_cdesc_count;
138 /* save the first cdesc idx of the current packet */
139 u16 cur_rx_pkt_cdesc_start_idx;
140
141 u16 q_depth;
142 /* Caller qid */
143 u16 qid;
144
145 /* Device queue index */
146 u16 idx;
147 u16 head;
148 u8 phase;
149 u8 cdesc_entry_size_in_bytes;
150
151 } ____cacheline_aligned;
152
153 struct ena_com_io_bounce_buffer_control {
154 u8 *base_buffer;
155 u16 next_to_use;
156 u16 buffer_size;
157 u16 buffers_num; /* Must be a power of 2 */
158 };
159
160 /* This struct is to keep tracking the current location of the next llq entry */
161 struct ena_com_llq_pkt_ctrl {
162 u8 *curr_bounce_buf;
163 u16 idx;
164 u16 descs_left_in_line;
165 };
166
167 struct ena_com_io_sq {
168 struct ena_com_io_desc_addr desc_addr;
169 void *bus;
170
171 u32 __iomem *db_addr;
172
173 enum queue_direction direction;
174 enum ena_admin_placement_policy_type mem_queue_type;
175
176 bool disable_meta_caching;
177
178 u32 msix_vector;
179 struct ena_com_tx_meta cached_tx_meta;
180 struct ena_com_llq_info llq_info;
181 struct ena_com_llq_pkt_ctrl llq_buf_ctrl;
182 struct ena_com_io_bounce_buffer_control bounce_buf_ctrl;
183
184 u16 q_depth;
185 u16 qid;
186
187 u16 idx;
188 u16 tail;
189 u16 next_to_comp;
190 u16 llq_last_copy_tail;
191 u32 tx_max_header_size;
192 u8 phase;
193 u8 desc_entry_size;
194 u8 dma_addr_bits;
195 u16 entries_in_tx_burst_left;
196 } ____cacheline_aligned;
197
198 struct ena_com_admin_cq {
199 struct ena_admin_acq_entry *entries;
200 ena_mem_handle_t mem_handle;
201 dma_addr_t dma_addr;
202
203 u16 head;
204 u8 phase;
205 };
206
207 struct ena_com_admin_sq {
208 struct ena_admin_aq_entry *entries;
209 ena_mem_handle_t mem_handle;
210 dma_addr_t dma_addr;
211
212 u32 __iomem *db_addr;
213
214 u16 head;
215 u16 tail;
216 u8 phase;
217
218 };
219
220 struct ena_com_stats_admin {
221 u64 aborted_cmd;
222 u64 submitted_cmd;
223 u64 completed_cmd;
224 u64 out_of_space;
225 u64 no_completion;
226 };
227
228 struct ena_com_stats_phc {
229 u64 phc_cnt;
230 u64 phc_exp;
231 u64 phc_skp;
232 u64 phc_err;
233 };
234
235 struct ena_com_admin_queue {
236 void *q_dmadev;
237 void *bus;
238 struct ena_com_dev *ena_dev;
239 ena_spinlock_t q_lock; /* spinlock for the admin queue */
240
241 struct ena_comp_ctx *comp_ctx;
242 u32 completion_timeout;
243 u16 q_depth;
244 struct ena_com_admin_cq cq;
245 struct ena_com_admin_sq sq;
246
247 /* Indicate if the admin queue should poll for completion */
248 bool polling;
249
250 /* Define if fallback to polling mode should occur */
251 bool auto_polling;
252
253 u16 curr_cmd_id;
254
255 /* Indicate that the ena was initialized and can
256 * process new admin commands
257 */
258 bool running_state;
259
260 /* Count the number of outstanding admin commands */
261 ena_atomic32_t outstanding_cmds;
262
263 struct ena_com_stats_admin stats;
264 };
265
266 struct ena_aenq_handlers;
267
268 struct ena_com_aenq {
269 u16 head;
270 u8 phase;
271 struct ena_admin_aenq_entry *entries;
272 dma_addr_t dma_addr;
273 ena_mem_handle_t mem_handle;
274 u16 q_depth;
275 struct ena_aenq_handlers *aenq_handlers;
276 };
277
278 struct ena_com_mmio_read {
279 struct ena_admin_ena_mmio_req_read_less_resp *read_resp;
280 dma_addr_t read_resp_dma_addr;
281 ena_mem_handle_t read_resp_mem_handle;
282 u32 reg_read_to; /* in us */
283 u16 seq_num;
284 bool readless_supported;
285 /* spin lock to ensure a single outstanding read */
286 ena_spinlock_t lock;
287 };
288
289 /* PTP hardware clock (PHC) MMIO read data info */
290 struct ena_com_phc_info {
291 /* Internal PHC statistics */
292 struct ena_com_stats_phc stats;
293
294 /* PHC shared memory - virtual address */
295 struct ena_admin_phc_resp *virt_addr;
296
297 /* Spin lock to ensure a single outstanding PHC read */
298 ena_spinlock_t lock;
299
300 /* PHC doorbell address as an offset to PCIe MMIO REG BAR */
301 u32 doorbell_offset;
302
303 /* Shared memory read expire timeout (usec)
304 * Max time for valid PHC retrieval, passing this threshold will fail the get time request
305 * and block new PHC requests for block_timeout_usec in order to prevent floods on busy
306 * device
307 */
308 u32 expire_timeout_usec;
309
310 /* Shared memory read abort timeout (usec)
311 * PHC requests block period, blocking starts once PHC request expired in order to prevent
312 * floods on busy device, any PHC requests during block period will be skipped
313 */
314 u32 block_timeout_usec;
315
316 /* Request id sent to the device */
317 u16 req_id;
318
319 /* True if PHC is active in the device */
320 bool active;
321
322 /* PHC shared memory - memory handle */
323 ena_mem_handle_t mem_handle;
324
325 /* PHC shared memory - physical address */
326 dma_addr_t phys_addr;
327 };
328
329 struct ena_rss {
330 /* Indirect table */
331 u16 *host_rss_ind_tbl;
332 struct ena_admin_rss_ind_table_entry *rss_ind_tbl;
333 dma_addr_t rss_ind_tbl_dma_addr;
334 ena_mem_handle_t rss_ind_tbl_mem_handle;
335 u16 tbl_log_size;
336
337 /* Hash key */
338 enum ena_admin_hash_functions hash_func;
339 struct ena_admin_feature_rss_flow_hash_control *hash_key;
340 dma_addr_t hash_key_dma_addr;
341 ena_mem_handle_t hash_key_mem_handle;
342 u32 hash_init_val;
343
344 /* Flow Control */
345 struct ena_admin_feature_rss_hash_control *hash_ctrl;
346 dma_addr_t hash_ctrl_dma_addr;
347 ena_mem_handle_t hash_ctrl_mem_handle;
348
349 };
350
351 struct ena_customer_metrics {
352 /* in correlation with ENA_ADMIN_CUSTOMER_METRICS_SUPPORT_MASK
353 * and ena_admin_customer_metrics_id
354 */
355 uint64_t supported_metrics;
356 dma_addr_t buffer_dma_addr;
357 void *buffer_virt_addr;
358 ena_mem_handle_t buffer_dma_handle;
359 u32 buffer_len;
360 };
361
362 struct ena_host_attribute {
363 /* Debug area */
364 u8 *debug_area_virt_addr;
365 dma_addr_t debug_area_dma_addr;
366 ena_mem_handle_t debug_area_dma_handle;
367 u32 debug_area_size;
368
369 /* Host information */
370 struct ena_admin_host_info *host_info;
371 dma_addr_t host_info_dma_addr;
372 ena_mem_handle_t host_info_dma_handle;
373 };
374
375 /* Each ena_dev is a PCI function. */
376 struct ena_com_dev {
377 struct ena_com_admin_queue admin_queue;
378 struct ena_com_aenq aenq;
379 struct ena_com_io_cq io_cq_queues[ENA_TOTAL_NUM_QUEUES];
380 struct ena_com_io_sq io_sq_queues[ENA_TOTAL_NUM_QUEUES];
381 u8 __iomem *reg_bar;
382 void __iomem *mem_bar;
383 void *dmadev;
384 void *bus;
385 ena_netdev *net_device;
386
387 enum ena_admin_placement_policy_type tx_mem_queue_type;
388 u32 tx_max_header_size;
389 u16 stats_func; /* Selected function for extended statistic dump */
390 u16 stats_queue; /* Selected queue for extended statistic dump */
391
392 u32 ena_min_poll_delay_us;
393
394 struct ena_com_mmio_read mmio_read;
395 struct ena_com_phc_info phc;
396
397 struct ena_rss rss;
398 u32 supported_features;
399 u32 capabilities;
400 u32 dma_addr_bits;
401
402 struct ena_host_attribute host_attr;
403 bool adaptive_coalescing;
404 u16 intr_delay_resolution;
405
406 /* interrupt moderation intervals are in usec divided by
407 * intr_delay_resolution, which is supplied by the device.
408 */
409 u32 intr_moder_tx_interval;
410 u32 intr_moder_rx_interval;
411
412 struct ena_intr_moder_entry *intr_moder_tbl;
413
414 struct ena_com_llq_info llq_info;
415
416 struct ena_customer_metrics customer_metrics;
417 };
418
419 struct ena_com_dev_get_features_ctx {
420 struct ena_admin_queue_feature_desc max_queues;
421 struct ena_admin_queue_ext_feature_desc max_queue_ext;
422 struct ena_admin_device_attr_feature_desc dev_attr;
423 struct ena_admin_feature_aenq_desc aenq;
424 struct ena_admin_feature_offload_desc offload;
425 struct ena_admin_ena_hw_hints hw_hints;
426 struct ena_admin_feature_llq_desc llq;
427 };
428
429 struct ena_com_create_io_ctx {
430 enum ena_admin_placement_policy_type mem_queue_type;
431 enum queue_direction direction;
432 int numa_node;
433 u32 msix_vector;
434 u16 queue_size;
435 u16 qid;
436 };
437
438 typedef void (*ena_aenq_handler)(void *data,
439 struct ena_admin_aenq_entry *aenq_e);
440
441 /* Holds aenq handlers. Indexed by AENQ event group */
442 struct ena_aenq_handlers {
443 ena_aenq_handler handlers[ENA_MAX_HANDLERS];
444 ena_aenq_handler unimplemented_handler;
445 };
446
447 /*****************************************************************************/
448 /*****************************************************************************/
449 #if defined(__cplusplus)
450 extern "C" {
451 #endif
452
453 /* ena_com_mmio_reg_read_request_init - Init the mmio reg read mechanism
454 * @ena_dev: ENA communication layer struct
455 *
456 * Initialize the register read mechanism.
457 *
458 * @note: This method must be the first stage in the initialization sequence.
459 *
460 * @return - 0 on success, negative value on failure.
461 */
462 int ena_com_mmio_reg_read_request_init(struct ena_com_dev *ena_dev);
463
464 /* ena_com_phc_init - Allocate and initialize PHC feature
465 * @ena_dev: ENA communication layer struct
466 * @note: This method assumes PHC is supported by the device
467 * @return - 0 on success, negative value on failure
468 */
469 int ena_com_phc_init(struct ena_com_dev *ena_dev);
470
471 /* ena_com_phc_supported - Return if PHC feature is supported by the device
472 * @ena_dev: ENA communication layer struct
473 * @note: This method must be called after getting supported features
474 * @return - supported or not
475 */
476 bool ena_com_phc_supported(struct ena_com_dev *ena_dev);
477
478 /* ena_com_phc_config - Configure PHC feature
479 * @ena_dev: ENA communication layer struct
480 * Configure PHC feature in driver and device
481 * @note: This method assumes PHC is supported by the device
482 * @return - 0 on success, negative value on failure
483 */
484 int ena_com_phc_config(struct ena_com_dev *ena_dev);
485
486 /* ena_com_phc_destroy - Destroy PHC feature
487 * @ena_dev: ENA communication layer struct
488 */
489 void ena_com_phc_destroy(struct ena_com_dev *ena_dev);
490
491 /* ena_com_phc_get - Retrieve PHC timestamp
492 * @ena_dev: ENA communication layer struct
493 * @timestamp: Retrieve PHC timestamp
494 * @return - 0 on success, negative value on failure
495 */
496 int ena_com_phc_get(struct ena_com_dev *ena_dev, u64 *timestamp);
497
498 /* ena_com_set_mmio_read_mode - Enable/disable the indirect mmio reg read mechanism
499 * @ena_dev: ENA communication layer struct
500 * @readless_supported: readless mode (enable/disable)
501 */
502 void ena_com_set_mmio_read_mode(struct ena_com_dev *ena_dev,
503 bool readless_supported);
504
505 /* ena_com_mmio_reg_read_request_write_dev_addr - Write the mmio reg read return
506 * value physical address.
507 * @ena_dev: ENA communication layer struct
508 */
509 void ena_com_mmio_reg_read_request_write_dev_addr(struct ena_com_dev *ena_dev);
510
511 /* ena_com_mmio_reg_read_request_destroy - Destroy the mmio reg read mechanism
512 * @ena_dev: ENA communication layer struct
513 */
514 void ena_com_mmio_reg_read_request_destroy(struct ena_com_dev *ena_dev);
515
516 /* ena_com_admin_init - Init the admin and the async queues
517 * @ena_dev: ENA communication layer struct
518 * @aenq_handlers: Those handlers to be called upon event.
519 *
520 * Initialize the admin submission and completion queues.
521 * Initialize the asynchronous events notification queues.
522 *
523 * @return - 0 on success, negative value on failure.
524 */
525 int ena_com_admin_init(struct ena_com_dev *ena_dev,
526 struct ena_aenq_handlers *aenq_handlers);
527
528 /* ena_com_admin_destroy - Destroy the admin and the async events queues.
529 * @ena_dev: ENA communication layer struct
530 *
531 * @note: Before calling this method, the caller must validate that the device
532 * won't send any additional admin completions/aenq.
533 * To achieve that, a FLR is recommended.
534 */
535 void ena_com_admin_destroy(struct ena_com_dev *ena_dev);
536
537 /* ena_com_dev_reset - Perform device FLR to the device.
538 * @ena_dev: ENA communication layer struct
539 * @reset_reason: Specify what is the trigger for the reset in case of an error.
540 *
541 * @return - 0 on success, negative value on failure.
542 */
543 int ena_com_dev_reset(struct ena_com_dev *ena_dev,
544 enum ena_regs_reset_reason_types reset_reason);
545
546 /* ena_com_create_io_queue - Create io queue.
547 * @ena_dev: ENA communication layer struct
548 * @ctx - create context structure
549 *
550 * Create the submission and the completion queues.
551 *
552 * @return - 0 on success, negative value on failure.
553 */
554 int ena_com_create_io_queue(struct ena_com_dev *ena_dev,
555 struct ena_com_create_io_ctx *ctx);
556
557 /* ena_com_destroy_io_queue - Destroy IO queue with the queue id - qid.
558 * @ena_dev: ENA communication layer struct
559 * @qid - the caller virtual queue id.
560 */
561 void ena_com_destroy_io_queue(struct ena_com_dev *ena_dev, u16 qid);
562
563 /* ena_com_get_io_handlers - Return the io queue handlers
564 * @ena_dev: ENA communication layer struct
565 * @qid - the caller virtual queue id.
566 * @io_sq - IO submission queue handler
567 * @io_cq - IO completion queue handler.
568 *
569 * @return - 0 on success, negative value on failure.
570 */
571 int ena_com_get_io_handlers(struct ena_com_dev *ena_dev, u16 qid,
572 struct ena_com_io_sq **io_sq,
573 struct ena_com_io_cq **io_cq);
574
575 /* ena_com_admin_aenq_enable - ENAble asynchronous event notifications
576 * @ena_dev: ENA communication layer struct
577 *
578 * After this method, aenq event can be received via AENQ.
579 */
580 void ena_com_admin_aenq_enable(struct ena_com_dev *ena_dev);
581
582 /* ena_com_set_admin_running_state - Set the state of the admin queue
583 * @ena_dev: ENA communication layer struct
584 *
585 * Change the state of the admin queue (enable/disable)
586 */
587 void ena_com_set_admin_running_state(struct ena_com_dev *ena_dev, bool state);
588
589 /* ena_com_get_admin_running_state - Get the admin queue state
590 * @ena_dev: ENA communication layer struct
591 *
592 * Retrieve the state of the admin queue (enable/disable)
593 *
594 * @return - current polling mode (enable/disable)
595 */
596 bool ena_com_get_admin_running_state(struct ena_com_dev *ena_dev);
597
598 /* ena_com_set_admin_polling_mode - Set the admin completion queue polling mode
599 * @ena_dev: ENA communication layer struct
600 * @polling: ENAble/Disable polling mode
601 *
602 * Set the admin completion mode.
603 */
604 void ena_com_set_admin_polling_mode(struct ena_com_dev *ena_dev, bool polling);
605
606 /* ena_com_get_admin_polling_mode - Get the admin completion queue polling mode
607 * @ena_dev: ENA communication layer struct
608 *
609 * Get the admin completion mode.
610 * If polling mode is on, ena_com_execute_admin_command will perform a
611 * polling on the admin completion queue for the commands completion,
612 * otherwise it will wait on wait event.
613 *
614 * @return state
615 */
616 bool ena_com_get_admin_polling_mode(struct ena_com_dev *ena_dev);
617
618 /* ena_com_set_admin_auto_polling_mode - Enable autoswitch to polling mode
619 * @ena_dev: ENA communication layer struct
620 * @polling: Enable/Disable polling mode
621 *
622 * Set the autopolling mode.
623 * If autopolling is on:
624 * In case of missing interrupt when data is available switch to polling.
625 */
626 void ena_com_set_admin_auto_polling_mode(struct ena_com_dev *ena_dev,
627 bool polling);
628
629 /* ena_com_admin_q_comp_intr_handler - admin queue interrupt handler
630 * @ena_dev: ENA communication layer struct
631 *
632 * This method goes over the admin completion queue and wakes up all the pending
633 * threads that wait on the commands wait event.
634 *
635 * @note: Should be called after MSI-X interrupt.
636 */
637 void ena_com_admin_q_comp_intr_handler(struct ena_com_dev *ena_dev);
638
639 /* ena_com_aenq_intr_handler - AENQ interrupt handler
640 * @ena_dev: ENA communication layer struct
641 *
642 * This method goes over the async event notification queue and calls the proper
643 * aenq handler.
644 */
645 void ena_com_aenq_intr_handler(struct ena_com_dev *ena_dev, void *data);
646
647 /* ena_com_abort_admin_commands - Abort all the outstanding admin commands.
648 * @ena_dev: ENA communication layer struct
649 *
650 * This method aborts all the outstanding admin commands.
651 * The caller should then call ena_com_wait_for_abort_completion to make sure
652 * all the commands were completed.
653 */
654 void ena_com_abort_admin_commands(struct ena_com_dev *ena_dev);
655
656 /* ena_com_wait_for_abort_completion - Wait for admin commands abort.
657 * @ena_dev: ENA communication layer struct
658 *
659 * This method waits until all the outstanding admin commands are completed.
660 */
661 void ena_com_wait_for_abort_completion(struct ena_com_dev *ena_dev);
662
663 /* ena_com_validate_version - Validate the device parameters
664 * @ena_dev: ENA communication layer struct
665 *
666 * This method verifies the device parameters are the same as the saved
667 * parameters in ena_dev.
668 * This method is useful after device reset, to validate the device mac address
669 * and the device offloads are the same as before the reset.
670 *
671 * @return - 0 on success negative value otherwise.
672 */
673 int ena_com_validate_version(struct ena_com_dev *ena_dev);
674
675 /* ena_com_get_link_params - Retrieve physical link parameters.
676 * @ena_dev: ENA communication layer struct
677 * @resp: Link parameters
678 *
679 * Retrieve the physical link parameters,
680 * like speed, auto-negotiation and full duplex support.
681 *
682 * @return - 0 on Success negative value otherwise.
683 */
684 int ena_com_get_link_params(struct ena_com_dev *ena_dev,
685 struct ena_admin_get_feat_resp *resp);
686
687 /* ena_com_get_dma_width - Retrieve physical dma address width the device
688 * supports.
689 * @ena_dev: ENA communication layer struct
690 *
691 * Retrieve the maximum physical address bits the device can handle.
692 *
693 * @return: > 0 on Success and negative value otherwise.
694 */
695 int ena_com_get_dma_width(struct ena_com_dev *ena_dev);
696
697 /* ena_com_set_aenq_config - Set aenq groups configurations
698 * @ena_dev: ENA communication layer struct
699 * @groups flag: bit fields flags of enum ena_admin_aenq_group.
700 *
701 * Configure which aenq event group the driver would like to receive.
702 *
703 * @return: 0 on Success and negative value otherwise.
704 */
705 int ena_com_set_aenq_config(struct ena_com_dev *ena_dev, u32 groups_flag);
706
707 /* ena_com_get_dev_attr_feat - Get device features
708 * @ena_dev: ENA communication layer struct
709 * @get_feat_ctx: returned context that contain the get features.
710 *
711 * @return: 0 on Success and negative value otherwise.
712 */
713 int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev,
714 struct ena_com_dev_get_features_ctx *get_feat_ctx);
715
716 /* ena_com_get_dev_basic_stats - Get device basic statistics
717 * @ena_dev: ENA communication layer struct
718 * @stats: stats return value
719 *
720 * @return: 0 on Success and negative value otherwise.
721 */
722 int ena_com_get_dev_basic_stats(struct ena_com_dev *ena_dev,
723 struct ena_admin_basic_stats *stats);
724
725 /* ena_com_get_eni_stats - Get extended network interface statistics
726 * @ena_dev: ENA communication layer struct
727 * @stats: stats return value
728 *
729 * @return: 0 on Success and negative value otherwise.
730 */
731 int ena_com_get_eni_stats(struct ena_com_dev *ena_dev,
732 struct ena_admin_eni_stats *stats);
733
734 /* ena_com_get_ena_srd_info - Get ENA SRD network interface statistics
735 * @ena_dev: ENA communication layer struct
736 * @info: ena srd stats and flags
737 *
738 * @return: 0 on Success and negative value otherwise.
739 */
740 int ena_com_get_ena_srd_info(struct ena_com_dev *ena_dev,
741 struct ena_admin_ena_srd_info *info);
742
743 /* ena_com_get_customer_metrics - Get customer metrics for network interface
744 * @ena_dev: ENA communication layer struct
745 * @buffer: buffer for returned customer metrics
746 * @len: size of the buffer
747 *
748 * @return: 0 on Success and negative value otherwise.
749 */
750 int ena_com_get_customer_metrics(struct ena_com_dev *ena_dev, char *buffer, u32 len);
751
752 /* ena_com_set_dev_mtu - Configure the device mtu.
753 * @ena_dev: ENA communication layer struct
754 * @mtu: mtu value
755 *
756 * @return: 0 on Success and negative value otherwise.
757 */
758 int ena_com_set_dev_mtu(struct ena_com_dev *ena_dev, u32 mtu);
759
760 /* ena_com_get_offload_settings - Retrieve the device offloads capabilities
761 * @ena_dev: ENA communication layer struct
762 * @offlad: offload return value
763 *
764 * @return: 0 on Success and negative value otherwise.
765 */
766 int ena_com_get_offload_settings(struct ena_com_dev *ena_dev,
767 struct ena_admin_feature_offload_desc *offload);
768
769 /* ena_com_rss_init - Init RSS
770 * @ena_dev: ENA communication layer struct
771 * @log_size: indirection log size
772 *
773 * Allocate RSS/RFS resources.
774 * The caller then can configure rss using ena_com_set_hash_function,
775 * ena_com_set_hash_ctrl and ena_com_indirect_table_set.
776 *
777 * @return: 0 on Success and negative value otherwise.
778 */
779 int ena_com_rss_init(struct ena_com_dev *ena_dev, u16 log_size);
780
781 /* ena_com_rss_destroy - Destroy rss
782 * @ena_dev: ENA communication layer struct
783 *
784 * Free all the RSS/RFS resources.
785 */
786 void ena_com_rss_destroy(struct ena_com_dev *ena_dev);
787
788 /* ena_com_get_current_hash_function - Get RSS hash function
789 * @ena_dev: ENA communication layer struct
790 *
791 * Return the current hash function.
792 * @return: 0 or one of the ena_admin_hash_functions values.
793 */
794 int ena_com_get_current_hash_function(struct ena_com_dev *ena_dev);
795
796 /* ena_com_fill_hash_function - Fill RSS hash function
797 * @ena_dev: ENA communication layer struct
798 * @func: The hash function (Toeplitz or crc)
799 * @key: Hash key (for toeplitz hash)
800 * @key_len: key length (max length 10 DW)
801 * @init_val: initial value for the hash function
802 *
803 * Fill the ena_dev resources with the desire hash function, hash key, key_len
804 * and key initial value (if needed by the hash function).
805 * To flush the key into the device the caller should call
806 * ena_com_set_hash_function.
807 *
808 * @return: 0 on Success and negative value otherwise.
809 */
810 int ena_com_fill_hash_function(struct ena_com_dev *ena_dev,
811 enum ena_admin_hash_functions func,
812 const u8 *key, u16 key_len, u32 init_val);
813
814 /* ena_com_set_hash_function - Flush the hash function and it dependencies to
815 * the device.
816 * @ena_dev: ENA communication layer struct
817 *
818 * Flush the hash function and it dependencies (key, key length and
819 * initial value) if needed.
820 *
821 * @note: Prior to this method the caller should call ena_com_fill_hash_function
822 *
823 * @return: 0 on Success and negative value otherwise.
824 */
825 int ena_com_set_hash_function(struct ena_com_dev *ena_dev);
826
827 /* ena_com_get_hash_function - Retrieve the hash function from the device.
828 * @ena_dev: ENA communication layer struct
829 * @func: hash function
830 *
831 * Retrieve the hash function from the device.
832 *
833 * @note: If the caller called ena_com_fill_hash_function but didn't flush
834 * it to the device, the new configuration will be lost.
835 *
836 * @return: 0 on Success and negative value otherwise.
837 */
838 int ena_com_get_hash_function(struct ena_com_dev *ena_dev,
839 enum ena_admin_hash_functions *func);
840
841 /* ena_com_get_hash_key - Retrieve the hash key
842 * @ena_dev: ENA communication layer struct
843 * @key: hash key
844 *
845 * Retrieve the hash key.
846 *
847 * @note: If the caller called ena_com_fill_hash_key but didn't flush
848 * it to the device, the new configuration will be lost.
849 *
850 * @return: 0 on Success and negative value otherwise.
851 */
852 int ena_com_get_hash_key(struct ena_com_dev *ena_dev, u8 *key);
853 /* ena_com_fill_hash_ctrl - Fill RSS hash control
854 * @ena_dev: ENA communication layer struct.
855 * @proto: The protocol to configure.
856 * @hash_fields: bit mask of ena_admin_flow_hash_fields
857 *
858 * Fill the ena_dev resources with the desire hash control (the ethernet
859 * fields that take part of the hash) for a specific protocol.
860 * To flush the hash control to the device, the caller should call
861 * ena_com_set_hash_ctrl.
862 *
863 * @return: 0 on Success and negative value otherwise.
864 */
865 int ena_com_fill_hash_ctrl(struct ena_com_dev *ena_dev,
866 enum ena_admin_flow_hash_proto proto,
867 u16 hash_fields);
868
869 /* ena_com_set_hash_ctrl - Flush the hash control resources to the device.
870 * @ena_dev: ENA communication layer struct
871 *
872 * Flush the hash control (the ethernet fields that take part of the hash)
873 *
874 * @note: Prior to this method the caller should call ena_com_fill_hash_ctrl.
875 *
876 * @return: 0 on Success and negative value otherwise.
877 */
878 int ena_com_set_hash_ctrl(struct ena_com_dev *ena_dev);
879
880 /* ena_com_get_hash_ctrl - Retrieve the hash control from the device.
881 * @ena_dev: ENA communication layer struct
882 * @proto: The protocol to retrieve.
883 * @fields: bit mask of ena_admin_flow_hash_fields.
884 *
885 * Retrieve the hash control from the device.
886 *
887 * @note: If the caller called ena_com_fill_hash_ctrl but didn't flush
888 * it to the device, the new configuration will be lost.
889 *
890 * @return: 0 on Success and negative value otherwise.
891 */
892 int ena_com_get_hash_ctrl(struct ena_com_dev *ena_dev,
893 enum ena_admin_flow_hash_proto proto,
894 u16 *fields);
895
896 /* ena_com_set_default_hash_ctrl - Set the hash control to a default
897 * configuration.
898 * @ena_dev: ENA communication layer struct
899 *
900 * Fill the ena_dev resources with the default hash control configuration.
901 * To flush the hash control to the device, the caller should call
902 * ena_com_set_hash_ctrl.
903 *
904 * @return: 0 on Success and negative value otherwise.
905 */
906 int ena_com_set_default_hash_ctrl(struct ena_com_dev *ena_dev);
907
908 /* ena_com_indirect_table_fill_entry - Fill a single entry in the RSS
909 * indirection table
910 * @ena_dev: ENA communication layer struct.
911 * @entry_idx - indirection table entry.
912 * @entry_value - redirection value
913 *
914 * Fill a single entry of the RSS indirection table in the ena_dev resources.
915 * To flush the indirection table to the device, the called should call
916 * ena_com_indirect_table_set.
917 *
918 * @return: 0 on Success and negative value otherwise.
919 */
920 int ena_com_indirect_table_fill_entry(struct ena_com_dev *ena_dev,
921 u16 entry_idx, u16 entry_value);
922
923 /* ena_com_indirect_table_set - Flush the indirection table to the device.
924 * @ena_dev: ENA communication layer struct
925 *
926 * Flush the indirection hash control to the device.
927 * Prior to this method the caller should call ena_com_indirect_table_fill_entry
928 *
929 * @return: 0 on Success and negative value otherwise.
930 */
931 int ena_com_indirect_table_set(struct ena_com_dev *ena_dev);
932
933 /* ena_com_indirect_table_get - Retrieve the indirection table from the device.
934 * @ena_dev: ENA communication layer struct
935 * @ind_tbl: indirection table
936 *
937 * Retrieve the RSS indirection table from the device.
938 *
939 * @note: If the caller called ena_com_indirect_table_fill_entry but didn't flush
940 * it to the device, the new configuration will be lost.
941 *
942 * @return: 0 on Success and negative value otherwise.
943 */
944 int ena_com_indirect_table_get(struct ena_com_dev *ena_dev, u32 *ind_tbl);
945
946 /* ena_com_allocate_host_info - Allocate host info resources.
947 * @ena_dev: ENA communication layer struct
948 *
949 * @return: 0 on Success and negative value otherwise.
950 */
951 int ena_com_allocate_host_info(struct ena_com_dev *ena_dev);
952
953 /* ena_com_allocate_debug_area - Allocate debug area.
954 * @ena_dev: ENA communication layer struct
955 * @debug_area_size - debug area size.
956 *
957 * @return: 0 on Success and negative value otherwise.
958 */
959 int ena_com_allocate_debug_area(struct ena_com_dev *ena_dev,
960 u32 debug_area_size);
961
962 /* ena_com_allocate_customer_metrics_buffer - Allocate customer metrics resources.
963 * @ena_dev: ENA communication layer struct
964 *
965 * @return: 0 on Success and negative value otherwise.
966 */
967 int ena_com_allocate_customer_metrics_buffer(struct ena_com_dev *ena_dev);
968
969 /* ena_com_delete_debug_area - Free the debug area resources.
970 * @ena_dev: ENA communication layer struct
971 *
972 * Free the allocated debug area.
973 */
974 void ena_com_delete_debug_area(struct ena_com_dev *ena_dev);
975
976 /* ena_com_delete_host_info - Free the host info resources.
977 * @ena_dev: ENA communication layer struct
978 *
979 * Free the allocated host info.
980 */
981 void ena_com_delete_host_info(struct ena_com_dev *ena_dev);
982
983 /* ena_com_delete_customer_metrics_buffer - Free the customer metrics resources.
984 * @ena_dev: ENA communication layer struct
985 *
986 * Free the allocated customer metrics area.
987 */
988 void ena_com_delete_customer_metrics_buffer(struct ena_com_dev *ena_dev);
989
990 /* ena_com_set_host_attributes - Update the device with the host
991 * attributes (debug area and host info) base address.
992 * @ena_dev: ENA communication layer struct
993 *
994 * @return: 0 on Success and negative value otherwise.
995 */
996 int ena_com_set_host_attributes(struct ena_com_dev *ena_dev);
997
998 /* ena_com_create_io_cq - Create io completion queue.
999 * @ena_dev: ENA communication layer struct
1000 * @io_cq - io completion queue handler
1001
1002 * Create IO completion queue.
1003 *
1004 * @return - 0 on success, negative value on failure.
1005 */
1006 int ena_com_create_io_cq(struct ena_com_dev *ena_dev,
1007 struct ena_com_io_cq *io_cq);
1008
1009 /* ena_com_destroy_io_cq - Destroy io completion queue.
1010 * @ena_dev: ENA communication layer struct
1011 * @io_cq - io completion queue handler
1012
1013 * Destroy IO completion queue.
1014 *
1015 * @return - 0 on success, negative value on failure.
1016 */
1017 int ena_com_destroy_io_cq(struct ena_com_dev *ena_dev,
1018 struct ena_com_io_cq *io_cq);
1019
1020 /* ena_com_execute_admin_command - Execute admin command
1021 * @admin_queue: admin queue.
1022 * @cmd: the admin command to execute.
1023 * @cmd_size: the command size.
1024 * @cmd_completion: command completion return value.
1025 * @cmd_comp_size: command completion size.
1026
1027 * Submit an admin command and then wait until the device returns a
1028 * completion.
1029 * The completion will be copied into cmd_comp.
1030 *
1031 * @return - 0 on success, negative value on failure.
1032 */
1033 int ena_com_execute_admin_command(struct ena_com_admin_queue *admin_queue,
1034 struct ena_admin_aq_entry *cmd,
1035 size_t cmd_size,
1036 struct ena_admin_acq_entry *cmd_comp,
1037 size_t cmd_comp_size);
1038
1039 /* ena_com_init_interrupt_moderation - Init interrupt moderation
1040 * @ena_dev: ENA communication layer struct
1041 *
1042 * @return - 0 on success, negative value on failure.
1043 */
1044 int ena_com_init_interrupt_moderation(struct ena_com_dev *ena_dev);
1045
1046 /* ena_com_interrupt_moderation_supported - Return if interrupt moderation
1047 * capability is supported by the device.
1048 *
1049 * @return - supported or not.
1050 */
1051 bool ena_com_interrupt_moderation_supported(struct ena_com_dev *ena_dev);
1052
1053 /* ena_com_update_nonadaptive_moderation_interval_tx - Update the
1054 * non-adaptive interval in Tx direction.
1055 * @ena_dev: ENA communication layer struct
1056 * @tx_coalesce_usecs: Interval in usec.
1057 *
1058 * @return - 0 on success, negative value on failure.
1059 */
1060 int ena_com_update_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev,
1061 u32 tx_coalesce_usecs);
1062
1063 /* ena_com_update_nonadaptive_moderation_interval_rx - Update the
1064 * non-adaptive interval in Rx direction.
1065 * @ena_dev: ENA communication layer struct
1066 * @rx_coalesce_usecs: Interval in usec.
1067 *
1068 * @return - 0 on success, negative value on failure.
1069 */
1070 int ena_com_update_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev,
1071 u32 rx_coalesce_usecs);
1072
1073 /* ena_com_get_nonadaptive_moderation_interval_tx - Retrieve the
1074 * non-adaptive interval in Tx direction.
1075 * @ena_dev: ENA communication layer struct
1076 *
1077 * @return - interval in usec
1078 */
1079 unsigned int ena_com_get_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev);
1080
1081 /* ena_com_get_nonadaptive_moderation_interval_rx - Retrieve the
1082 * non-adaptive interval in Rx direction.
1083 * @ena_dev: ENA communication layer struct
1084 *
1085 * @return - interval in usec
1086 */
1087 unsigned int ena_com_get_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev);
1088
1089 /* ena_com_config_dev_mode - Configure the placement policy of the device.
1090 * @ena_dev: ENA communication layer struct
1091 * @llq_features: LLQ feature descriptor, retrieve via
1092 * ena_com_get_dev_attr_feat.
1093 * @ena_llq_config: The default driver LLQ parameters configurations
1094 */
1095 int ena_com_config_dev_mode(struct ena_com_dev *ena_dev,
1096 struct ena_admin_feature_llq_desc *llq_features,
1097 struct ena_llq_configurations *llq_default_config);
1098
1099 /* ena_com_io_sq_to_ena_dev - Extract ena_com_dev using contained field io_sq.
1100 * @io_sq: IO submit queue struct
1101 *
1102 * @return - ena_com_dev struct extracted from io_sq
1103 */
ena_com_io_sq_to_ena_dev(struct ena_com_io_sq * io_sq)1104 static inline struct ena_com_dev *ena_com_io_sq_to_ena_dev(struct ena_com_io_sq *io_sq)
1105 {
1106 return container_of(io_sq, struct ena_com_dev, io_sq_queues[io_sq->qid]);
1107 }
1108
1109 /* ena_com_io_cq_to_ena_dev - Extract ena_com_dev using contained field io_cq.
1110 * @io_sq: IO submit queue struct
1111 *
1112 * @return - ena_com_dev struct extracted from io_sq
1113 */
ena_com_io_cq_to_ena_dev(struct ena_com_io_cq * io_cq)1114 static inline struct ena_com_dev *ena_com_io_cq_to_ena_dev(struct ena_com_io_cq *io_cq)
1115 {
1116 return container_of(io_cq, struct ena_com_dev, io_cq_queues[io_cq->qid]);
1117 }
1118
ena_com_get_adaptive_moderation_enabled(struct ena_com_dev * ena_dev)1119 static inline bool ena_com_get_adaptive_moderation_enabled(struct ena_com_dev *ena_dev)
1120 {
1121 return ena_dev->adaptive_coalescing;
1122 }
1123
ena_com_enable_adaptive_moderation(struct ena_com_dev * ena_dev)1124 static inline void ena_com_enable_adaptive_moderation(struct ena_com_dev *ena_dev)
1125 {
1126 ena_dev->adaptive_coalescing = true;
1127 }
1128
ena_com_disable_adaptive_moderation(struct ena_com_dev * ena_dev)1129 static inline void ena_com_disable_adaptive_moderation(struct ena_com_dev *ena_dev)
1130 {
1131 ena_dev->adaptive_coalescing = false;
1132 }
1133
1134 /* ena_com_get_cap - query whether device supports a capability.
1135 * @ena_dev: ENA communication layer struct
1136 * @cap_id: enum value representing the capability
1137 *
1138 * @return - true if capability is supported or false otherwise
1139 */
ena_com_get_cap(struct ena_com_dev * ena_dev,enum ena_admin_aq_caps_id cap_id)1140 static inline bool ena_com_get_cap(struct ena_com_dev *ena_dev,
1141 enum ena_admin_aq_caps_id cap_id)
1142 {
1143 return !!(ena_dev->capabilities & BIT(cap_id));
1144 }
1145
1146 /* ena_com_get_customer_metric_support - query whether device supports a given customer metric.
1147 * @ena_dev: ENA communication layer struct
1148 * @metric_id: enum value representing the customer metric
1149 *
1150 * @return - true if customer metric is supported or false otherwise
1151 */
ena_com_get_customer_metric_support(struct ena_com_dev * ena_dev,enum ena_admin_customer_metrics_id metric_id)1152 static inline bool ena_com_get_customer_metric_support(struct ena_com_dev *ena_dev,
1153 enum ena_admin_customer_metrics_id metric_id)
1154 {
1155 return !!(ena_dev->customer_metrics.supported_metrics & BIT64(metric_id));
1156 }
1157
1158 /* ena_com_get_customer_metric_count - return the number of supported customer metrics.
1159 * @ena_dev: ENA communication layer struct
1160 *
1161 * @return - the number of supported customer metrics
1162 */
ena_com_get_customer_metric_count(struct ena_com_dev * ena_dev)1163 static inline int ena_com_get_customer_metric_count(struct ena_com_dev *ena_dev)
1164 {
1165 return ENA_BITS_PER_U64(ena_dev->customer_metrics.supported_metrics);
1166 }
1167
1168 /* ena_com_update_intr_reg - Prepare interrupt register
1169 * @intr_reg: interrupt register to update.
1170 * @rx_delay_interval: Rx interval in usecs
1171 * @tx_delay_interval: Tx interval in usecs
1172 * @unmask: unmask enable/disable
1173 * @no_moderation_update: 0 - Indicates that any of the TX/RX intervals was
1174 * updated, 1 - otherwise
1175 *
1176 * Prepare interrupt update register with the supplied parameters.
1177 */
ena_com_update_intr_reg(struct ena_eth_io_intr_reg * intr_reg,u32 rx_delay_interval,u32 tx_delay_interval,bool unmask,bool no_moderation_update)1178 static inline void ena_com_update_intr_reg(struct ena_eth_io_intr_reg *intr_reg,
1179 u32 rx_delay_interval,
1180 u32 tx_delay_interval,
1181 bool unmask,
1182 bool no_moderation_update)
1183 {
1184 intr_reg->intr_control = 0;
1185 intr_reg->intr_control |= rx_delay_interval &
1186 ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK;
1187
1188 intr_reg->intr_control |=
1189 (tx_delay_interval << ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT)
1190 & ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK;
1191
1192 if (unmask)
1193 intr_reg->intr_control |= ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK;
1194
1195 intr_reg->intr_control |=
1196 (((u32)no_moderation_update) << ENA_ETH_IO_INTR_REG_NO_MODERATION_UPDATE_SHIFT) &
1197 ENA_ETH_IO_INTR_REG_NO_MODERATION_UPDATE_MASK;
1198 }
1199
ena_com_get_next_bounce_buffer(struct ena_com_io_bounce_buffer_control * bounce_buf_ctrl)1200 static inline u8 *ena_com_get_next_bounce_buffer(struct ena_com_io_bounce_buffer_control *bounce_buf_ctrl)
1201 {
1202 u16 size, buffers_num;
1203 u8 *buf;
1204
1205 size = bounce_buf_ctrl->buffer_size;
1206 buffers_num = bounce_buf_ctrl->buffers_num;
1207
1208 buf = bounce_buf_ctrl->base_buffer +
1209 (bounce_buf_ctrl->next_to_use++ & (buffers_num - 1)) * size;
1210
1211 prefetchw(bounce_buf_ctrl->base_buffer +
1212 (bounce_buf_ctrl->next_to_use & (buffers_num - 1)) * size);
1213
1214 return buf;
1215 }
1216
1217 #ifdef ENA_EXTENDED_STATS
1218 int ena_com_get_dev_extended_stats(struct ena_com_dev *ena_dev, char *buff,
1219 u32 len);
1220
1221 int ena_com_extended_stats_set_func_queue(struct ena_com_dev *ena_dev,
1222 u32 funct_queue);
1223 #endif
1224 #if defined(__cplusplus)
1225 }
1226 #endif /* __cplusplus */
1227 #endif /* !(ENA_COM) */
1228