1 /* $OpenBSD: lsi64854.c,v 1.12 2022/10/16 01:22:39 jsg Exp $ */
2 /* $NetBSD: lsi64854.c,v 1.18 2001/06/04 20:56:51 mrg Exp $ */
3
4 /*-
5 * Copyright (c) 1998 The NetBSD Foundation, Inc.
6 * All rights reserved.
7 *
8 * This code is derived from software contributed to The NetBSD Foundation
9 * by Paul Kranenburg.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 * POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/kernel.h>
36 #include <sys/errno.h>
37 #include <sys/device.h>
38
39 #include <machine/bus.h>
40 #include <machine/autoconf.h>
41 #include <machine/cpu.h>
42
43 #include <scsi/scsi_all.h>
44 #include <scsi/scsiconf.h>
45
46 #include <dev/ic/lsi64854reg.h>
47 #include <dev/ic/lsi64854var.h>
48
49 #include <dev/ic/ncr53c9xreg.h>
50 #include <dev/ic/ncr53c9xvar.h>
51
52 void lsi64854_reset(struct lsi64854_softc *);
53 int lsi64854_setup(struct lsi64854_softc *, caddr_t *, size_t *,
54 int, size_t *);
55 int lsi64854_setup_pp(struct lsi64854_softc *, caddr_t *, size_t *,
56 int, size_t *);
57 int lsi64854_scsi_intr(void *);
58 int lsi64854_pp_intr(void *);
59
60 #ifdef DEBUG
61 #define LDB_SCSI 1
62 #define LDB_ENET 2
63 #define LDB_PP 4
64 #define LDB_ANY 0xff
65 int lsi64854debug = 0;
66 #define DPRINTF(a,x) do { if (lsi64854debug & (a)) printf x ; } while (0)
67 #else
68 #define DPRINTF(a,x)
69 #endif
70
71 #define MAX_DMA_SZ (16*1024*1024)
72
73 /*
74 * Finish attaching this DMA device.
75 * Front-end must fill in these fields:
76 * sc_bustag
77 * sc_dmatag
78 * sc_regs
79 * sc_burst
80 * sc_channel (one of SCSI, ENET, PP)
81 * sc_client (one of SCSI, ENET, PP `soft_c' pointers)
82 */
83 int
lsi64854_attach(struct lsi64854_softc * sc)84 lsi64854_attach(struct lsi64854_softc *sc)
85 {
86 u_int32_t csr;
87 int rc;
88
89 /* Indirect functions */
90 switch (sc->sc_channel) {
91 case L64854_CHANNEL_SCSI:
92 sc->intr = lsi64854_scsi_intr;
93 sc->setup = lsi64854_setup;
94 break;
95 case L64854_CHANNEL_ENET:
96 sc->intr = lsi64854_enet_intr;
97 sc->setup = lsi64854_setup;
98 break;
99 case L64854_CHANNEL_PP:
100 sc->intr = lsi64854_pp_intr;
101 sc->setup = lsi64854_setup_pp;
102 break;
103 default:
104 printf("%s: unknown channel\n", sc->sc_dev.dv_xname);
105 }
106 sc->reset = lsi64854_reset;
107
108 /* Allocate a dmamap */
109 if ((rc = bus_dmamap_create(sc->sc_dmatag, MAX_DMA_SZ, 1, MAX_DMA_SZ,
110 0, BUS_DMA_WAITOK, &sc->sc_dmamap)) != 0) {
111 printf(": dma map create failed\n");
112 return (rc);
113 }
114
115 printf(": dma rev ");
116 csr = L64854_GCSR(sc);
117 sc->sc_rev = csr & L64854_DEVID;
118 switch (sc->sc_rev) {
119 case DMAREV_0:
120 printf("0");
121 break;
122 case DMAREV_ESC:
123 printf("esc");
124 break;
125 case DMAREV_1:
126 printf("1");
127 break;
128 case DMAREV_PLUS:
129 printf("1+");
130 break;
131 case DMAREV_2:
132 printf("2");
133 break;
134 case DMAREV_HME:
135 printf("fas");
136 break;
137 default:
138 printf("unknown (0x%x)", sc->sc_rev);
139 }
140
141 DPRINTF(LDB_ANY, (", burst 0x%x, csr 0x%x", sc->sc_burst, csr));
142 printf("\n");
143
144 return (0);
145 }
146
147 /*
148 * DMAWAIT waits while condition is true
149 */
150 #define DMAWAIT(SC, COND, MSG, DONTPANIC) do if (COND) { \
151 int count = 500000; \
152 while ((COND) && --count > 0) DELAY(1); \
153 if (count == 0) { \
154 printf("%s: line %d: CSR = 0x%lx\n", __FILE__, __LINE__, \
155 (u_long)L64854_GCSR(SC)); \
156 if (DONTPANIC) \
157 printf(MSG); \
158 else \
159 panic(MSG); \
160 } \
161 } while (0)
162
163 #define DMA_DRAIN(sc, dontpanic) do { \
164 u_int32_t csr; \
165 /* \
166 * DMA rev0 & rev1: we are not allowed to touch the DMA "flush" \
167 * and "drain" bits while it is still thinking about a \
168 * request. \
169 * other revs: D_ESC_R_PEND bit reads as 0 \
170 */ \
171 DMAWAIT(sc, L64854_GCSR(sc) & D_ESC_R_PEND, "R_PEND", dontpanic);\
172 if (sc->sc_rev != DMAREV_HME) { \
173 /* \
174 * Select drain bit based on revision \
175 * also clears errors and D_TC flag \
176 */ \
177 csr = L64854_GCSR(sc); \
178 if (sc->sc_rev == DMAREV_1 || sc->sc_rev == DMAREV_0) \
179 csr |= D_ESC_DRAIN; \
180 else \
181 csr |= L64854_INVALIDATE; \
182 \
183 L64854_SCSR(sc,csr); \
184 } \
185 /* \
186 * Wait for draining to finish \
187 * rev0 & rev1 call this PACKCNT \
188 */ \
189 DMAWAIT(sc, L64854_GCSR(sc) & L64854_DRAINING, "DRAINING", dontpanic);\
190 } while(0)
191
192 #define DMA_FLUSH(sc, dontpanic) do { \
193 u_int32_t csr; \
194 /* \
195 * DMA rev0 & rev1: we are not allowed to touch the DMA "flush" \
196 * and "drain" bits while it is still thinking about a \
197 * request. \
198 * other revs: D_ESC_R_PEND bit reads as 0 \
199 */ \
200 DMAWAIT(sc, L64854_GCSR(sc) & D_ESC_R_PEND, "R_PEND", dontpanic);\
201 csr = L64854_GCSR(sc); \
202 csr &= ~(L64854_WRITE|L64854_EN_DMA); /* no-ops on ENET */ \
203 csr |= L64854_INVALIDATE; /* XXX FAS ? */ \
204 L64854_SCSR(sc,csr); \
205 } while(0)
206
207 void
lsi64854_reset(struct lsi64854_softc * sc)208 lsi64854_reset(struct lsi64854_softc *sc)
209 {
210 u_int32_t csr;
211
212 DMA_FLUSH(sc, 1);
213 csr = L64854_GCSR(sc);
214
215 DPRINTF(LDB_ANY, ("lsi64854_reset: csr 0x%x\n", csr));
216
217 /*
218 * XXX is sync needed?
219 */
220 if (sc->sc_dmamap->dm_nsegs > 0)
221 bus_dmamap_unload(sc->sc_dmatag, sc->sc_dmamap);
222
223 if (sc->sc_rev == DMAREV_HME)
224 L64854_SCSR(sc, csr | D_HW_RESET_FAS366);
225
226
227 csr |= L64854_RESET; /* reset DMA */
228 L64854_SCSR(sc, csr);
229 DELAY(200); /* > 10 Sbus clocks(?) */
230
231 /*DMAWAIT1(sc); why was this here? */
232 csr = L64854_GCSR(sc);
233 csr &= ~L64854_RESET; /* de-assert reset line */
234 L64854_SCSR(sc, csr);
235 DELAY(5); /* allow a few ticks to settle */
236
237 csr = L64854_GCSR(sc);
238 csr |= L64854_INT_EN; /* enable interrupts */
239 if (sc->sc_rev > DMAREV_1 && sc->sc_channel == L64854_CHANNEL_SCSI) {
240 if (sc->sc_rev == DMAREV_HME)
241 csr |= D_TWO_CYCLE;
242 else
243 csr |= D_FASTER;
244 }
245
246 /* Set burst */
247 switch (sc->sc_rev) {
248 case DMAREV_HME:
249 case DMAREV_2:
250 csr &= ~L64854_BURST_SIZE;
251 if (sc->sc_burst == 32) {
252 csr |= L64854_BURST_32;
253 } else if (sc->sc_burst == 16) {
254 csr |= L64854_BURST_16;
255 } else {
256 csr |= L64854_BURST_0;
257 }
258 break;
259 case DMAREV_ESC:
260 csr |= D_ESC_AUTODRAIN; /* Auto-drain */
261 if (sc->sc_burst == 32) {
262 csr &= ~D_ESC_BURST;
263 } else
264 csr |= D_ESC_BURST;
265 break;
266 default:
267 break;
268 }
269 L64854_SCSR(sc, csr);
270
271 if (sc->sc_rev == DMAREV_HME) {
272 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR, 0);
273 sc->sc_dmactl = csr;
274 }
275 sc->sc_active = 0;
276
277 DPRINTF(LDB_ANY, ("lsi64854_reset: done, csr 0x%x\n", csr));
278 }
279
280
281 #define DMAMAX(a) (MAX_DMA_SZ - ((a) & (MAX_DMA_SZ-1)))
282 /*
283 * setup a dma transfer
284 */
285 int
lsi64854_setup(struct lsi64854_softc * sc,caddr_t * addr,size_t * len,int datain,size_t * dmasize)286 lsi64854_setup(struct lsi64854_softc *sc, caddr_t *addr, size_t *len,
287 int datain, size_t *dmasize)
288 {
289 u_int32_t csr;
290
291 DMA_FLUSH(sc, 0);
292
293 #if 0
294 DMACSR(sc) &= ~D_INT_EN;
295 #endif
296 sc->sc_dmaaddr = addr;
297 sc->sc_dmalen = len;
298
299 /*
300 * the rules say we cannot transfer more than the limit
301 * of this DMA chip (64k for old and 16Mb for new),
302 * and we cannot cross a 16Mb boundary.
303 */
304 *dmasize = sc->sc_dmasize =
305 min(*dmasize, DMAMAX((size_t) *sc->sc_dmaaddr));
306
307 DPRINTF(LDB_ANY, ("dma_setup: dmasize = %ld\n", (long)sc->sc_dmasize));
308
309 /*
310 * XXX what length?
311 */
312 if (sc->sc_rev == DMAREV_HME) {
313
314 L64854_SCSR(sc, sc->sc_dmactl | L64854_RESET);
315 L64854_SCSR(sc, sc->sc_dmactl);
316
317 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_CNT, *dmasize);
318 }
319
320 /* Program the DMA address */
321 if (sc->sc_dmasize) {
322 sc->sc_dvmaaddr = *sc->sc_dmaaddr;
323 if (bus_dmamap_load(sc->sc_dmatag, sc->sc_dmamap,
324 *sc->sc_dmaaddr, sc->sc_dmasize,
325 NULL /* kernel address */,
326 BUS_DMA_NOWAIT | BUS_DMA_STREAMING))
327 panic("%s: cannot allocate DVMA address",
328 sc->sc_dev.dv_xname);
329 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 0, sc->sc_dmasize,
330 datain
331 ? BUS_DMASYNC_PREREAD
332 : BUS_DMASYNC_PREWRITE);
333 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR,
334 sc->sc_dmamap->dm_segs[0].ds_addr);
335 }
336
337 if (sc->sc_rev == DMAREV_ESC) {
338 /* DMA ESC chip bug work-around */
339 long bcnt = sc->sc_dmasize;
340 long eaddr = bcnt + (long)*sc->sc_dmaaddr;
341 if ((eaddr & PGOFSET) != 0)
342 bcnt = roundup(bcnt, PAGE_SIZE);
343 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_CNT,
344 bcnt);
345 }
346
347 /* Setup DMA control register */
348 csr = L64854_GCSR(sc);
349
350 if (datain)
351 csr |= L64854_WRITE;
352 else
353 csr &= ~L64854_WRITE;
354 csr |= L64854_INT_EN;
355
356 if (sc->sc_rev == DMAREV_HME) {
357 csr |= (D_DSBL_SCSI_DRN | D_EN_DMA);
358 }
359
360 L64854_SCSR(sc, csr);
361
362 return (0);
363 }
364
365 /*
366 * Pseudo (chained) interrupt from the esp driver to kick the
367 * current running DMA transfer. Called from ncr53c9x_intr()
368 * for now.
369 *
370 * return 1 if it was a DMA continue.
371 */
372 int
lsi64854_scsi_intr(void * arg)373 lsi64854_scsi_intr(void *arg)
374 {
375 struct lsi64854_softc *sc = arg;
376 struct ncr53c9x_softc *nsc = sc->sc_client;
377 char bits[64];
378 int trans, resid;
379 u_int32_t csr;
380
381 csr = L64854_GCSR(sc);
382
383 DPRINTF(LDB_SCSI, ("%s: dmaintr: addr 0x%x, csr %b\n", sc->sc_dev.dv_xname,
384 bus_space_read_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR),
385 csr, DDMACSR_BITS));
386
387 if (csr & (D_ERR_PEND|D_SLAVE_ERR)) {
388 snprintf(bits, sizeof(bits), "%b", csr, DDMACSR_BITS);
389 printf("%s: error: csr=%s\n", sc->sc_dev.dv_xname, bits);
390 csr &= ~D_EN_DMA; /* Stop DMA */
391 /* Invalidate the queue; SLAVE_ERR bit is write-to-clear */
392 csr |= D_INVALIDATE|D_SLAVE_ERR;
393 L64854_SCSR(sc, csr);
394 return (-1);
395 }
396
397 /* This is an "assertion" :) */
398 if (sc->sc_active == 0)
399 panic("dmaintr: DMA wasn't active");
400
401 DMA_DRAIN(sc, 0);
402
403 /* DMA has stopped */
404 csr &= ~D_EN_DMA;
405 L64854_SCSR(sc, csr);
406 sc->sc_active = 0;
407
408 if (sc->sc_dmasize == 0) {
409 /* A "Transfer Pad" operation completed */
410 DPRINTF(LDB_SCSI, ("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n",
411 NCR_READ_REG(nsc, NCR_TCL) |
412 (NCR_READ_REG(nsc, NCR_TCM) << 8),
413 NCR_READ_REG(nsc, NCR_TCL),
414 NCR_READ_REG(nsc, NCR_TCM)));
415 return 0;
416 }
417
418 resid = 0;
419 /*
420 * If a transfer onto the SCSI bus gets interrupted by the device
421 * (e.g. for a SAVEPOINTER message), the data in the FIFO counts
422 * as residual since the NCR53C9X counter registers get decremented
423 * as bytes are clocked into the FIFO.
424 */
425 if (!(csr & D_WRITE) &&
426 (resid = (NCR_READ_REG(nsc, NCR_FFLAG) & NCRFIFO_FF)) != 0) {
427 DPRINTF(LDB_SCSI, ("dmaintr: empty esp FIFO of %d ", resid));
428 if (nsc->sc_rev == NCR_VARIANT_FAS366 &&
429 (NCR_READ_REG(nsc, NCR_CFG3) & NCRFASCFG3_EWIDE))
430 resid <<= 1;
431 }
432
433 if ((nsc->sc_espstat & NCRSTAT_TC) == 0) {
434 /*
435 * `Terminal count' is off, so read the residue
436 * out of the NCR53C9X counter registers.
437 */
438 resid += (NCR_READ_REG(nsc, NCR_TCL) |
439 (NCR_READ_REG(nsc, NCR_TCM) << 8) |
440 ((nsc->sc_cfg2 & NCRCFG2_FE)
441 ? (NCR_READ_REG(nsc, NCR_TCH) << 16)
442 : 0));
443
444 if (resid == 0 && sc->sc_dmasize == 65536 &&
445 (nsc->sc_cfg2 & NCRCFG2_FE) == 0)
446 /* A transfer of 64K is encoded as `TCL=TCM=0' */
447 resid = 65536;
448 }
449
450 trans = sc->sc_dmasize - resid;
451 if (trans < 0) { /* transferred < 0 ? */
452 #if 0
453 /*
454 * This situation can happen in perfectly normal operation
455 * if the ESP is reselected while using DMA to select
456 * another target. As such, don't print the warning.
457 */
458 printf("%s: xfer (%d) > req (%d)\n",
459 sc->sc_dev.dv_xname, trans, sc->sc_dmasize);
460 #endif
461 trans = sc->sc_dmasize;
462 }
463
464 DPRINTF(LDB_SCSI, ("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n",
465 NCR_READ_REG(nsc, NCR_TCL),
466 NCR_READ_REG(nsc, NCR_TCM),
467 (nsc->sc_cfg2 & NCRCFG2_FE)
468 ? NCR_READ_REG(nsc, NCR_TCH) : 0,
469 trans, resid));
470
471 if (sc->sc_dmamap->dm_nsegs > 0) {
472 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 0, sc->sc_dmasize,
473 (csr & D_WRITE) != 0
474 ? BUS_DMASYNC_POSTREAD
475 : BUS_DMASYNC_POSTWRITE);
476 bus_dmamap_unload(sc->sc_dmatag, sc->sc_dmamap);
477 }
478
479 *sc->sc_dmalen -= trans;
480 *sc->sc_dmaaddr += trans;
481
482 #if 0 /* this is not normal operation just yet */
483 if (*sc->sc_dmalen == 0 ||
484 nsc->sc_phase != nsc->sc_prevphase)
485 return 0;
486
487 /* and again */
488 dma_start(sc, sc->sc_dmaaddr, sc->sc_dmalen, DMACSR(sc) & D_WRITE);
489 return 1;
490 #endif
491 return 0;
492 }
493
494 /*
495 * Pseudo (chained) interrupt to le driver to handle DMA errors.
496 */
497 int
lsi64854_enet_intr(void * arg)498 lsi64854_enet_intr(void *arg)
499 {
500 struct lsi64854_softc *sc = arg;
501 char bits[64];
502 u_int32_t csr;
503 static int dodrain = 0;
504 int rv;
505
506 csr = L64854_GCSR(sc);
507
508 /* If the DMA logic shows an interrupt, claim it */
509 rv = ((csr & E_INT_PEND) != 0) ? 1 : 0;
510
511 if (csr & (E_ERR_PEND|E_SLAVE_ERR)) {
512 snprintf(bits, sizeof(bits), "%b", csr, EDMACSR_BITS);
513 printf("%s: error: csr=%s\n", sc->sc_dev.dv_xname, bits);
514 csr &= ~L64854_EN_DMA; /* Stop DMA */
515 /* Invalidate the queue; SLAVE_ERR bit is write-to-clear */
516 csr |= E_INVALIDATE|E_SLAVE_ERR;
517 L64854_SCSR(sc, csr);
518 DMA_RESET(sc);
519 dodrain = 1;
520 return (1);
521 }
522
523 if (dodrain) { /* XXX - is this necessary with D_DSBL_WRINVAL on? */
524 int i = 10;
525 csr |= E_DRAIN;
526 L64854_SCSR(sc, csr);
527 while (i-- > 0 && (L64854_GCSR(sc) & D_DRAINING))
528 delay(1);
529 }
530
531 return (rv | (*sc->sc_intrchain)(sc->sc_intrchainarg));
532 }
533
534 /*
535 * setup a dma transfer
536 */
537 int
lsi64854_setup_pp(struct lsi64854_softc * sc,caddr_t * addr,size_t * len,int datain,size_t * dmasize)538 lsi64854_setup_pp(struct lsi64854_softc *sc, caddr_t *addr, size_t *len,
539 int datain, size_t *dmasize)
540 {
541 u_int32_t csr;
542
543 DMA_FLUSH(sc, 0);
544
545 sc->sc_dmaaddr = addr;
546 sc->sc_dmalen = len;
547
548 DPRINTF(LDB_PP, ("%s: pp start %ld@%p,%d\n", sc->sc_dev.dv_xname,
549 (long)*sc->sc_dmalen, *sc->sc_dmaaddr, datain ? 1 : 0));
550
551 /*
552 * the rules say we cannot transfer more than the limit
553 * of this DMA chip (64k for old and 16Mb for new),
554 * and we cannot cross a 16Mb boundary.
555 */
556 *dmasize = sc->sc_dmasize =
557 min(*dmasize, DMAMAX((size_t) *sc->sc_dmaaddr));
558
559 DPRINTF(LDB_PP, ("dma_setup_pp: dmasize = %ld\n", (long)sc->sc_dmasize));
560
561 /* Program the DMA address */
562 if (sc->sc_dmasize) {
563 sc->sc_dvmaaddr = *sc->sc_dmaaddr;
564 if (bus_dmamap_load(sc->sc_dmatag, sc->sc_dmamap,
565 *sc->sc_dmaaddr, sc->sc_dmasize,
566 NULL /* kernel address */,
567 BUS_DMA_NOWAIT/*|BUS_DMA_COHERENT*/))
568 panic("%s: pp cannot allocate DVMA address",
569 sc->sc_dev.dv_xname);
570 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 0, sc->sc_dmasize,
571 datain
572 ? BUS_DMASYNC_PREREAD
573 : BUS_DMASYNC_PREWRITE);
574 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR,
575 sc->sc_dmamap->dm_segs[0].ds_addr);
576
577 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_CNT,
578 sc->sc_dmasize);
579 }
580
581 /* Setup DMA control register */
582 csr = L64854_GCSR(sc);
583 csr &= ~L64854_BURST_SIZE;
584 if (sc->sc_burst == 32) {
585 csr |= L64854_BURST_32;
586 } else if (sc->sc_burst == 16) {
587 csr |= L64854_BURST_16;
588 } else {
589 csr |= L64854_BURST_0;
590 }
591 csr |= P_EN_DMA|P_INT_EN|P_EN_CNT;
592 #if 0
593 /* This bit is read-only in PP csr register */
594 if (datain)
595 csr |= P_WRITE;
596 else
597 csr &= ~P_WRITE;
598 #endif
599 L64854_SCSR(sc, csr);
600
601 return (0);
602 }
603 /*
604 * Parallel port DMA interrupt.
605 */
606 int
lsi64854_pp_intr(void * arg)607 lsi64854_pp_intr(void *arg)
608 {
609 struct lsi64854_softc *sc = arg;
610 int ret, trans, resid = 0;
611 u_int32_t csr;
612
613 csr = L64854_GCSR(sc);
614
615 DPRINTF(LDB_PP, ("%s: pp intr: addr 0x%x, csr %b\n", sc->sc_dev.dv_xname,
616 bus_space_read_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR),
617 csr, PDMACSR_BITS));
618
619 if (csr & (P_ERR_PEND|P_SLAVE_ERR)) {
620 resid = bus_space_read_4(sc->sc_bustag, sc->sc_regs,
621 L64854_REG_CNT);
622 printf("%s: pp error: resid %d csr=%b\n", sc->sc_dev.dv_xname,
623 resid, csr, PDMACSR_BITS);
624 csr &= ~P_EN_DMA; /* Stop DMA */
625 /* Invalidate the queue; SLAVE_ERR bit is write-to-clear */
626 csr |= P_INVALIDATE|P_SLAVE_ERR;
627 L64854_SCSR(sc, csr);
628 return (1);
629 }
630
631 ret = (csr & P_INT_PEND) != 0;
632
633 if (sc->sc_active != 0) {
634 DMA_DRAIN(sc, 0);
635 resid = bus_space_read_4(sc->sc_bustag, sc->sc_regs,
636 L64854_REG_CNT);
637 }
638
639 /* DMA has stopped */
640 csr &= ~D_EN_DMA;
641 L64854_SCSR(sc, csr);
642 sc->sc_active = 0;
643
644 trans = sc->sc_dmasize - resid;
645 if (trans < 0) { /* transferred < 0 ? */
646 trans = sc->sc_dmasize;
647 }
648 *sc->sc_dmalen -= trans;
649 *sc->sc_dmaaddr += trans;
650
651 if (sc->sc_dmamap->dm_nsegs > 0) {
652 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 0, sc->sc_dmasize,
653 (csr & D_WRITE) != 0
654 ? BUS_DMASYNC_POSTREAD
655 : BUS_DMASYNC_POSTWRITE);
656 bus_dmamap_unload(sc->sc_dmatag, sc->sc_dmamap);
657 }
658
659 return (ret != 0);
660 }
661