1 /*****************************************************************************
2 *
3 * m4510.c
4 * Portable 4510 emulator V1.0beta1
5 *
6 * Copyright (c) 2000 Peter Trauner, all rights reserved
7 * documentation preliminary databook
8 * documentation by michael steil mist@c64.org
9 * available at ftp://ftp.funet.fi/pub/cbm/c65
10 *
11 * - This source code is released as freeware for non-commercial purposes.
12 * - You are free to use and redistribute this code in modified or
13 * unmodified form, provided you list me in the credits.
14 * - If you modify this source code, you must add a notice to each modified
15 * source file that it has been changed. If you're a nice person, you
16 * will clearly mark each change too. :)
17 * - If you wish to use this for commercial purposes, please contact me at
18 * pullmoll@t-online.de
19 * - The author of this copywritten work reserves the right to change the
20 * terms of its usage and license at any time, including retroactively
21 * - This entire notice must remain in the source code.
22 *
23 *****************************************************************************/
24
25 /*
26 c65 memory management
27 (reset)
28 c64 ff
29 c65 20 (interface)
30
31 a (c65 mode)
32 a:00 x:e3 y:00 z:b3
33 c65 64 (interface)
34 c64 ff
35
36 b (c65 dosmode?)
37 c65 65 (interface, full colorram)
38 a:00 x:11 y:80 z:31
39 c64 ff
40
41 c (?)
42 c64 07
43 a:00 x:00 y:00 z:00
44
45 a c65 mode
46
47 diskcontroller accesses
48
49
50 monitor
51 c64 ff
52 a:a0 x:82 y:00 z:83
53
54 c64 mode
55 c65 0
56 c65 2f:0 !
57 c64 ff
58 a:00 x:00 y:00 z:00
59
60 internal 8 mb to 64k switching (jmp routine in rom)
61 ( seams to be incomplete, in chapter 1 1megabyte memory mapper )
62 a x y z
63 g 0 00 e0 00 f0
64 g 10000 00 e1 00 f1
65 g 20000 00 e2 00 f2
66 g 30000 00 e3 00 f3
67 g 40000 00 e4 00 f4
68 g 50000 00 e5 00 f5
69 g 60000 00 e6 00 f6
70 .
71 .
72 g f0000 00 ef 00 ff
73 the same for 100000 .. 700000
74 g 800000 00 e3 00 b3
75
76 thesis:
77 a: ?0?0 0000
78 ? ? only in monitor mode set
79 x: xxxx address bits a19 .. a16 for memory accesses with a15 0 ?
80 0000 c64 mode
81 0001 dosmode
82 1110 c65 mode, plain ram access
83 (0000-1fff contains the switching code, so not switchable!?)
84 1000 monitor
85 1 map 6000-7fff
86 1 map 4000-5fff
87 1 map 2000-3fff
88 1 map 0000-1fff
89 y: ?000 0000
90 ? only in dos mode set
91 z: xxxx address bits a19 .. a16 for memory accesses with a15 1 ?
92 0000 c64 mode
93 0011 dosmode
94 1000 monitor
95 1011 c65 mode
96 1111 plain ram access
97 1 map e000-ffff
98 1 map c000-dfff
99 1 map a000-bfff
100 1 map 8000-9fff
101 */
102
103 #include <stdio.h>
104 #include "driver.h"
105 #include "state.h"
106 #include "mamedbg.h"
107 #include "m6502.h"
108 #include "m4510.h"
109
110 #include "ops02.h"
111 #include "opsc02.h"
112 #include "opsce02.h"
113 #include "ops4510.h"
114
115 #define M6502_NMI_VEC 0xfffa
116 #define M6502_RST_VEC 0xfffc
117 #define M6502_IRQ_VEC 0xfffe
118 #define M4510_RST_VEC M6502_RST_VEC
119 #define M4510_IRQ_VEC M6502_IRQ_VEC
120 #define M4510_NMI_VEC M6502_NMI_VEC
121
122 #define VERBOSE 0
123
124 #if VERBOSE
125 #define LOG(x) logerror x
126 #else
127 #define LOG(x)
128 #endif
129
130 #ifdef RUNTIME_LOADER
131 struct cpu_interface
132 m4510_interface=
133 CPU0(M4510, m4510, 1, 0,1.00,M4510_INT_NONE, M4510_INT_IRQ, M4510_INT_NMI, 8, 20, 0,20,LE,1, 3);
134
m4510_runtime_loader_init(void)135 extern void m4510_runtime_loader_init(void)
136 {
137 cpuintf[CPU_M4510]=m4510_interface;
138 }
139 #endif
140
141 /* Layout of the registers in the debugger */
142 static UINT8 m4510_reg_layout[] = {
143 M4510_A,M4510_X,M4510_Y,M4510_Z,M4510_S,M4510_PC,
144 M4510_MEM_LOW,
145 -1,
146 M4510_EA,M4510_ZP,M4510_NMI_STATE,M4510_IRQ_STATE, M4510_B,
147 M4510_P,
148 M4510_MEM_HIGH,
149 0
150 };
151
152 /* Layout of the debugger windows x,y,w,h */
153 static UINT8 m4510_win_layout[] = {
154 25, 0,55, 2, /* register window (top, right rows) */
155 0, 0,24,22, /* disassembler window (left colums) */
156 25, 3,55, 9, /* memory #1 window (right, upper middle) */
157 25,13,55, 9, /* memory #2 window (right, lower middle) */
158 0,23,80, 1, /* command line window (bottom rows) */
159 };
160
161 typedef struct {
162 void (**insn)(void); /* pointer to the function pointer table */
163 PAIR ppc; /* previous program counter */
164 PAIR pc; /* program counter */
165 PAIR sp; /* stack pointer (always 100 - 1FF) */
166 PAIR zp; /* zero page address */
167 /* contains B register zp.b.h */
168 PAIR ea; /* effective address */
169 UINT8 a; /* Accumulator */
170 UINT8 x; /* X index register */
171 UINT8 y; /* Y index register */
172 UINT8 z; /* Z index register */
173 UINT8 p; /* Processor status */
174 UINT8 pending_irq; /* nonzero if an IRQ is pending */
175 UINT8 after_cli; /* pending IRQ and last insn cleared I */
176 UINT8 nmi_state;
177 UINT8 irq_state;
178 UINT16 low, high;
179 UINT32 mem[8];
180 int (*irq_callback)(int irqline); /* IRQ callback */
181 } m4510_Regs;
182
183 int m4510_ICount = 0;
184
185 static m4510_Regs m4510;
186
187 /***************************************************************
188 * include the opcode macros, functions and tables
189 ***************************************************************/
190
m4510_cpu_readop(void)191 static INLINE int m4510_cpu_readop(void)
192 {
193 register UINT16 t=m4510.pc.w.l++;
194 return cpu_readop(M4510_MEM(t));
195 }
196
m4510_cpu_readop_arg(void)197 static INLINE int m4510_cpu_readop_arg(void)
198 {
199 register UINT16 t=m4510.pc.w.l++;
200 return cpu_readop_arg(M4510_MEM(t));
201 }
202
203 #define M4510
204 #include "t65ce02.c"
205
m4510_reset(void * param)206 void m4510_reset (void *param)
207 {
208 m4510.insn = insn4510;
209
210 /* wipe out the rest of the m65ce02 structure */
211 /* read the reset vector into PC */
212 /* reset z index and b bank */
213 PCL = RDMEM(M4510_RST_VEC);
214 PCH = RDMEM(M4510_RST_VEC+1);
215
216 /* after reset in 6502 compatibility mode */
217 m4510.sp.d = 0x01ff; /* high byte descriped in databook */
218 m4510.z = 0;
219 B = 0;
220 m4510.p = F_E|F_B|F_I|F_Z; /* set E, I and Z flags */
221 m4510.pending_irq = 0; /* nonzero if an IRQ is pending */
222 m4510.after_cli = 0; /* pending IRQ and last insn cleared I */
223 m4510.irq_callback = NULL;
224
225 /* don't know */
226 m4510.high=0x8200;
227 m4510.mem[7]=0x20000;
228
229 CHANGE_PC;
230 }
231
m4510_exit(void)232 void m4510_exit(void)
233 {
234 /* nothing to do yet */
235 }
236
m4510_get_context(void * dst)237 unsigned m4510_get_context (void *dst)
238 {
239 if( dst )
240 *(m4510_Regs*)dst = m4510;
241 return sizeof(m4510_Regs);
242 }
243
m4510_set_context(void * src)244 void m4510_set_context (void *src)
245 {
246 if( src )
247 {
248 m4510 = *(m4510_Regs*)src;
249 CHANGE_PC;
250 }
251 }
252
m4510_get_reg(int regnum)253 unsigned m4510_get_reg (int regnum)
254 {
255 switch( regnum )
256 {
257 case REG_PC: return M4510_MEM(PCD);
258 case M4510_PC: return m4510.pc.w.l;
259 case REG_SP: return S;
260 case M4510_S: return m4510.sp.w.l;
261 case M4510_P: return m4510.p;
262 case M4510_A: return m4510.a;
263 case M4510_X: return m4510.x;
264 case M4510_Y: return m4510.y;
265 case M4510_Z: return m4510.z;
266 case M4510_B: return m4510.zp.b.h;
267 case M4510_MEM_LOW: return m4510.low;
268 case M4510_MEM_HIGH: return m4510.high;
269 case M4510_MEM0: return m4510.mem[0];
270 case M4510_MEM1: return m4510.mem[1];
271 case M4510_MEM2: return m4510.mem[2];
272 case M4510_MEM3: return m4510.mem[3];
273 case M4510_MEM4: return m4510.mem[4];
274 case M4510_MEM5: return m4510.mem[5];
275 case M4510_MEM6: return m4510.mem[6];
276 case M4510_MEM7: return m4510.mem[7];
277 case M4510_EA: return m4510.ea.w.l;
278 case M4510_ZP: return m4510.zp.b.l;
279 case M4510_NMI_STATE: return m4510.nmi_state;
280 case M4510_IRQ_STATE: return m4510.irq_state;
281 case REG_PREVIOUSPC: return m4510.ppc.w.l;
282 default:
283 if( regnum <= REG_SP_CONTENTS )
284 {
285 unsigned offset = S + 2 * (REG_SP_CONTENTS - regnum);
286 if( offset < 0x1ff )
287 return RDMEM( offset ) | ( RDMEM( offset + 1 ) << 8 );
288 }
289 }
290 return 0;
291 }
292
m4510_set_reg(int regnum,unsigned val)293 void m4510_set_reg (int regnum, unsigned val)
294 {
295 switch( regnum )
296 {
297 case REG_PC: PCW = val; CHANGE_PC; break;
298 case M4510_PC: m4510.pc.w.l = val; break;
299 case REG_SP: S = val; break;
300 case M4510_S: m4510.sp.w.l = val; break;
301 case M4510_P: m4510.p = val; break;
302 case M4510_MEM_LOW:
303 m4510.low = val;
304 // change the memory registers
305 break;
306 case M4510_MEM_HIGH:
307 m4510.high = val;
308 // change the memory registers
309 break;
310 case M4510_A: m4510.a = val; break;
311 case M4510_X: m4510.x = val; break;
312 case M4510_Y: m4510.y = val; break;
313 case M4510_Z: m4510.z = val; break;
314 case M4510_B: m4510.zp.b.h = val; break;
315 case M4510_EA: m4510.ea.w.l = val; break;
316 case M4510_ZP: m4510.zp.b.l = val; break;
317 case M4510_NMI_STATE: m4510_set_irq_line( IRQ_LINE_NMI, val ); break;
318 case M4510_IRQ_STATE: m4510_set_irq_line( 0, val ); break;
319 default:
320 if( regnum <= REG_SP_CONTENTS )
321 {
322 unsigned offset = S + 2 * (REG_SP_CONTENTS - regnum);
323 if( offset < 0x1ff )
324 {
325 WRMEM( offset, val & 0xfff );
326 WRMEM( offset + 1, (val >> 8) & 0xff );
327 }
328 }
329 }
330 }
331
m4510_take_irq(void)332 static INLINE void m4510_take_irq(void)
333 {
334 if( !(P & F_I) )
335 {
336 EAD = M4510_IRQ_VEC;
337 m4510_ICount -= 7;
338 PUSH(PCH);
339 PUSH(PCL);
340 PUSH(P & ~F_B);
341 P = (P & ~F_D) | F_I; /* knock out D and set I flag */
342 PCL = RDMEM(EAD);
343 PCH = RDMEM(EAD+1);
344 LOG((errorlog,"M4510#%d takes IRQ ($%04x)\n", cpu_getactivecpu(), PCD));
345 /* call back the cpuintrf to let it clear the line */
346 if (m4510.irq_callback) (*m4510.irq_callback)(0);
347 CHANGE_PC;
348 }
349 m4510.pending_irq = 0;
350 }
351
m4510_execute(int cycles)352 int m4510_execute(int cycles)
353 {
354 m4510_ICount = cycles;
355
356 CHANGE_PC;
357
358 do
359 {
360 UINT8 op;
361 PPC = PCD;
362
363 CALL_MAME_DEBUG;
364
365 /* if an irq is pending, take it now */
366 if( m4510.pending_irq )
367 m4510_take_irq();
368
369 op = RDOP();
370 (*insn4510[op])();
371
372 /* check if the I flag was just reset (interrupts enabled) */
373 if( m4510.after_cli )
374 {
375 LOG((errorlog,"M4510#%d after_cli was >0", cpu_getactivecpu()));
376 m4510.after_cli = 0;
377 if (m4510.irq_state != CLEAR_LINE)
378 {
379 LOG((errorlog,": irq line is asserted: set pending IRQ\n"));
380 m4510.pending_irq = 1;
381 }
382 else
383 {
384 LOG((errorlog,": irq line is clear\n"));
385 }
386 }
387 else
388 if( m4510.pending_irq )
389 m4510_take_irq();
390
391 } while (m4510_ICount > 0);
392
393 return cycles - m4510_ICount;
394 }
395
m4510_set_irq_line(int irqline,int state)396 void m4510_set_irq_line(int irqline, int state)
397 {
398 if (irqline == IRQ_LINE_NMI)
399 {
400 if (m4510.nmi_state == state) return;
401 m4510.nmi_state = state;
402 if( state != CLEAR_LINE )
403 {
404 LOG((errorlog, "M4510#%d set_nmi_line(ASSERT)\n", cpu_getactivecpu()));
405 EAD = M4510_NMI_VEC;
406 m4510_ICount -= 7;
407 PUSH(PCH);
408 PUSH(PCL);
409 PUSH(P & ~F_B);
410 P = (P & ~F_D) | F_I; /* knock out D and set I flag */
411 PCL = RDMEM(EAD);
412 PCH = RDMEM(EAD+1);
413 LOG((errorlog,"M4510#%d takes NMI ($%04x)\n", cpu_getactivecpu(), PCD));
414 CHANGE_PC;
415 }
416 }
417 else
418 {
419 m4510.irq_state = state;
420 if( state != CLEAR_LINE )
421 {
422 LOG((errorlog, "M4510#%d set_irq_line(ASSERT)\n", cpu_getactivecpu()));
423 m4510.pending_irq = 1;
424 }
425 }
426 }
427
m4510_set_irq_callback(int (* callback)(int))428 void m4510_set_irq_callback(int (*callback)(int))
429 {
430 m4510.irq_callback = callback;
431 }
432
433 /****************************************************************************
434 * Return a formatted string for a register
435 ****************************************************************************/
m4510_info(void * context,int regnum)436 const char *m4510_info(void *context, int regnum)
437 {
438 static char buffer[16][47+1];
439 static int which = 0;
440 m4510_Regs *r = context;
441
442 which = (which+1) % 16;
443 buffer[which][0] = '\0';
444 if( !context )
445 r = &m4510;
446
447 switch( regnum )
448 {
449 case CPU_INFO_REG+M4510_PC: sprintf(buffer[which], "PC:%04X", r->pc.w.l); break;
450 case CPU_INFO_REG+M4510_S: sprintf(buffer[which], "S:%04X", r->sp.w.l); break;
451 case CPU_INFO_REG+M4510_P: sprintf(buffer[which], "P:%02X", r->p); break;
452 case CPU_INFO_REG+M4510_MEM_LOW: sprintf(buffer[which], "LO:%04X", r->low); break;
453 case CPU_INFO_REG+M4510_MEM_HIGH: sprintf(buffer[which], "HI:%04X", r->high); break;
454 case CPU_INFO_REG+M4510_A: sprintf(buffer[which], "A:%02X", r->a); break;
455 case CPU_INFO_REG+M4510_X: sprintf(buffer[which], "X:%02X", r->x); break;
456 case CPU_INFO_REG+M4510_Y: sprintf(buffer[which], "Y:%02X", r->y); break;
457 case CPU_INFO_REG+M4510_Z: sprintf(buffer[which], "Z:%02X", r->z); break;
458 case CPU_INFO_REG+M4510_B: sprintf(buffer[which], "B:%02X", r->zp.b.h); break;
459 case CPU_INFO_REG+M4510_EA: sprintf(buffer[which], "EA:%04X", r->ea.w.l); break;
460 case CPU_INFO_REG+M4510_ZP: sprintf(buffer[which], "ZP:%04X", r->zp.w.l); break;
461 case CPU_INFO_REG+M4510_NMI_STATE: sprintf(buffer[which], "NMI:%X", r->nmi_state); break;
462 case CPU_INFO_REG+M4510_IRQ_STATE: sprintf(buffer[which], "IRQ:%X", r->irq_state); break;
463 case CPU_INFO_FLAGS:
464 sprintf(buffer[which], "%c%c%c%c%c%c%c%c",
465 r->p & 0x80 ? 'N':'.',
466 r->p & 0x40 ? 'V':'.',
467 r->p & 0x20 ? 'E':'.',
468 r->p & 0x10 ? 'B':'.',
469 r->p & 0x08 ? 'D':'.',
470 r->p & 0x04 ? 'I':'.',
471 r->p & 0x02 ? 'Z':'.',
472 r->p & 0x01 ? 'C':'.');
473 break;
474 case CPU_INFO_NAME: return "M4510";
475 case CPU_INFO_FAMILY: return "CBM Semiconductor Group CSG 65CE02";
476 case CPU_INFO_VERSION: return "1.0beta";
477 case CPU_INFO_CREDITS:
478 return "Copyright (c) 1998 Juergen Buchmueller\n"
479 "Copyright (c) 2000 Peter Trauner\n"
480 "all rights reserved.";
481 case CPU_INFO_FILE: return __FILE__;
482 case CPU_INFO_REG_LAYOUT: return (const char*)m4510_reg_layout;
483 case CPU_INFO_WIN_LAYOUT: return (const char*)m4510_win_layout;
484 }
485 return buffer[which];
486 }
487
m4510_dasm(char * buffer,unsigned pc)488 unsigned m4510_dasm(char *buffer, unsigned pc)
489 {
490 #ifdef MAME_DEBUG
491 return Dasm4510( buffer, pc );
492 #else
493 sprintf( buffer, "$%02X", cpu_readop(pc) );
494 return 1;
495 #endif
496 }
497
498
m4510_init(void)499 extern void m4510_init(void){ return; }
500
501
502